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Merged
merged 13 commits into from
Apr 28, 2025
Merged

enum class rr_type #3001

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eb54502
make format
soheilshahrouz Apr 24, 2025
161f605
remove typedef t_rr_type
soheilshahrouz Apr 25, 2025
a6fe3fa
doxygen comment for Direction
soheilshahrouz Apr 25, 2025
6291e16
add vtr::array class
soheilshahrouz Apr 25, 2025
57d1006
make rr_node_typename of type vtr::array to index it only with e_rr_type
soheilshahrouz Apr 25, 2025
971f432
add default constructor to vtr::array
soheilshahrouz Apr 25, 2025
1e192c9
access rr_node_indices_ with e_rr_type instead of casting to size_t
soheilshahrouz Apr 25, 2025
c2d7545
add single argument constructor to vtr::array
soheilshahrouz Apr 25, 2025
0f8a76a
use vtr::array to index some arrays using e_rr_type
soheilshahrouz Apr 25, 2025
a126801
make format
soheilshahrouz Apr 25, 2025
27fbe98
avoid using e_rr_type and casting it in place_macro
soheilshahrouz Apr 25, 2025
2322aa6
add vtr::array to docs
soheilshahrouz Apr 27, 2025
9f139f1
Merge branch 'master' into temp_enum_class_rr_type
soheilshahrouz Apr 27, 2025
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72 changes: 36 additions & 36 deletions libs/librrgraph/src/base/check_rr_graph.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -154,22 +154,22 @@ void check_rr_graph(const RRGraphView& rr_graph,
* - CHAN -> IPIN connections (unique rr_node for IPIN nodes on multiple sides)
* - OPIN -> CHAN connections (unique rr_node for OPIN nodes on multiple sides)
*/
bool is_chan_to_chan = (rr_type == CHANX || rr_type == CHANY) && (to_rr_type == CHANY || to_rr_type == CHANX);
bool is_chan_to_ipin = (rr_type == CHANX || rr_type == CHANY) && to_rr_type == IPIN;
bool is_opin_to_chan = rr_type == OPIN && (to_rr_type == CHANX || to_rr_type == CHANY);
bool is_chan_to_chan = (rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY) && (to_rr_type == t_rr_type::CHANY || to_rr_type == t_rr_type::CHANX);
bool is_chan_to_ipin = (rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY) && to_rr_type == t_rr_type::IPIN;
bool is_opin_to_chan = rr_type == t_rr_type::OPIN && (to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY);
bool is_internal_edge = false;
if (is_flat) {
is_internal_edge = (rr_type == IPIN && to_rr_type == IPIN) || (rr_type == OPIN && to_rr_type == OPIN);
is_internal_edge = (rr_type == t_rr_type::IPIN && to_rr_type == t_rr_type::IPIN) || (rr_type == t_rr_type::OPIN && to_rr_type == t_rr_type::OPIN);
}
if (!(is_chan_to_chan || is_chan_to_ipin || is_opin_to_chan || is_internal_edge)) {
VPR_ERROR(VPR_ERROR_ROUTE,
"in check_rr_graph: node %d (%s) connects to node %d (%s) %zu times - multi-connections only expected for CHAN<->CHAN, CHAN->IPIN, OPIN->CHAN.\n",
inode, rr_node_typename[rr_type], to_node, rr_node_typename[to_rr_type], num_edges_to_node);
inode, rr_node_typename[(size_t)rr_type], to_node, rr_node_typename[(size_t)to_rr_type], num_edges_to_node);
}

//Between two wire segments
VTR_ASSERT_MSG(to_rr_type == CHANX || to_rr_type == CHANY || to_rr_type == IPIN, "Expect channel type or input pin type");
VTR_ASSERT_MSG(rr_type == CHANX || rr_type == CHANY || rr_type == OPIN, "Expect channel type or output pin type");
VTR_ASSERT_MSG(to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY || to_rr_type == t_rr_type::IPIN, "Expect channel type or input pin type");
VTR_ASSERT_MSG(rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY || rr_type == t_rr_type::OPIN, "Expect channel type or output pin type");

//While multiple connections between the same wires can be electrically legal,
//they are redundant if they are of the same switch type.
Expand All @@ -190,8 +190,8 @@ void check_rr_graph(const RRGraphView& rr_graph,
/* Redundant edges are not allowed for chan <-> chan connections
* but allowed for input pin <-> chan or output pin <-> chan connections
*/
if ((to_rr_type == CHANX || to_rr_type == CHANY)
&& (rr_type == CHANX || rr_type == CHANY)) {
if ((to_rr_type == t_rr_type::CHANX || to_rr_type == t_rr_type::CHANY)
&& (rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY)) {
auto switch_type = rr_graph.rr_switch_inf(RRSwitchId(kv.first)).type();

VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d has %d redundant connections to node %d of switch type %d (%s)",
Expand Down Expand Up @@ -240,22 +240,22 @@ void check_rr_graph(const RRGraphView& rr_graph,

t_physical_tile_type_ptr type = grid.get_physical_type({xlow, ylow, layer_num});

if (rr_type == IPIN || rr_type == OPIN) {
if (rr_type == t_rr_type::IPIN || rr_type == t_rr_type::OPIN) {
// #TODO: No edges are added for internal pins. However, they need to be checked somehow!
if (ptc_num >= type->num_pins) {
VTR_LOG_ERROR("in check_rr_graph: node %d (%s) type: %s is internal node.\n",
inode, rr_graph.node_type_string(rr_node), rr_node_typename[rr_type]);
inode, rr_graph.node_type_string(rr_node), rr_node_typename[(size_t)rr_type]);
}
}

if (rr_type != SOURCE) {
if (rr_type != t_rr_type::SOURCE) {
if (total_edges_to_node[inode] < 1 && !rr_node_is_global_clb_ipin(rr_graph, grid, rr_node)) {
/* A global CLB input pin will not have any edges, and neither will *
* a SOURCE or the start of a carry-chain. Anything else is an error.
* For simplicity, carry-chain input pin are entirely ignored in this test
*/
bool is_chain = false;
if (rr_type == IPIN) {
if (rr_type == t_rr_type::IPIN) {
for (const t_fc_specification& fc_spec : types[type->index].fc_specs) {
if (fc_spec.fc_value == 0 && fc_spec.seg_index == 0) {
is_chain = true;
Expand All @@ -269,11 +269,11 @@ void check_rr_graph(const RRGraphView& rr_graph,
|| (rr_graph.node_ylow(rr_node) == 1)
|| (rr_graph.node_xhigh(rr_node) == int(grid.width()) - 2)
|| (rr_graph.node_yhigh(rr_node) == int(grid.height()) - 2));
bool is_wire = (rr_graph.node_type(rr_node) == CHANX
|| rr_graph.node_type(rr_node) == CHANY);
bool is_wire = (rr_graph.node_type(rr_node) == t_rr_type::CHANX
|| rr_graph.node_type(rr_node) == t_rr_type::CHANY);

if (!is_chain && !is_fringe && !is_wire) {
if (rr_graph.node_type(rr_node) == IPIN || rr_graph.node_type(rr_node) == OPIN) {
if (rr_graph.node_type(rr_node) == t_rr_type::IPIN || rr_graph.node_type(rr_node) == t_rr_type::OPIN) {
if (has_adjacent_channel(rr_graph, grid, node)) {
auto block_type = grid.get_physical_type({rr_graph.node_xlow(rr_node),
rr_graph.node_ylow(rr_node),
Expand Down Expand Up @@ -320,7 +320,7 @@ static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const Device
rr_graph.node_ylow(inode),
rr_graph.node_layer(inode)});

if (rr_graph.node_type(inode) != IPIN)
if (rr_graph.node_type(inode) != t_rr_type::IPIN)
return (false);

ipin = rr_graph.node_pin_num(inode);
Expand Down Expand Up @@ -389,7 +389,7 @@ void check_rr_node(const RRGraphView& rr_graph,
type = grid.get_physical_type({xlow, ylow, layer_num});

switch (rr_type) {
case SOURCE:
case t_rr_type::SOURCE:
if (type == nullptr) {
VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow);
Expand All @@ -400,7 +400,7 @@ void check_rr_node(const RRGraphView& rr_graph,
"in check_rr_node: node %d (type %d) has endpoints (%d,%d) and (%d,%d)\n", inode, rr_type, xlow, ylow, xhigh, yhigh);
}
break;
case SINK: {
case t_rr_type::SINK: {
if (type == nullptr) {
VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow);
Expand All @@ -413,8 +413,8 @@ void check_rr_node(const RRGraphView& rr_graph,
}
break;
}
case IPIN:
case OPIN:
case t_rr_type::IPIN:
case t_rr_type::OPIN:
if (type == nullptr) {
VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow);
Expand All @@ -425,7 +425,7 @@ void check_rr_node(const RRGraphView& rr_graph,
}
break;

case CHANX:
case t_rr_type::CHANX:
if (xlow < 1 || xhigh > int(grid.width()) - 2 || yhigh > int(grid.height()) - 2 || yhigh != ylow) {
VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: CHANX out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh);
Expand All @@ -436,7 +436,7 @@ void check_rr_node(const RRGraphView& rr_graph,
}
break;

case CHANY:
case t_rr_type::CHANY:
if (xhigh > int(grid.width()) - 2 || ylow < 1 || yhigh > int(grid.height()) - 2 || xlow != xhigh) {
VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
"Error in check_rr_node: CHANY out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh);
Expand All @@ -459,12 +459,12 @@ void check_rr_node(const RRGraphView& rr_graph,
e_pin_type class_type = OPEN;
int class_num_pins = -1;
switch (rr_type) {
case SOURCE:
case SINK:
case t_rr_type::SOURCE:
case t_rr_type::SINK:
class_type = get_class_type_from_class_physical_num(type, ptc_num);
class_num_pins = get_class_num_pins_from_class_physical_num(type, ptc_num);
if (ptc_num >= class_max_ptc
|| class_type != ((rr_type == SOURCE) ? DRIVER : RECEIVER)) {
|| class_type != ((rr_type == t_rr_type::SOURCE) ? DRIVER : RECEIVER)) {
VPR_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num);
}
Expand All @@ -474,11 +474,11 @@ void check_rr_node(const RRGraphView& rr_graph,
}
break;

case OPIN:
case IPIN:
case t_rr_type::OPIN:
case t_rr_type::IPIN:
class_type = get_pin_type_from_pin_physical_num(type, ptc_num);
if (ptc_num >= pin_max_ptc
|| class_type != ((rr_type == OPIN) ? DRIVER : RECEIVER)) {
|| class_type != ((rr_type == t_rr_type::OPIN) ? DRIVER : RECEIVER)) {
VPR_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num);
}
Expand All @@ -488,14 +488,14 @@ void check_rr_node(const RRGraphView& rr_graph,
}
break;

case CHANX:
case CHANY:
case t_rr_type::CHANX:
case t_rr_type::CHANY:
if (route_type == DETAILED) {
nodes_per_chan = chan_width.max;
tracks_per_node = 1;
} else {
nodes_per_chan = 1;
tracks_per_node = ((rr_type == CHANX) ? chan_width.x_list[ylow] : chan_width.y_list[xlow]);
tracks_per_node = ((rr_type == t_rr_type::CHANX) ? chan_width.x_list[ylow] : chan_width.y_list[xlow]);
}

//if a chanx/chany has length 0, it means it is used to connect different dice together
Expand All @@ -522,7 +522,7 @@ void check_rr_node(const RRGraphView& rr_graph,
C = rr_graph.node_C(rr_node);
R = rr_graph.node_R(rr_node);

if (rr_type == CHANX || rr_type == CHANY) {
if (rr_type == t_rr_type::CHANX || rr_type == t_rr_type::CHANY) {
if (C < 0. || R < 0.) {
VPR_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: node %d of type %d has R = %g and C = %g.\n", inode, rr_type, R, C);
Expand All @@ -545,7 +545,7 @@ static void check_unbuffered_edges(const RRGraphView& rr_graph, int from_node) {
bool trans_matched;

from_rr_type = rr_graph.node_type(RRNodeId(from_node));
if (from_rr_type != CHANX && from_rr_type != CHANY)
if (from_rr_type != t_rr_type::CHANX && from_rr_type != t_rr_type::CHANY)
return;

from_num_edges = rr_graph.num_edges(RRNodeId(from_node));
Expand All @@ -554,7 +554,7 @@ static void check_unbuffered_edges(const RRGraphView& rr_graph, int from_node) {
to_node = size_t(rr_graph.edge_sink_node(RRNodeId(from_node), from_edge));
to_rr_type = rr_graph.node_type(RRNodeId(to_node));

if (to_rr_type != CHANX && to_rr_type != CHANY)
if (to_rr_type != t_rr_type::CHANX && to_rr_type != t_rr_type::CHANY)
continue;

from_switch_type = rr_graph.edge_switch(RRNodeId(from_node), from_edge);
Expand Down Expand Up @@ -592,7 +592,7 @@ static bool has_adjacent_channel(const RRGraphView& rr_graph, const DeviceGrid&
/* TODO: this function should be reworked later to adapt RRGraphView interface
* once xlow(), ylow(), side() APIs are implemented
*/
VTR_ASSERT(rr_graph.node_type(node.id()) == IPIN || rr_graph.node_type(node.id()) == OPIN);
VTR_ASSERT(rr_graph.node_type(node.id()) == t_rr_type::IPIN || rr_graph.node_type(node.id()) == e_rr_type::OPIN);

if ((rr_graph.node_xlow(node.id()) == 0 && !rr_graph.is_node_on_specific_side(node.id(), RIGHT)) //left device edge connects only along block's right side
|| (rr_graph.node_ylow(node.id()) == int(grid.height() - 1) && !rr_graph.is_node_on_specific_side(node.id(), BOTTOM)) //top device edge connects only along block's bottom side
Expand Down
4 changes: 2 additions & 2 deletions libs/librrgraph/src/base/check_rr_graph_obj.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,7 @@ static bool check_rr_graph_source_nodes(const RRGraph& rr_graph) {
*/
for (auto node : rr_graph.nodes()) {
/* Pass nodes whose types are not SOURCE */
if (SOURCE != rr_graph.node_type(node)) {
if (t_rr_type::SOURCE != rr_graph.node_type(node)) {
continue;
}
if ((0 != rr_graph.node_fan_in(node))
Expand Down Expand Up @@ -123,7 +123,7 @@ static bool check_rr_graph_sink_nodes(const RRGraph& rr_graph) {
*/
for (auto node : rr_graph.nodes()) {
/* Pass nodes whose types are not SINK */
if (SINK != rr_graph.node_type(node)) {
if (t_rr_type::SINK != rr_graph.node_type(node)) {
continue;
}
if ((0 == rr_graph.node_fan_in(node))
Expand Down
12 changes: 6 additions & 6 deletions libs/librrgraph/src/base/rr_graph_builder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -36,20 +36,20 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) {
node_ptc_num += node_twist * node_offset;
node_offset++;
switch (node_type) {
case SOURCE:
case SINK:
case CHANY:
case t_rr_type::SOURCE:
case t_rr_type::SINK:
case t_rr_type::CHANY:
node_lookup_.add_node(node, node_layer, ix, iy, node_type, node_ptc_num, TOTAL_2D_SIDES[0]);
break;
case CHANX:
case t_rr_type::CHANX:
/* Currently need to swap x and y for CHANX because of chan, seg convention
* TODO: Once the builders is reworked for use consistent (x, y) convention,
* the following swapping can be removed
*/
node_lookup_.add_node(node, node_layer, iy, ix, node_type, node_ptc_num, TOTAL_2D_SIDES[0]);
break;
case OPIN:
case IPIN:
case t_rr_type::OPIN:
case t_rr_type::IPIN:
for (const e_side& side : TOTAL_2D_SIDES) {
if (node_storage_.is_node_on_specific_side(node, side)) {
node_lookup_.add_node(node,node_layer, ix, iy, node_type, node_ptc_num, side);
Expand Down
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