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Support gPTP sync with PI control and fix i.MXRT1060 support #89234
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The RT10XX uses fixed 25M for PTP clock per RM. Verified on RT1060. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The enet handle in mac driver was not shared with ptp driver properly. This was causing wrong TX timestamp. This patch is to fix it. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The rate adjustment should be based on nomianl frequency, but not current frequency. Then any PTP stack with PID control could adjust frequency well. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Converted ENET_Ptp1588Configure to ENET_Ptp1588StartTimer during reset. This is to avoid configuring IRQ handlers again in hal driver with ENET_Ptp1588Configure. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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jukkar
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Apr 29, 2025
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Updated to v2. Changes include,
Thanks. |
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jukkar
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Current clock synchronization was always stepping clock. This was causing large offset, and discontiguous ptp hardware clock time. For TSN hardware, discontiguous ptp hardware clock time was not able to be used for other TSN protocols. This patch is to convert to frequency adjustment with a basic PI control algorithm. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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jukkar
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dleach02
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This was referenced May 6, 2025
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Labels
area: Clock Control
area: Clocks
area: Ethernet
area: Networking
platform: NXP Drivers
NXP Semiconductors, drivers
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I'm just starting to look at zephyr gPTP with a i.MXRT1060 EVK board on hand.
It looks like there are many problems in both drivers and gPTP stack.
So, I basically fixed key issues in ENET MAC/PTP drivers for RT1060. Also added a simple PI control algorithm to support continuous frequency adjustment in gPTP stack.
Finally the sync offset convergence on RT1060 was as below log. It's stable at about 100ns sync offset. (RT1060 PTP clock nominal frequency is 25M, 40ns period)
Thanks.