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[STA] Generating SDC Commands Post-Implementation #3016

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AlexandreSinger
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Added an option to have VPR generate an SDC file containing the timing commands required for an external timing analysis of the post- implementation netlist to match VPR's timing analysis.

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool docs Documentation lang-cpp C/C++ code labels May 1, 2025
Added an option to have VPR generate an SDC file containing the timing
commands required for an external timing analysis of the post-
implementation netlist to match VPR's timing analysis.
@AlexandreSinger
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@vaughnbetz This is the PR which adds the ability to generate a post-implementation SDC file, as I presented at the meeting this afternoon.

Based on the feedback, I have modified it to always set (non-virtual) clocks to propagated; even when the clock model is set to ideal.

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