A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
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May 20, 2022 - Verilog
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mips-processor
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5-stage pipelined 32-bit MIPS microprocessor in Verilog
verilog microprocessor computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project
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Apr 3, 2020 - Verilog
It's all coming back into focus!
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May 11, 2024 - Java
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
processor-architecture cpu vhdl isa cpu-model instruction-set-architecture mips-processor vhdl-modules risc-processor vhdl-code cpu-architecture multi-cycle processor-design
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Jun 19, 2021 - VHDL
Linux kernel source tree with the latest features and modifications to unleash the full potential of Ingenic processors.
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Mar 27, 2025 - C
Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree 💾
cpu algorithms storage mips processor assembly asm assembler parallelism mips-assembly assembly-language assembly-language-programming mips-architecture mips-processor assembly-x86 assemblyscript recursive-algorithms asm-mars computer-hardware
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Nov 10, 2024 - Assembly
A 5-stage pipelined mips32 processor
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May 9, 2017 - Verilog
🔮 A 16-bit MIPS Processor Implementation in Verilog HDL
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Aug 30, 2020 - Verilog
A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.
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Jun 21, 2021 - Verilog
🔮 A 32-bit MIPS Processor Implementation in Verilog HDL
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May 18, 2022 - Verilog
A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog
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Dec 26, 2020 - SystemVerilog
Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.
java mips mips-assembly mips-assembler mips32cpu mips-language mips-architecture mips-processor mips32 mips-instructions mips-simulator
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Feb 10, 2023 - HTML
MIPS simulator written in Go
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Aug 10, 2021 - Go
A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
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Sep 3, 2019 - Verilog
An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler
statistics stack static-code-analysis mips static-analysis stackoverflow static analyzer mips-assembly stack-overflow static-analyzer microchip mips32cpu mips-architecture xc32 mips-processor mips32 mips-instructions microchip-pic microchippic32
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Mar 30, 2022 - C
Solution for the assignment in Digital Design and Computer Architecture course including test benches running faster than official nightly tests.
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May 19, 2022 - VHDL
A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.
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Apr 20, 2017 - VHDL
Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding cont…
verilog computer-architecture mips-architecture mips-processor mips32 pipelined-processors mips-pipline-processor-verilog
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Mar 22, 2022 - Verilog
《计算机组成原理》课程设计，基于 MIPS 的流水线 CPU 系统设计。
cpu fpga pipeline mips architecture verilog course-project computer-architecture mips-architecture mips-processor homework-project
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Dec 17, 2024 - Verilog
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