Case Study: Combinational Circuits

Combinational circuits don't contain any element which could store statement informations. In other words, there are no registers in a combinational circuit. There are only connections or wires in a combinational circuit. In order that, we could consider the combinational circuit as a graph, the operator are nodes in the graph. In PyHCL, all connections are nodes in the graph. PyHCL would scan the module definition and construct the logic graph of the module. In this process, some pre-define elements may not appear in the graph. Those elements are redundant, and would not reflected to the result code.

3 to 8 decoder is a very classic combinational circuit. Also, the ALU we define in the previous section is also a classic combinational circuit. We give an example of 3 to 8 decoder:

class Decoder(Module):
    io = IO(
        a=Input(U.w(3)),
        d=Output(U.w(8))
    )

    io.d <<= U.w(8)(1) << io.a

We ignore some signals such as enable. In our decoder, the output is wire to a left shift operation between a literal unsigned integer 1 and input port a. There is no element would store any statement. The input value would directly reflected to the output. You may ask that where is the reset signal. In fact, the reset and clock signal are defined in the based Module class, which would make using PyHCL to define sequential circuit a little bit different to the Verilog. We would describe this in detail in next section, but now we continue to focus on combinational circuits.

Another classic combinational circuit is arbiter. Consider a two channel input arbiter, which has two input channel ch0 and ch1, and the priority of ch0 is greater than ch1. We give the example code of the arbiter:

class Arbiter(Module):
    io = IO(
        ready=Output(Bool),
        data=Output(U.w(16)),
        ch0_ready=Input(Bool),
        ch0_data=Input(U.w(16)),
        ch1_ready=Input(Bool),
        ch1_data=Input(U.w(16)),
    )

    io.ready <<= io.ch0_ready | io.ch1_ready
    io.data <<= Mux(io.ch0_ready, io.ch0_data, io.ch1_data)

Mux is a pre-defined PyHCL utils, it is a classic combinational component, which select a input channel according to the condition. Those pre-defined components would describe in advanced topics.

We have give two classic combinational circuits for examples. Infact, combinational circuit is easy for learning and design. In the end, we give an exercise for readers: try to design a 8-3 encoder in PyHCL, we give the I/O ports definition of the encoder:

class Encoder(Module):
  	io = IO(
    		a=Input(U.w(8)),
      	s=Output(U.w(3)),
    )
    
    # ...

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