From 81a73cd8ef6433cb66a7cdb3fe1d5b3afa96ea83 Mon Sep 17 00:00:00 2001 From: Rongbo Zhang Date: Mon, 10 Feb 2025 20:08:13 -0500 Subject: [PATCH 1/2] [packer] Changing the vector of candidate molecules into LazyPopUniquePriorityQueue. The class LazyPopUniquePriorityQueue is a priority queue that allows for lazy deletion of elements. It is implemented using a vector and 2 sets, one set keeps track of the elements in the queue, and the other set keeps track of the elements that are pending deletion. The queue is sorted by the sort-value(SV) of the elements, and the elements are stored in a vector. The set is used to keep track of the elements that are pending deletion, so that they can be removed from the queue when they are popped. The class definiation can be found in vpr/src/util/lazy_pop_unique_priority_queue.h Currently, the class supports the following functions: LazyPopUniquePriorityQueue::push(): Pushes a key-sort-value (K-SV) pair into the priority queue and adds the key to the tracking set. LazyPopUniquePriorityQueue::pop(): Returns the K-SV pair with the highest SV whose key is not pending deletion. LazyPopUniquePriorityQueue::remove(): Removes an element from the priority queue immediately. LazyPopUniquePriorityQueue::remove_at_pop_time(): Removes an element from the priority queue when it is popped. LazyPopUniquePriorityQueue::empty(): Returns whether the queue is empty. LazyPopUniquePriorityQueue::clear(): Clears the priority queue vector and the tracking sets. LazyPopUniquePriorityQueue::size(): Returns the number of elements in the queue. LazyPopUniquePriorityQueue::contains(): Returns true if the key is in the queue, false otherwise. --- vpr/src/pack/greedy_candidate_selector.cpp | 131 ++++------- vpr/src/pack/greedy_candidate_selector.h | 35 ++- vpr/src/util/lazy_pop_unique_priority_queue.h | 216 ++++++++++++++++++ 3 files changed, 285 insertions(+), 97 deletions(-) create mode 100644 vpr/src/util/lazy_pop_unique_priority_queue.h diff --git a/vpr/src/pack/greedy_candidate_selector.cpp b/vpr/src/pack/greedy_candidate_selector.cpp index 10255890d6..3874b66d45 100644 --- a/vpr/src/pack/greedy_candidate_selector.cpp +++ b/vpr/src/pack/greedy_candidate_selector.cpp @@ -64,7 +64,6 @@ static void add_molecule_to_pb_stats_candidates( PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats, t_logical_block_type_ptr cluster_type, - int max_queue_size, AttractionInfo& attraction_groups, const Prepacker& prepacker, const AtomNetlist& atom_netlist, @@ -219,13 +218,11 @@ ClusterGainStats GreedyCandidateSelector::create_cluster_gain_stats( // Initialize the cluster gain stats. ClusterGainStats cluster_gain_stats; cluster_gain_stats.seed_molecule_id = cluster_seed_mol_id; - cluster_gain_stats.num_feasible_blocks = NOT_VALID; cluster_gain_stats.has_done_connectivity_and_timing = false; - // TODO: The reason this is being resized and not reserved is due to legacy - // code which should be updated. - cluster_gain_stats.feasible_blocks.resize(packer_opts_.feasible_block_array_size); - for (int i = 0; i < packer_opts_.feasible_block_array_size; i++) - cluster_gain_stats.feasible_blocks[i] = PackMoleculeId::INVALID(); + cluster_gain_stats.initial_search_for_feasible_blocks = true; + cluster_gain_stats.num_candidates_proposed = 0; + cluster_gain_stats.candidates_propose_limit = packer_opts_.feasible_block_array_size; + cluster_gain_stats.feasible_blocks.clear(); cluster_gain_stats.tie_break_high_fanout_net = AtomNetId::INVALID(); cluster_gain_stats.explore_transitive_fanout = true; @@ -288,8 +285,10 @@ void GreedyCandidateSelector::update_cluster_gain_stats_candidate_success( AttractGroupId atom_grp_id = attraction_groups.get_atom_attraction_group(blk_id); /* reset list of feasible blocks */ - cluster_gain_stats.num_feasible_blocks = NOT_VALID; cluster_gain_stats.has_done_connectivity_and_timing = false; + cluster_gain_stats.initial_search_for_feasible_blocks = true; + cluster_gain_stats.num_candidates_proposed = 0; + cluster_gain_stats.feasible_blocks.clear(); /* TODO: Allow clusters to have more than one attraction group. */ if (atom_grp_id.is_valid()) cluster_gain_stats.attraction_grp_id = atom_grp_id; @@ -684,8 +683,8 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( */ // 1. Find unpacked molecules based on criticality and strong connectedness (connected by low fanout nets) with current cluster - if (cluster_gain_stats.num_feasible_blocks == NOT_VALID) { - cluster_gain_stats.num_feasible_blocks = 0; + if (cluster_gain_stats.initial_search_for_feasible_blocks) { + cluster_gain_stats.initial_search_for_feasible_blocks = false; add_cluster_molecule_candidates_by_connectivity_and_timing(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -695,7 +694,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( if (packer_opts_.prioritize_transitive_connectivity) { // 2. Find unpacked molecules based on transitive connections (eg. 2 hops away) with current cluster - if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.explore_transitive_fanout) { + if (cluster_gain_stats.feasible_blocks.empty() && cluster_gain_stats.explore_transitive_fanout) { add_cluster_molecule_candidates_by_transitive_connectivity(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -703,7 +702,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } // 3. Find unpacked molecules based on weak connectedness (connected by high fanout nets) with current cluster - if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.tie_break_high_fanout_net) { + if (cluster_gain_stats.feasible_blocks.empty() && cluster_gain_stats.tie_break_high_fanout_net) { add_cluster_molecule_candidates_by_highfanout_connectivity(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -711,7 +710,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } } else { //Reverse order // 3. Find unpacked molecules based on weak connectedness (connected by high fanout nets) with current cluster - if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.tie_break_high_fanout_net) { + if (cluster_gain_stats.feasible_blocks.empty() && cluster_gain_stats.tie_break_high_fanout_net) { add_cluster_molecule_candidates_by_highfanout_connectivity(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -719,7 +718,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } // 2. Find unpacked molecules based on transitive connections (eg. 2 hops away) with current cluster - if (cluster_gain_stats.num_feasible_blocks == 0 && cluster_gain_stats.explore_transitive_fanout) { + if (cluster_gain_stats.feasible_blocks.empty() && cluster_gain_stats.explore_transitive_fanout) { add_cluster_molecule_candidates_by_transitive_connectivity(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -728,7 +727,7 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } // 4. Find unpacked molecules based on attraction group of the current cluster (if the cluster has an attraction group) - if (cluster_gain_stats.num_feasible_blocks == 0) { + if (cluster_gain_stats.feasible_blocks.empty()) { add_cluster_molecule_candidates_by_attraction_group(cluster_gain_stats, cluster_id, cluster_legalizer, @@ -736,15 +735,25 @@ PackMoleculeId GreedyCandidateSelector::get_next_candidate_for_cluster( } /* Grab highest gain molecule */ - // If this was a vector, this would just be a pop_back. PackMoleculeId best_molecule = PackMoleculeId::INVALID(); - if (cluster_gain_stats.num_feasible_blocks > 0) { - cluster_gain_stats.num_feasible_blocks--; - int index = cluster_gain_stats.num_feasible_blocks; - best_molecule = cluster_gain_stats.feasible_blocks[index]; + // If there are feasible blocks being proposed and the number of suggestions did not reach the limit. + // Get the block with highest gain from the top of the priority queue. + if (!cluster_gain_stats.feasible_blocks.empty() && !cluster_gain_stats.current_stage_candidates_proposed_limit_reached()) { + best_molecule = cluster_gain_stats.feasible_blocks.pop().first; + VTR_ASSERT(best_molecule != PackMoleculeId::INVALID()); + cluster_gain_stats.num_candidates_proposed++; VTR_ASSERT(!cluster_legalizer.is_mol_clustered(best_molecule)); } + // If we have no feasible blocks, or we have reached the limit of number of pops, + // then we need to clear the feasible blocks list and reset the number of pops. + // This ensures that we can continue searching for feasible blocks for the remaining + // steps (2.transitive, 3.high fanout, 4.attraction group). + if (cluster_gain_stats.feasible_blocks.empty() || cluster_gain_stats.current_stage_candidates_proposed_limit_reached()) { + cluster_gain_stats.feasible_blocks.clear(); + cluster_gain_stats.num_candidates_proposed = 0; + } + // If we are allowing unrelated clustering and no molecule has been found, // get unrelated candidate for cluster. if (allow_unrelated_clustering_ && best_molecule == PackMoleculeId::INVALID()) { @@ -778,7 +787,9 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_connectivity_an LegalizationClusterId legalization_cluster_id, const ClusterLegalizer& cluster_legalizer, AttractionInfo& attraction_groups) { - cluster_gain_stats.explore_transitive_fanout = true; /* If no legal molecules found, enable exploration of molecules two hops away */ + + cluster_gain_stats.explore_transitive_fanout = true; /* If no legal molecules found, enable exploration of molecules two hops away */ + cluster_gain_stats.candidates_propose_limit = packer_opts_.feasible_block_array_size; // set the limit of candidates to propose for (AtomBlockId blk_id : cluster_gain_stats.marked_blocks) { // Get the molecule that contains this block. @@ -789,7 +800,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_connectivity_an add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - packer_opts_.feasible_block_array_size, attraction_groups, prepacker_, atom_netlist_, @@ -805,6 +815,7 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_transitive_conn AttractionInfo& attraction_groups) { //TODO: For now, only done by fan-out; should also consider fan-in cluster_gain_stats.explore_transitive_fanout = false; + cluster_gain_stats.candidates_propose_limit = std::min(packer_opts_.feasible_block_array_size, AAPACK_MAX_TRANSITIVE_EXPLORE); // set the limit of candidates to propose /* First time finding transitive fanout candidates therefore alloc and load them */ load_transitive_fanout_candidates(cluster_gain_stats, @@ -818,8 +829,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_transitive_conn add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - std::min(packer_opts_.feasible_block_array_size, - AAPACK_MAX_TRANSITIVE_EXPLORE), attraction_groups, prepacker_, atom_netlist_, @@ -838,6 +847,7 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_highfanout_conn * related blocks */ AtomNetId net_id = cluster_gain_stats.tie_break_high_fanout_net; + cluster_gain_stats.candidates_propose_limit = std::min(packer_opts_.feasible_block_array_size, AAPACK_MAX_TRANSITIVE_EXPLORE); // set the limit of candidates to propose int count = 0; for (AtomPinId pin_id : atom_netlist_.net_pins(net_id)) { @@ -852,8 +862,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_highfanout_conn add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - std::min(packer_opts_.feasible_block_array_size, - AAPACK_MAX_HIGH_FANOUT_EXPLORE), attraction_groups, prepacker_, atom_netlist_, @@ -881,6 +889,7 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou * group molecules for candidate molecules. */ AttractGroupId grp_id = cluster_gain_stats.attraction_grp_id; + cluster_gain_stats.candidates_propose_limit = packer_opts_.feasible_block_array_size; // set the limit of candidates to propose if (grp_id == AttractGroupId::INVALID()) { return; } @@ -913,7 +922,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - packer_opts_.feasible_block_array_size, attraction_groups, prepacker_, atom_netlist_, @@ -935,7 +943,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou add_molecule_to_pb_stats_candidates(molecule_id, cluster_gain_stats, cluster_legalizer.get_cluster_type(legalization_cluster_id), - packer_opts_.feasible_block_array_size, attraction_groups, prepacker_, atom_netlist_, @@ -950,7 +957,6 @@ void GreedyCandidateSelector::add_cluster_molecule_candidates_by_attraction_grou static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats, t_logical_block_type_ptr cluster_type, - int max_queue_size, AttractionInfo& attraction_groups, const Prepacker& prepacker, const AtomNetlist& atom_netlist, @@ -1004,45 +1010,18 @@ static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, } } - for (int i = 0; i < cluster_gain_stats.num_feasible_blocks; i++) { - if (cluster_gain_stats.feasible_blocks[i] == molecule_id) { - return; // already in queue, do nothing - } + // if already in queue, do nothing + if (cluster_gain_stats.feasible_blocks.contains(molecule_id)) { + return; } - if (cluster_gain_stats.num_feasible_blocks >= max_queue_size - 1) { - /* maximum size for array, remove smallest gain element and sort */ - if (get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) > get_molecule_gain(cluster_gain_stats.feasible_blocks[0], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { - /* single loop insertion sort */ - int j; - for (j = 0; j < cluster_gain_stats.num_feasible_blocks - 1; j++) { - if (get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) <= get_molecule_gain(cluster_gain_stats.feasible_blocks[j + 1], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { - cluster_gain_stats.feasible_blocks[j] = molecule_id; - break; - } else { - cluster_gain_stats.feasible_blocks[j] = cluster_gain_stats.feasible_blocks[j + 1]; - } - } - if (j == cluster_gain_stats.num_feasible_blocks - 1) { - cluster_gain_stats.feasible_blocks[j] = molecule_id; - } - } - } else { - /* Expand array and single loop insertion sort */ - int j; - for (j = cluster_gain_stats.num_feasible_blocks - 1; j >= 0; j--) { - if (get_molecule_gain(cluster_gain_stats.feasible_blocks[j], cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) > get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx)) { - cluster_gain_stats.feasible_blocks[j + 1] = cluster_gain_stats.feasible_blocks[j]; - } else { - cluster_gain_stats.feasible_blocks[j + 1] = molecule_id; - break; - } - } - if (j < 0) { - cluster_gain_stats.feasible_blocks[0] = molecule_id; - } - cluster_gain_stats.num_feasible_blocks++; + for (std::pair& feasible_block : cluster_gain_stats.feasible_blocks.heap) { + VTR_ASSERT_DEBUG(get_molecule_gain(feasible_block.first, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx) == feasible_block.second); } + + // Insert the molecule into the queue sorted by gain, and maintain the heap property + float molecule_gain = get_molecule_gain(molecule_id, cluster_gain_stats, cluster_att_grp, attraction_groups, num_molecule_failures, prepacker, atom_netlist, appack_ctx); + cluster_gain_stats.feasible_blocks.push(molecule_id, molecule_gain); } /* @@ -1053,27 +1032,7 @@ static void add_molecule_to_pb_stats_candidates(PackMoleculeId molecule_id, */ static void remove_molecule_from_pb_stats_candidates(PackMoleculeId molecule_id, ClusterGainStats& cluster_gain_stats) { - int molecule_index; - bool found_molecule = false; - - //find the molecule index - for (int i = 0; i < cluster_gain_stats.num_feasible_blocks; i++) { - if (cluster_gain_stats.feasible_blocks[i] == molecule_id) { - found_molecule = true; - molecule_index = i; - } - } - - //if it is not in the array, return - if (found_molecule == false) { - return; - } - - //Otherwise, shift the molecules while removing the specified molecule - for (int j = molecule_index; j < cluster_gain_stats.num_feasible_blocks - 1; j++) { - cluster_gain_stats.feasible_blocks[j] = cluster_gain_stats.feasible_blocks[j + 1]; - } - cluster_gain_stats.num_feasible_blocks--; + cluster_gain_stats.feasible_blocks.remove_at_pop_time(molecule_id); } /* diff --git a/vpr/src/pack/greedy_candidate_selector.h b/vpr/src/pack/greedy_candidate_selector.h index a7af8d448b..b39ad469b4 100644 --- a/vpr/src/pack/greedy_candidate_selector.h +++ b/vpr/src/pack/greedy_candidate_selector.h @@ -23,6 +23,7 @@ #include "vtr_vector.h" #include "vtr_random.h" #include "vtr_vector_map.h" +#include "lazy_pop_unique_priority_queue.h" // Forward declarations class AtomNetlist; @@ -97,13 +98,6 @@ struct ClusterGainStats { /// with the cluster. AttractGroupId attraction_grp_id; - /// @brief Array of feasible blocks to select from [0..max_array_size-1] - /// - /// Sorted in ascending gain order so that the last cluster_ctx.blocks is - /// the most desirable (this makes it easy to pop blocks off the list. - std::vector feasible_blocks; - int num_feasible_blocks; - /// @brief The flat placement location of this cluster. /// /// This is some function of the positions of the molecules which have been @@ -126,6 +120,25 @@ struct ClusterGainStats { /// set when the stats are created based on the primitive pb type /// of the seed. bool is_memory = false; + + /// @brief List of feasible block and its gain pairs. + /// The list is maintained in heap structure with the highest gain block + /// at the front. + LazyPopUniquePriorityQueue feasible_blocks; + + /// @brief Indicator for the initial search for feasible blocks. + bool initial_search_for_feasible_blocks; + + /// @brief Limit for the number of candiate proposed at each stage. + unsigned candidates_propose_limit; + + /// @brief Counter for the number of candiate proposed at each stage. + unsigned num_candidates_proposed; + + /// @brief Check if the current stage candidates proposed limit is reached. + bool current_stage_candidates_proposed_limit_reached() { + return num_candidates_proposed >= candidates_propose_limit; + } }; /** @@ -444,7 +457,7 @@ class GreedyCandidateSelector { // Cluster Candidate Selection // ===================================================================== // - /* + /** * @brief Add molecules with strong connectedness to the current cluster to * the list of feasible blocks. */ @@ -471,7 +484,7 @@ class GreedyCandidateSelector { LegalizationClusterId legalization_cluster_id, const ClusterLegalizer& cluster_legalizer); - /* + /** * @brief Add molecules based on transitive connections (eg. 2 hops away) * with current cluster. */ @@ -481,7 +494,7 @@ class GreedyCandidateSelector { const ClusterLegalizer& cluster_legalizer, AttractionInfo& attraction_groups); - /* + /** * @brief Add molecules based on weak connectedness (connected by high * fanout nets) with current cluster. */ @@ -491,7 +504,7 @@ class GreedyCandidateSelector { const ClusterLegalizer& cluster_legalizer, AttractionInfo& attraction_groups); - /* + /** * @brief If the current cluster being packed has an attraction group * associated with it (i.e. there are atoms in it that belong to an * attraction group), this routine adds molecules from the associated diff --git a/vpr/src/util/lazy_pop_unique_priority_queue.h b/vpr/src/util/lazy_pop_unique_priority_queue.h new file mode 100644 index 0000000000..d375daf19c --- /dev/null +++ b/vpr/src/util/lazy_pop_unique_priority_queue.h @@ -0,0 +1,216 @@ +/** + * @file + * @author Rongbo Zhang + * @date 2025-04-23 + * @brief This file contains the definition of the LazyPopUniquePriorityQueue class. + * + * The class LazyPopUniquePriorityQueue is a priority queue that allows for lazy deletion of elements. + * The elements are pair of key and sort-value. The key is a unique value to identify the item, and the sort-value is used to sort the item. + * It is implemented using a vector and 2 sets, one set keeps track of the elements in the queue, and the other set keeps track of the elements that are pending deletion, + * so that they can be removed from the queue when they are popped. + * + * Currently, the class supports the following functions: + * LazyPopUniquePriorityQueue::push(): Pushes a key-sort-value (K-SV) pair into the priority queue and adds the key to the tracking set. + * LazyPopUniquePriorityQueue::pop(): Returns the K-SV pair with the highest SV whose key is not pending deletion. + * LazyPopUniquePriorityQueue::remove(): Removes an element from the priority queue immediately. + * LazyPopUniquePriorityQueue::remove_at_pop_time(): Removes an element from the priority queue when it is popped. + * LazyPopUniquePriorityQueue::empty(): Returns whether the queue is empty. + * LazyPopUniquePriorityQueue::clear(): Clears the priority queue vector and the tracking sets. + * LazyPopUniquePriorityQueue::size(): Returns the number of elements in the queue. + * LazyPopUniquePriorityQueue::contains(): Returns true if the key is in the queue, false otherwise. + */ + +#pragma once + +#include +#include +#include + +/** + * @brief Lazy Pop Unique Priority Queue + * + * This is a priority queue that is used to sort items which are identified by the key + * and sorted by the sort value. + * + * It uses a vector to store the key and sort value pair. + * It uses a set to store the keys that are in the vector for uniqueness checking + * and a set to store the delete pending keys which will be removed at pop time. + */ + +template +class LazyPopUniquePriorityQueue { + public: + /** @brief The custom comparsion struct for sorting the items in the priority queue. + * A less than comparison will put the item with the highest sort value to the front of the queue. + * A greater than comparison will put the item with the lowest sort value to the front of the queue. + */ + struct LazyPopUniquePriorityQueueCompare { + bool operator()(const std::pair& a, + const std::pair& b) const { + return a.second < b.second; + } + }; + + /// @brief The vector maintained as heap to store the key and sort value pair. + std::vector> heap; + + /// @brief The set to store the keys that are in the queue. This is used to ensure uniqueness + std::unordered_set content_set; + + /// @brief The set to store the delete pending item from the queue refered by the key. + std::unordered_set delete_pending_set; + + /** + * @brief Push the key and the sort value as a pair into the priority queue. + * + * @param key + * The unique key for the item that will be pushed onto the queue. + * @param value + * The sort value used for sorting the item. + */ + void push(T_key key, T_sort value) { + // Insert the key and sort value pair into the queue if it is not already present + if (content_set.find(key) != content_set.end()) { + // If the key is already in the queue, do nothing + return; + } + // Insert the key and sort value pair into the heap and track the key + // The new item is added to the end of the vector and then the push_heap function is call + // to push the item to the correct position in the heap structure. + heap.emplace_back(key, value); + std::push_heap(heap.begin(), heap.end(), LazyPopUniquePriorityQueueCompare()); + content_set.insert(key); + } + + /** + * @brief Pop the top item from the priority queue. + * + * @return The key and sort value pair. + */ + std::pair pop() { + std::pair top_pair; + while (heap.size() > 0) { + top_pair = heap.front(); + // Remove the key from the heap and the tracking set. + // The pop_heap function will move the top item in the heap structure to the end of the vector container. + // Then the pop_back function will remove the last item. + std::pop_heap(heap.begin(), heap.end(), LazyPopUniquePriorityQueueCompare()); + heap.pop_back(); + content_set.erase(top_pair.first); + + // Checking if the key with the highest sort value is in the delete pending set. + // If it is, ignore the current top item and remove the key from the delete pending set. Then get the next top item. + // Otherwise, the top item found, break the loop. + if (delete_pending_set.find(top_pair.first) != delete_pending_set.end()) { + delete_pending_set.erase(top_pair.first); + top_pair = std::pair(); + } else { + break; + } + } + + // If there is zero non-pending-delete item, clear the queue. + if (empty()) { + clear(); + } + + return top_pair; + } + + /** + * @brief Remove the item with matching key value from the priority queue + * This will immediately remove the item and re-heapify the queue. + * + * This function is expensive, as it requires a full re-heapify of the queue. + * The time complexity is O(n log n) for the re-heapify, where n is the size of the queue. + * It is recommended to use remove_at_pop_time() instead. + * @param key + * The key of the item to be delected from the queue. + */ + void remove(T_key key) { + // If the key is in the priority queue, remove it from the heap and reheapify. + // Otherwise, do nothing. + if (content_set.find(key) != content_set.end()) { + content_set.erase(key); + delete_pending_set.erase(key); + for (int i = 0; i < heap.size(); i++) { + if (heap[i].first == key) { + heap.erase(heap.begin() + i); + break; + } + } + + // If this delete caused the queue to have zero non-pending-delete item, clear the queue. + if (empty()) { + clear(); + // Otherwise re-heapify the queue + } else { + std::make_heap(heap.begin(), heap.end(), LazyPopUniquePriorityQueueCompare()); + } + } + } + + /** + * @brief Remove the item with matching key value from the priority queue at pop time. + * Add the key to the delete pending set for tracking, + * and it will be deleted when it is popped. + * + * This function will not immediately delete the key from the + * priority queue. It will be deleted when it is popped. Thus do not + * expect a size reduction in the priority queue immediately. + * @param key + * The key of the item to be delected from the queue at pop time. + */ + void remove_at_pop_time(T_key key) { + // If the key is in the list, start tracking it in the delete pending list. + // Otherwise, do nothing. + if (content_set.find(key) != content_set.end()) { + delete_pending_set.insert(key); + + // If this marks the last non-pending-delete item as to-be-deleted, clear the queue + if (empty()) { + clear(); + } + } + } + + /** + * @brief Check if the priority queue is empty, i.e. there is zero non-pending-delete item. + * + * @return True if the priority queue is empty, false otherwise. + */ + bool empty() { + return size() == 0; + } + + /** + * @brief Clears the priority queue and the tracking sets. + * + * @return None + */ + void clear() { + heap.clear(); + content_set.clear(); + delete_pending_set.clear(); + } + + /** + * @brief Get the number of non-pending-delete items in the priority queue. + * + * @return The number of non-pending-delete items in the priority queue. + */ + size_t size() { + return heap.size() - delete_pending_set.size(); + } + + /** + * @brief Check if the item referred to the key is in the priority queue. + * + * @param key + * The key of the item. + * @return True if the key is in the priority queue, false otherwise. + */ + bool contains(T_key key) { + return content_set.find(key) != content_set.end(); + } +}; From 8de3926ce76530441814b1b514287003de87ee00 Mon Sep 17 00:00:00 2001 From: Rongbo Zhang Date: Thu, 1 May 2025 22:07:16 -0400 Subject: [PATCH 2/2] [packer] recollected golden results for regression basic, basic_odin, strong, strong_odin --- .../basic_no_timing/config/golden_results.txt | 10 +- .../basic_timing/config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../basic_no_timing/config/golden_results.txt | 10 +- .../basic_timing/config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../basic_ap/config/golden_results.txt | 10 +- .../koios_test/config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../strong_3d/3d_cb/config/golden_results.txt | 2 +- .../strong_3d/3d_sb/config/golden_results.txt | 2 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../strong_ap/mcnc/config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../no_fixed_blocks/config/golden_results.txt | 12 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 10 +- .../vtr_chain/config/golden_results.txt | 10 +- .../strong_bidir/config/golden_results.txt | 10 +- .../strong_binary/config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../strong_depop/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_fc_abs/config/golden_results.txt | 4 +- .../apex2_block_locations.place | 352 +++++++++--------- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../read_write/config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +-- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_mcnc/config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../strong_noc/config/golden_results.txt | 4 +- .../strong_pack/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../strong_place/config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +-- .../strong_power/config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_sdc/config/golden_results.txt | 14 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 28 +- .../config/golden_results.txt | 4 +- .../strong_timing/config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 14 +- .../strong_titan/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../koios_test/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../strong_bidir/config/golden_results.txt | 10 +- .../strong_binary/config/golden_results.txt | 6 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../strong_depop/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_fc_abs/config/golden_results.txt | 4 +- .../apex2_block_locations.place | 352 +++++++++--------- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +-- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_mcnc/config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_pack/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../strong_place/config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 42 +-- .../strong_power/config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_sdc/config/golden_results.txt | 14 +- .../config/golden_results.txt | 14 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 28 +- .../config/golden_results.txt | 4 +- .../strong_timing/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../strong_titan/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 10 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 4 +- 199 files changed, 1094 insertions(+), 1082 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt index a19aa57c93..b47d76ffed 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.71 vpr 62.29 MiB -1 -1 0.45 18372 3 0.09 -1 -1 33140 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63780 99 130 353 483 1 222 301 13 13 169 clb auto 22.7 MiB 0.06 730 30541 5185 13290 12066 62.3 MiB 0.05 0.00 28 1583 11 3.33e+06 2.25e+06 384474. 2275.00 0.18 - k4_N10_memSize16384_memData64.xml diffeq1.v common 3.90 vpr 66.30 MiB -1 -1 0.72 23492 23 0.30 -1 -1 34028 -1 -1 77 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 67888 162 96 1200 1141 1 675 340 13 13 169 clb auto 25.9 MiB 0.18 5120 92848 24971 61178 6699 66.3 MiB 0.19 0.00 52 9637 13 3.33e+06 2.76e+06 671819. 3975.26 1.14 - k4_N10_memSize16384_memData64.xml single_wire.v common 2.10 vpr 59.81 MiB -1 -1 0.16 16372 1 0.17 -1 -1 29680 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 61244 1 1 1 2 0 1 2 3 3 9 -1 auto 21.3 MiB 0.00 2 3 0 3 0 59.8 MiB 0.01 0.00 2 1 1 30000 0 1489.46 165.495 0.01 - k4_N10_memSize16384_memData64.xml single_ff.v common 2.13 vpr 59.62 MiB -1 -1 0.15 16244 1 0.17 -1 -1 29552 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 61048 2 1 3 4 1 3 4 3 3 9 -1 auto 21.2 MiB 0.00 6 9 6 0 3 59.6 MiB 0.01 0.00 16 5 1 30000 30000 2550.78 283.420 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.17 vpr 63.18 MiB -1 -1 0.21 18728 3 0.06 -1 -1 32704 -1 -1 72 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64692 99 130 353 483 1 220 302 13 13 169 clb auto 23.4 MiB 0.03 1748 641 31674 5814 13912 11948 63.2 MiB 0.03 0.00 36 1209 9 3.33e+06 2.28e+06 481319. 2848.04 0.18 +k4_N10_memSize16384_memData64.xml diffeq1.v common 2.84 vpr 66.43 MiB -1 -1 0.32 23332 23 0.28 -1 -1 33440 -1 -1 78 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68020 162 96 1200 1141 1 690 341 14 14 196 clb auto 26.8 MiB 0.11 8696 5304 81261 22686 53433 5142 66.4 MiB 0.09 0.00 46 10726 18 4.32e+06 2.79e+06 735717. 3753.66 1.10 +k4_N10_memSize16384_memData64.xml single_wire.v common 0.50 vpr 61.17 MiB -1 -1 0.06 17192 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62636 1 1 1 2 0 1 2 3 3 9 -1 auto 22.6 MiB 0.00 2 2 3 0 3 0 61.2 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 +k4_N10_memSize16384_memData64.xml single_ff.v common 0.51 vpr 61.02 MiB -1 -1 0.05 17192 1 0.02 -1 -1 29212 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62484 2 1 3 4 1 3 4 3 3 9 -1 auto 22.4 MiB 0.00 6 6 9 6 0 3 61.0 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt index 751bc75b90..e2311faa13 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.47 vpr 63.16 MiB -1 -1 0.44 18236 3 0.17 -1 -1 33188 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64672 99 130 344 474 1 225 301 13 13 169 clb auto 23.3 MiB 0.09 736 75901 22924 36629 16348 63.2 MiB 0.26 0.00 2.16096 -125.507 -2.16096 2.16096 0.16 0.00128139 0.00121469 0.100824 0.095478 -1 -1 -1 -1 32 1361 16 6.63067e+06 4.37447e+06 323148. 1912.12 0.39 0.254103 0.235005 11612 59521 -1 1272 10 497 712 34049 10041 1.99692 1.99692 -142.118 -1.99692 -0.13959 -0.0561481 396943. 2348.77 0.01 0.05 0.06 -1 -1 0.01 0.0312641 0.0288189 - k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.44 vpr 63.16 MiB -1 -1 0.50 18152 3 0.14 -1 -1 33088 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 64676 99 130 344 474 1 225 301 13 13 169 clb auto 23.2 MiB 0.11 736 75901 22924 36629 16348 63.2 MiB 0.26 0.00 2.16096 -125.507 -2.16096 2.16096 0.16 0.00128481 0.00121739 0.100806 0.0954483 -1 -1 -1 -1 32 1361 16 6.63067e+06 4.37447e+06 323148. 1912.12 0.39 0.254201 0.235091 11612 59521 -1 1272 10 497 712 34049 10041 1.99692 1.99692 -142.118 -1.99692 -0.13959 -0.0561481 396943. 2348.77 0.01 0.05 0.06 -1 -1 0.01 0.0311227 0.0286984 - k6_N10_mem32K_40nm.xml diffeq1.v common 9.49 vpr 67.11 MiB -1 -1 0.77 23280 15 0.36 -1 -1 34140 -1 -1 61 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 68724 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.7 MiB 0.29 5596 100404 30167 62963 7274 67.1 MiB 0.72 0.01 21.2727 -1572.97 -21.2727 21.2727 0.25 0.00332766 0.00312916 0.315543 0.296132 -1 -1 -1 -1 40 11119 33 1.21132e+07 5.26753e+06 612675. 2393.26 4.42 1.40293 1.28823 19892 118481 -1 8936 23 3487 7703 996102 285541 21.8294 21.8294 -1657.3 -21.8294 0 0 771607. 3014.09 0.03 0.36 0.10 -1 -1 0.03 0.165646 0.152968 - k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 9.36 vpr 66.73 MiB -1 -1 0.76 23068 15 0.37 -1 -1 34060 -1 -1 61 162 0 5 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 68332 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 27.4 MiB 0.27 5596 100404 30167 62963 7274 66.7 MiB 0.73 0.01 21.2727 -1572.97 -21.2727 21.2727 0.25 0.00332438 0.00312633 0.31865 0.29876 -1 -1 -1 -1 40 11119 33 1.21132e+07 5.26753e+06 612675. 2393.26 4.32 1.38842 1.27429 19892 118481 -1 8936 23 3487 7703 996102 285541 21.8294 21.8294 -1657.3 -21.8294 0 0 771607. 3014.09 0.03 0.36 0.10 -1 -1 0.03 0.165924 0.153299 - k6_N10_mem32K_40nm.xml single_wire.v common 2.19 vpr 61.04 MiB -1 -1 0.10 16040 1 0.17 -1 -1 29628 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62508 1 1 1 2 0 1 2 3 3 9 -1 auto 22.4 MiB 0.03 2 3 0 3 0 61.0 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0106e-05 6.693e-06 6.7577e-05 4.7955e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00184576 0.00171316 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00130358 0.00127692 - k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.14 vpr 61.03 MiB -1 -1 0.18 16180 1 0.17 -1 -1 29612 -1 -1 0 1 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62496 1 1 1 2 0 1 2 3 3 9 -1 auto 22.5 MiB 0.01 2 3 0 3 0 61.0 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 3.4991e-05 2.3839e-05 0.000154694 0.000110075 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.01 0.00205152 0.00184775 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00106138 0.00103434 - k6_N10_mem32K_40nm.xml single_ff.v common 2.12 vpr 60.94 MiB -1 -1 0.17 16352 1 0.17 -1 -1 29692 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62400 2 1 3 4 1 3 4 3 3 9 -1 auto 22.4 MiB 0.01 6 9 3 5 1 60.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5239e-05 1.148e-05 9.224e-05 7.1486e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00131631 0.00123081 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.0011347 0.00109647 - k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.11 vpr 61.02 MiB -1 -1 0.17 16384 1 0.17 -1 -1 29576 -1 -1 1 2 0 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 62488 2 1 3 4 1 3 4 3 3 9 -1 auto 22.5 MiB 0.00 6 9 3 5 1 61.0 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.54e-05 1.1599e-05 9.8314e-05 7.6493e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.001247 0.00116724 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00104656 0.00101086 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.52 vpr 65.36 MiB -1 -1 0.22 18440 3 0.07 -1 -1 32724 -1 -1 72 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66924 99 130 344 474 1 224 302 13 13 169 clb auto 25.4 MiB 0.04 1746 762 68106 19514 34631 13961 65.4 MiB 0.11 0.00 2.21168 1.87164 -122.901 -1.87164 1.87164 0.11 0.000580681 0.000545769 0.0407202 0.038189 -1 -1 -1 -1 32 1396 14 6.63067e+06 4.42837e+06 323148. 1912.12 0.21 0.109197 0.100619 11612 59521 -1 1378 10 517 775 49020 15288 2.04417 2.04417 -145.25 -2.04417 -0.103145 -0.0426347 396943. 2348.77 0.01 0.03 0.04 -1 -1 0.01 0.0163045 0.0151785 +k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.50 vpr 65.35 MiB -1 -1 0.22 18440 3 0.06 -1 -1 32992 -1 -1 72 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66920 99 130 344 474 1 224 302 13 13 169 clb auto 25.6 MiB 0.04 1746 762 68106 19514 34631 13961 65.4 MiB 0.11 0.00 2.21168 1.87164 -122.901 -1.87164 1.87164 0.11 0.000562052 0.000527144 0.0404975 0.0379682 -1 -1 -1 -1 32 1396 14 6.63067e+06 4.42837e+06 323148. 1912.12 0.21 0.108919 0.100249 11612 59521 -1 1378 10 517 775 49020 15288 2.04417 2.04417 -145.25 -2.04417 -0.103145 -0.0426347 396943. 2348.77 0.01 0.03 0.03 -1 -1 0.01 0.0159129 0.0148233 +k6_N10_mem32K_40nm.xml diffeq1.v common 4.82 vpr 68.54 MiB -1 -1 0.32 23428 15 0.29 -1 -1 33480 -1 -1 61 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70188 162 96 1009 950 1 667 324 16 16 256 mult_36 auto 29.2 MiB 0.15 9690 5422 80388 23076 51132 6180 68.5 MiB 0.32 0.01 24.8942 21.9154 -1692.2 -21.9154 21.9154 0.17 0.00158522 0.00147129 0.125116 0.116593 -1 -1 -1 -1 40 11149 48 1.21132e+07 5.26753e+06 612675. 2393.26 2.20 0.557099 0.514381 19892 118481 -1 8842 23 4046 9257 1093658 327616 22.4259 22.4259 -1741.35 -22.4259 0 0 771607. 3014.09 0.02 0.25 0.09 -1 -1 0.02 0.0937785 0.087944 +k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 4.76 vpr 68.70 MiB -1 -1 0.31 23432 15 0.29 -1 -1 33444 -1 -1 61 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70352 162 96 1009 950 1 667 324 16 16 256 mult_36 auto 29.4 MiB 0.16 9690 5422 80388 23076 51132 6180 68.7 MiB 0.33 0.01 24.8942 21.9154 -1692.2 -21.9154 21.9154 0.17 0.0015726 0.00146312 0.125878 0.117421 -1 -1 -1 -1 40 11149 48 1.21132e+07 5.26753e+06 612675. 2393.26 2.22 0.562575 0.519888 19892 118481 -1 8842 23 4046 9257 1093658 327616 22.4259 22.4259 -1741.35 -22.4259 0 0 771607. 3014.09 0.02 0.23 0.07 -1 -1 0.02 0.0896627 0.0838558 +k6_N10_mem32K_40nm.xml single_wire.v common 0.51 vpr 62.66 MiB -1 -1 0.07 16756 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64164 1 1 1 2 0 1 2 3 3 9 -1 auto 24.4 MiB 0.00 2 2 3 0 3 0 62.7 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.113e-06 3.2e-06 4.8224e-05 3.163e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.0008492 0.000799197 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000892211 0.000861501 +k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.50 vpr 63.12 MiB -1 -1 0.07 16904 1 0.02 -1 -1 29568 -1 -1 0 1 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64632 1 1 1 2 0 1 2 3 3 9 -1 auto 24.6 MiB 0.00 2 2 3 0 3 0 63.1 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 7.032e-06 3.894e-06 5.3602e-05 3.622e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.000856098 0.000806022 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000930211 0.000900687 +k6_N10_mem32K_40nm.xml single_ff.v common 0.53 vpr 62.12 MiB -1 -1 0.07 17284 1 0.02 -1 -1 29524 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 63612 2 1 3 4 1 3 4 3 3 9 -1 auto 23.9 MiB 0.00 6 6 9 3 5 1 62.1 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.614e-06 6.244e-06 7.396e-05 5.4469e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000951614 0.000891258 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000916914 0.000879236 +k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.53 vpr 62.47 MiB -1 -1 0.06 17284 1 0.02 -1 -1 29432 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 63972 2 1 3 4 1 3 4 3 3 9 -1 auto 24.3 MiB 0.00 6 6 9 3 5 1 62.5 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.432e-06 6.157e-06 7.2561e-05 5.4179e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000945489 0.000885341 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000919599 0.000881694 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt index e5e577a6aa..bbcf931477 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml mkPktMerge.v common 14.27 vpr 75.54 MiB -1 -1 1.67 25360 2 0.13 -1 -1 33796 -1 -1 43 311 15 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 77356 311 156 972 1128 1 953 525 28 28 784 memory auto 28.9 MiB 0.44 8505 220693 82593 126911 11189 69.5 MiB 1.24 0.02 3.82651 -4329.36 -3.82651 3.82651 0.84 0.00554225 0.00490893 0.598549 0.528234 -1 -1 -1 -1 40 13414 12 4.25198e+07 1.05374e+07 2.03169e+06 2591.44 6.02 1.94301 1.71815 62360 400487 -1 12485 12 2406 2992 760238 228941 4.26893 4.26893 -4812.21 -4.26893 -13.8425 -0.321515 2.55406e+06 3257.73 0.09 0.29 0.34 -1 -1 0.09 0.16964 0.153486 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml mkPktMerge.v common 6.26 vpr 70.44 MiB -1 -1 0.74 25976 2 0.09 -1 -1 33188 -1 -1 43 311 15 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72132 311 156 972 1128 1 953 525 28 28 784 memory auto 31.2 MiB 0.27 18876 8716 214342 80322 124048 9972 70.4 MiB 0.60 0.01 4.91229 4.39077 -4239.94 -4.39077 4.39077 0.60 0.00247588 0.00219652 0.268277 0.237182 -1 -1 -1 -1 40 13591 16 4.25198e+07 1.05374e+07 2.03169e+06 2591.44 1.92 0.83907 0.751065 62360 400487 -1 12638 13 2518 2949 727753 230227 4.48005 4.48005 -4599.19 -4.48005 -24.1998 -0.322548 2.55406e+06 3257.73 0.08 0.18 0.22 -1 -1 0.08 0.0972832 0.0901219 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt index cbe871a6d7..dfa68da0cc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 2.71 vpr 61.64 MiB -1 -1 0.45 18444 3 0.09 -1 -1 32856 -1 -1 71 99 1 0 success v8.0.0-11920-g63becbef4-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-12-04T15:29:41 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63120 99 130 353 483 1 222 301 13 13 169 clb auto 21.8 MiB 0.06 723 26509 3069 10019 13421 61.6 MiB 0.04 0.00 28 1598 8 3.33e+06 2.25e+06 384474. 2275.00 0.18 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 1.13 vpr 62.02 MiB -1 -1 0.20 18340 3 0.07 -1 -1 32320 -1 -1 72 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 63508 99 130 353 483 1 221 302 13 13 169 clb auto 22.2 MiB 0.03 1823 708 26614 3324 9855 13435 62.0 MiB 0.02 0.00 28 1654 13 3.33e+06 2.28e+06 384474. 2275.00 0.12 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt index 68c5f54f78..38b4f273c2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 3.06 vpr 62.63 MiB 0.05 9228 -1 -1 4 0.26 -1 -1 34628 -1 -1 78 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 64132 99 130 378 508 1 260 308 14 14 196 clb auto 23.1 MiB 0.07 836 35634 7872 13338 14424 62.6 MiB 0.06 0.00 30 1863 18 4.32e+06 2.46e+06 504535. 2574.16 1.49 - k4_N10_memSize16384_memData64.xml diffeq1.v common 3.71 vpr 66.76 MiB 0.03 9312 -1 -1 23 0.28 -1 -1 34812 -1 -1 78 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 68360 162 96 1214 1147 1 691 341 14 14 196 clb auto 26.3 MiB 0.20 5391 114581 32074 75067 7440 66.8 MiB 0.23 0.00 50 10696 14 4.32e+06 2.79e+06 792225. 4041.96 1.36 - k4_N10_memSize16384_memData64.xml single_wire.v common 0.50 vpr 60.26 MiB 0.03 6196 -1 -1 1 0.02 -1 -1 29884 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61708 1 1 1 2 0 1 2 3 3 9 -1 auto 21.5 MiB 0.00 2 3 0 3 0 60.3 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 - k4_N10_memSize16384_memData64.xml single_ff.v common 0.50 vpr 60.32 MiB 0.01 6248 -1 -1 1 0.02 -1 -1 29888 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 61772 2 1 3 4 1 3 4 3 3 9 -1 auto 21.6 MiB 0.00 6 9 6 0 3 60.3 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 3.75 odin 99.00 MiB 2.46 101376 -1 -1 4 0.20 -1 -1 33808 -1 -1 77 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65132 99 130 378 508 1 264 307 13 13 169 clb auto 23.6 MiB 0.03 2217 834 80002 17611 37329 25062 63.6 MiB 0.06 0.00 38 1591 8 3.33e+06 2.43e+06 504671. 2986.22 0.19 +k4_N10_memSize16384_memData64.xml diffeq1.v common 4.49 odin 85.88 MiB 1.86 87936 -1 -1 23 0.22 -1 -1 34268 -1 -1 78 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68156 162 96 1214 1147 1 683 341 14 14 196 clb auto 26.9 MiB 0.11 8470 5094 83641 22304 55208 6129 66.6 MiB 0.09 0.00 46 10813 38 4.32e+06 2.79e+06 735717. 3753.66 1.12 +k4_N10_memSize16384_memData64.xml single_wire.v common 1.85 vpr 61.12 MiB 1.34 61056 -1 -1 1 0.02 -1 -1 29292 -1 -1 0 1 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62584 1 1 1 2 0 1 2 3 3 9 -1 auto 22.9 MiB 0.00 2 2 3 0 3 0 61.1 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 +k4_N10_memSize16384_memData64.xml single_ff.v common 1.63 vpr 61.14 MiB 1.13 61440 -1 -1 1 0.02 -1 -1 29316 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62612 2 1 3 4 1 3 4 3 3 9 -1 auto 22.9 MiB 0.00 6 6 9 6 0 3 61.1 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt index ef84b66a48..e0593782ad 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 4.50 vpr 64.15 MiB 0.07 9400 -1 -1 3 0.27 -1 -1 34560 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65688 99 130 363 493 1 255 305 13 13 169 clb auto 24.4 MiB 0.09 908 74177 24418 37403 12356 64.1 MiB 0.26 0.00 2.24932 -227.778 -2.24932 2.24932 0.32 0.00128796 0.00121332 0.096703 0.0915143 -1 -1 -1 -1 32 1516 16 6.63067e+06 4.59005e+06 323148. 1912.12 2.05 0.536952 0.490784 11612 59521 -1 1275 27 730 1142 95340 32482 2.40779 2.40779 -232.565 -2.40779 0 0 396943. 2348.77 0.11 0.11 0.05 -1 -1 0.11 0.067572 0.0617159 - k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 4.47 vpr 64.18 MiB 0.07 9504 -1 -1 3 0.27 -1 -1 34508 -1 -1 75 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 65716 99 130 363 493 1 255 305 13 13 169 clb auto 24.4 MiB 0.09 908 74177 24418 37403 12356 64.2 MiB 0.25 0.00 2.24932 -227.778 -2.24932 2.24932 0.33 0.00129519 0.00122409 0.0975081 0.0921414 -1 -1 -1 -1 32 1516 16 6.63067e+06 4.59005e+06 323148. 1912.12 2.05 0.537515 0.491308 11612 59521 -1 1275 27 730 1142 95340 32482 2.40779 2.40779 -232.565 -2.40779 0 0 396943. 2348.77 0.10 0.10 0.06 -1 -1 0.10 0.0672906 0.0614343 - k6_N10_mem32K_40nm.xml diffeq1.v common 7.21 vpr 67.98 MiB 0.05 9412 -1 -1 15 0.36 -1 -1 34576 -1 -1 60 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69616 162 96 999 932 1 661 323 16 16 256 mult_36 auto 27.8 MiB 0.27 5495 75599 21207 48608 5784 68.0 MiB 0.58 0.01 21.6615 -1879.46 -21.6615 21.6615 0.51 0.00360796 0.00340202 0.25554 0.240594 -1 -1 -1 -1 44 10097 29 1.21132e+07 5.21364e+06 665287. 2598.78 3.00 1.1065 1.02126 20656 131250 -1 8720 22 3466 7443 973330 268208 22.2123 22.2123 -1936.09 -22.2123 0 0 864808. 3378.16 0.21 0.36 0.12 -1 -1 0.21 0.171024 0.158501 - k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 7.19 vpr 68.00 MiB 0.05 9256 -1 -1 15 0.38 -1 -1 34544 -1 -1 60 162 0 5 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 69628 162 96 999 932 1 661 323 16 16 256 mult_36 auto 27.8 MiB 0.27 5495 75599 21207 48608 5784 68.0 MiB 0.58 0.01 21.6615 -1879.46 -21.6615 21.6615 0.51 0.00357179 0.00336822 0.255146 0.240275 -1 -1 -1 -1 44 10097 29 1.21132e+07 5.21364e+06 665287. 2598.78 3.02 1.11639 1.03133 20656 131250 -1 8720 22 3466 7443 973330 268208 22.2123 22.2123 -1936.09 -22.2123 0 0 864808. 3378.16 0.21 0.36 0.12 -1 -1 0.21 0.171551 0.159214 - k6_N10_mem32K_40nm.xml single_wire.v common 0.52 vpr 61.57 MiB 0.02 6336 -1 -1 1 0.02 -1 -1 29916 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63052 1 1 1 2 0 1 2 3 3 9 -1 auto 23.1 MiB 0.00 2 3 0 3 0 61.6 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0413e-05 6.444e-06 6.9938e-05 4.9915e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00113499 0.00107062 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00114956 0.00110637 - k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.50 vpr 61.70 MiB 0.01 6288 -1 -1 1 0.02 -1 -1 29852 -1 -1 0 1 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63176 1 1 1 2 0 1 2 3 3 9 -1 auto 23.1 MiB 0.00 2 3 0 3 0 61.7 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0828e-05 6.306e-06 8.6241e-05 6.4409e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00147956 0.00135131 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00110491 0.00107479 - k6_N10_mem32K_40nm.xml single_ff.v common 0.51 vpr 61.60 MiB 0.01 6340 -1 -1 1 0.02 -1 -1 29792 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63080 2 1 3 4 1 3 4 3 3 9 -1 auto 23.2 MiB 0.00 6 9 5 1 3 61.6 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5674e-05 1.1879e-05 0.000102525 7.8057e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.0012801 0.00119733 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00109578 0.00105577 - k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.52 vpr 61.85 MiB 0.01 6336 -1 -1 1 0.02 -1 -1 29872 -1 -1 1 2 0 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63336 2 1 3 4 1 3 4 3 3 9 -1 auto 23.4 MiB 0.00 6 9 5 1 3 61.9 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5402e-05 1.1583e-05 0.00010302 8.1368e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00128286 0.00120047 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.0011085 0.00106995 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.98 odin 99.75 MiB 2.35 102144 -1 -1 3 0.20 -1 -1 33952 -1 -1 75 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66300 99 130 363 493 1 253 305 13 13 169 clb auto 24.9 MiB 0.04 2273 844 74177 21541 39695 12941 64.7 MiB 0.12 0.00 2.6333 2.22949 -229.909 -2.22949 2.22949 0.11 0.000550698 0.000515854 0.0427175 0.0400049 -1 -1 -1 -1 32 1393 19 6.63067e+06 4.59005e+06 323148. 1912.12 0.23 0.113233 0.104064 11612 59521 -1 1193 22 721 1096 62496 20405 2.52707 2.52707 -230.152 -2.52707 0 0 396943. 2348.77 0.01 0.04 0.03 -1 -1 0.01 0.0262396 0.0241574 +k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 4.05 odin 99.75 MiB 2.44 102144 -1 -1 3 0.20 -1 -1 33708 -1 -1 75 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66476 99 130 363 493 1 253 305 13 13 169 clb auto 25.4 MiB 0.04 2273 844 74177 21541 39695 12941 64.9 MiB 0.12 0.00 2.6333 2.22949 -229.909 -2.22949 2.22949 0.11 0.000538977 0.000504453 0.0432327 0.0405059 -1 -1 -1 -1 32 1393 19 6.63067e+06 4.59005e+06 323148. 1912.12 0.23 0.114698 0.105593 11612 59521 -1 1193 22 721 1096 62496 20405 2.52707 2.52707 -230.152 -2.52707 0 0 396943. 2348.77 0.01 0.04 0.03 -1 -1 0.01 0.0261132 0.0240314 +k6_N10_mem32K_40nm.xml diffeq1.v common 6.22 odin 86.62 MiB 1.92 88704 -1 -1 15 0.29 -1 -1 34324 -1 -1 62 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71032 162 96 999 932 1 663 325 16 16 256 mult_36 auto 29.4 MiB 0.15 9594 5574 90802 23938 58756 8108 69.4 MiB 0.36 0.01 24.8422 21.1611 -1910.27 -21.1611 21.1611 0.18 0.00171466 0.00161022 0.150493 0.141039 -1 -1 -1 -1 40 11068 31 1.21132e+07 5.32143e+06 612675. 2393.26 1.89 0.572902 0.53303 19892 118481 -1 8993 24 3753 8101 1142271 339586 22.091 22.091 -1952.75 -22.091 0 0 771607. 3014.09 0.02 0.25 0.07 -1 -1 0.02 0.0980349 0.092212 +k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 6.28 odin 86.62 MiB 2.02 88704 -1 -1 15 0.29 -1 -1 34276 -1 -1 62 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70652 162 96 999 932 1 663 325 16 16 256 mult_36 auto 29.4 MiB 0.15 9594 5574 90802 23938 58756 8108 69.0 MiB 0.35 0.01 24.8422 21.1611 -1910.27 -21.1611 21.1611 0.18 0.00168171 0.00157982 0.147926 0.138611 -1 -1 -1 -1 40 11068 31 1.21132e+07 5.32143e+06 612675. 2393.26 1.87 0.568077 0.527939 19892 118481 -1 8993 24 3753 8101 1142271 339586 22.091 22.091 -1952.75 -22.091 0 0 771607. 3014.09 0.02 0.25 0.07 -1 -1 0.02 0.0976556 0.0918962 +k6_N10_mem32K_40nm.xml single_wire.v common 1.91 vpr 62.42 MiB 1.40 62208 -1 -1 1 0.02 -1 -1 29296 -1 -1 0 1 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 63916 1 1 1 2 0 1 2 3 3 9 -1 auto 24.2 MiB 0.00 2 2 3 0 3 0 62.4 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.972e-06 3.868e-06 5.6338e-05 3.8595e-05 -1 -1 -1 -1 14 13 1 53894 0 3251.56 361.284 0.00 0.000911702 0.000853003 318 537 -1 13 1 1 1 42 40 1.13321 nan -1.13321 -1.13321 0 0 4350.07 483.341 0.00 0.00 0.00 -1 -1 0.00 0.000910373 0.000880126 +k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.72 vpr 62.74 MiB 1.20 62208 -1 -1 1 0.02 -1 -1 29292 -1 -1 0 1 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64248 1 1 1 2 0 1 2 3 3 9 -1 auto 24.5 MiB 0.00 2 2 3 0 3 0 62.7 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.977e-06 3.819e-06 6.0052e-05 4.1473e-05 -1 -1 -1 -1 14 13 1 53894 0 3251.56 361.284 0.00 0.000931173 0.000869506 318 537 -1 13 1 1 1 42 40 1.13321 nan -1.13321 -1.13321 0 0 4350.07 483.341 0.00 0.00 0.00 -1 -1 0.00 0.000874226 0.000841585 +k6_N10_mem32K_40nm.xml single_ff.v common 1.74 vpr 62.74 MiB 1.18 62208 -1 -1 1 0.02 -1 -1 29468 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64248 2 1 3 4 1 3 4 3 3 9 -1 auto 24.5 MiB 0.00 6 6 9 5 1 3 62.7 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 1.0056e-05 6.641e-06 8.6351e-05 6.6564e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00100009 0.000935434 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00115951 0.00111916 +k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.90 vpr 62.25 MiB 1.38 62208 -1 -1 1 0.02 -1 -1 29984 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 63740 2 1 3 4 1 3 4 3 3 9 -1 auto 24.0 MiB 0.00 6 6 9 5 1 3 62.2 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 1.6518e-05 1.1629e-05 8.3068e-05 6.0697e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000966192 0.000897504 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000961777 0.000923814 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc/config/golden_results.txt index 919720b66b..6798abce8a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_timing_no_sdc/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml mkPktMerge.v common 18.64 vpr 68.68 MiB 0.15 16588 -1 -1 2 0.14 -1 -1 33680 -1 -1 43 311 15 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 70328 311 156 972 1128 1 953 525 28 28 784 memory auto 29.0 MiB 0.43 9306 216459 81370 124762 10327 68.7 MiB 1.23 0.02 3.96757 -4422.94 -3.96757 3.96757 1.99 0.0055271 0.00489462 0.594444 0.523451 -1 -1 -1 -1 36 14708 20 4.25198e+07 1.05374e+07 1.86960e+06 2384.70 9.73 2.38769 2.10211 60012 360096 -1 13625 12 2932 3661 921536 275737 4.35536 4.35536 -4857.74 -4.35536 -16.7192 -0.318417 2.30301e+06 2937.52 0.63 0.34 0.31 -1 -1 0.63 0.170436 0.153664 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml mkPktMerge.v common 11.03 odin 619.85 MiB 5.14 634728 -1 -1 2 0.09 -1 -1 34816 -1 -1 43 311 15 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71800 311 156 972 1128 1 953 525 28 28 784 memory auto 31.0 MiB 0.26 18730 9136 197406 68626 118543 10237 70.1 MiB 0.56 0.01 4.81396 3.68545 -4313.24 -3.68545 3.68545 0.60 0.00249616 0.00220913 0.24992 0.220674 -1 -1 -1 -1 40 14133 17 4.25198e+07 1.05374e+07 2.03169e+06 2591.44 2.10 0.824624 0.737341 62360 400487 -1 13372 13 2874 3403 928204 274043 3.86375 3.86375 -4754.06 -3.86375 -26.664 -0.360359 2.55406e+06 3257.73 0.08 0.21 0.23 -1 -1 0.08 0.0960566 0.088839 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/hdl_include_odin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/hdl_include_odin/config/golden_results.txt index f19725cfd8..2598ff0926 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/hdl_include_odin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/hdl_include_odin/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 2.61 vpr 62.39 MiB 0.07 9224 -1 -1 4 0.25 -1 -1 34556 -1 -1 78 99 1 0 success v8.0.0-11852-g026644d7f-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-11-21T16:04:00 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing 63888 99 130 378 508 1 260 308 14 14 196 clb auto 23.3 MiB 0.07 836 35634 7872 13338 14424 62.4 MiB 0.06 0.00 30 1863 18 4.32e+06 2.46e+06 504535. 2574.16 0.99 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics_modified.v common 1.48 odin 97.12 MiB 0.19 99456 -1 -1 4 0.20 -1 -1 33708 -1 -1 77 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65108 99 130 378 508 1 264 307 13 13 169 clb auto 23.6 MiB 0.03 2217 834 80002 17611 37329 25062 63.6 MiB 0.06 0.00 38 1591 8 3.33e+06 2.43e+06 504671. 2986.22 0.18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt index f0282e9bf5..0379d64b18 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_k6_frac_N8_22nm.xml single_wire.v common 1.34 vpr 75.71 MiB -1 -1 0.07 20608 1 0.01 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77532 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 2 3 0 0 3 75.7 MiB 0.48 0.00 0.2714 0.2714 -0.2714 -0.2714 nan 0.40 1.4684e-05 9.512e-06 8.1482e-05 5.6821e-05 75.7 MiB 0.48 75.7 MiB 0.07 8 16 1 6.79088e+06 0 166176. 575.005 0.15 0.000912133 0.000836449 20206 45088 -1 18 1 1 1 141 56 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.01 0.00 0.04 -1 -1 0.01 0.000776852 0.0007249 - fixed_k6_frac_N8_22nm.xml single_ff.v common 1.51 vpr 75.95 MiB -1 -1 0.08 20852 1 0.02 -1 -1 33716 -1 -1 1 2 0 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77776 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 22 24 9 1 1 7 76.0 MiB 0.47 0.00 0.930505 0.74674 -1.43836 -0.74674 0.74674 0.39 1.1513e-05 7.851e-06 8.3564e-05 6.0773e-05 76.0 MiB 0.47 76.0 MiB 0.07 20 31 1 6.79088e+06 13472 414966. 1435.87 0.24 0.000928712 0.000851847 22510 95286 -1 32 1 2 2 231 42 0.74674 0.74674 -1.43836 -0.74674 0 0 503264. 1741.40 0.03 0.00 0.08 -1 -1 0.03 0.000833737 0.000775898 - fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 2.74 vpr 76.62 MiB -1 -1 0.26 22392 3 0.07 -1 -1 37308 -1 -1 67 99 1 0 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78456 99 130 240 229 1 225 297 17 17 289 -1 unnamed_device -1 -1 978 866 19107 2257 1105 15745 76.6 MiB 0.61 0.00 2.26688 1.84068 -122.242 -1.84068 1.84068 0.39 0.000595647 0.000527536 0.0138425 0.0123349 76.6 MiB 0.61 76.6 MiB 0.13 34 1974 43 6.79088e+06 1.45062e+06 618332. 2139.56 0.79 0.175076 0.154945 25102 150614 -1 1739 14 569 895 60631 18120 2.0466 2.0466 -143.082 -2.0466 -0.04337 -0.04337 787024. 2723.27 0.04 0.03 0.13 -1 -1 0.04 0.0355147 0.0319235 - fixed_k6_frac_N8_22nm.xml diffeq1.v common 9.26 vpr 78.62 MiB -1 -1 0.36 26868 15 0.31 -1 -1 37472 -1 -1 47 162 0 5 success v8.0.0-12401-g2b0120e4a-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-13T13:41:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 80512 162 96 817 258 1 691 310 17 17 289 -1 unnamed_device -1 -1 7341 6689 25462 269 7038 18155 78.6 MiB 1.27 0.01 22.1608 21.0485 -1573.19 -21.0485 21.0485 0.38 0.00201699 0.00177192 0.0590804 0.052726 78.6 MiB 1.27 78.6 MiB 0.26 54 12827 26 6.79088e+06 2.61318e+06 949917. 3286.91 5.15 0.794403 0.715337 28846 232421 -1 11184 19 3449 7611 967200 252634 20.9913 20.9913 -1571.36 -20.9913 0 0 1.17392e+06 4061.99 0.06 0.26 0.21 -1 -1 0.06 0.158612 0.144189 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_k6_frac_N8_22nm.xml single_wire.v common 1.12 vpr 74.28 MiB -1 -1 0.07 17288 1 0.02 -1 -1 29952 -1 -1 0 1 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76060 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 2 3 0 0 3 74.3 MiB 0.33 0.00 0.2714 0.2714 -0.2714 -0.2714 nan 0.23 6.503e-06 3.533e-06 5.0242e-05 3.32e-05 74.3 MiB 0.33 74.3 MiB 0.09 8 18 1 6.79088e+06 0 166176. 575.005 0.12 0.000951163 0.000890501 20206 45088 -1 18 1 1 1 110 40 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.01 0.00 0.02 -1 -1 0.01 0.000854953 0.000803008 +fixed_k6_frac_N8_22nm.xml single_ff.v common 1.16 vpr 73.50 MiB -1 -1 0.07 17284 1 0.02 -1 -1 30368 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75264 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 20 20 9 0 3 6 73.5 MiB 0.32 0.00 0.62144 0.62144 -1.18776 -0.62144 0.62144 0.23 8.816e-06 5.612e-06 7.0467e-05 5.1282e-05 73.5 MiB 0.32 73.5 MiB 0.08 20 27 1 6.79088e+06 13472 414966. 1435.87 0.15 0.000938983 0.000872608 22510 95286 -1 27 1 2 2 155 34 0.74674 0.74674 -1.31306 -0.74674 0 0 503264. 1741.40 0.02 0.00 0.05 -1 -1 0.02 0.000942198 0.000876165 +fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 2.07 vpr 74.55 MiB -1 -1 0.22 18436 3 0.06 -1 -1 33120 -1 -1 67 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76344 99 130 240 229 1 221 297 17 17 289 -1 unnamed_device -1 -1 875 831 15147 1842 1372 11933 74.6 MiB 0.45 0.00 1.77902 1.6707 -126.688 -1.6707 1.6707 0.23 0.000547799 0.000515562 0.010528 0.00994883 74.6 MiB 0.45 74.6 MiB 0.14 32 1830 14 6.79088e+06 1.45062e+06 586450. 2029.24 0.44 0.0908544 0.0829961 24814 144142 -1 1586 13 517 851 46748 14508 2.0466 2.0466 -137.082 -2.0466 -0.16867 -0.16867 744469. 2576.02 0.03 0.03 0.07 -1 -1 0.03 0.0292137 0.0271944 +fixed_k6_frac_N8_22nm.xml diffeq1.v common 6.63 vpr 76.43 MiB -1 -1 0.32 23044 15 0.29 -1 -1 33828 -1 -1 46 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78260 162 96 817 258 1 692 309 17 17 289 -1 unnamed_device -1 -1 7537 6452 26409 275 7390 18744 76.4 MiB 0.94 0.01 22.1138 21.2087 -1557.26 -21.2087 21.2087 0.23 0.00161758 0.0015186 0.0512946 0.0480432 76.4 MiB 0.94 76.4 MiB 0.23 52 12973 34 6.79088e+06 2.59971e+06 926341. 3205.33 3.30 0.639081 0.591661 28558 226646 -1 11227 22 3275 7622 1002575 262444 20.6757 20.6757 -1527 -20.6757 0 0 1.14541e+06 3963.36 0.04 0.21 0.12 -1 -1 0.04 0.133352 0.124998 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt index 39aa722dac..5099867db8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 9.38 vpr 77.35 MiB -1 -1 0.36 22280 1 0.10 -1 -1 35580 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79208 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.5 MiB 0.18 1862 38583 13232 21153 4198 77.4 MiB 0.24 0.00 5.12303 -624.562 -5.12303 5.12303 0.45 0.00115671 0.00104931 0.13445 0.124537 -1 -1 -1 -1 64 3969 9 4.93594e+06 1.0962e+06 976140. 4980.31 5.77 0.971386 0.907233 31408 195022 -1 3606 8 821 857 201107 78801 4.57723 4.57723 -666.876 -4.57723 0 0 1.23909e+06 6321.90 0.06 0.12 0.38 -1 -1 0.06 0.0628918 0.0600921 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 7.77 vpr 77.61 MiB -1 -1 0.36 22212 1 0.08 -1 -1 35140 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79472 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.6 MiB 0.18 1862 38583 13232 21153 4198 77.6 MiB 0.37 0.00 5.12303 -624.562 -5.12303 5.12303 0.55 0.00210597 0.00194049 0.204405 0.191731 -1 -1 -1 -1 64 3993 10 4.93594e+06 1.0962e+06 976140. 4980.31 3.98 0.785401 0.735059 31408 195022 -1 3592 9 794 830 166912 64369 4.57723 4.57723 -658.916 -4.57723 0 0 1.23909e+06 6321.90 0.07 0.13 0.32 -1 -1 0.07 0.068841 0.0645644 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 3.19 vpr 75.32 MiB -1 -1 0.19 18304 1 0.05 -1 -1 31624 -1 -1 12 130 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77132 130 40 596 562 1 355 185 14 14 196 dsp_top auto 36.6 MiB 0.09 3373 1886 37005 12673 19524 4808 75.3 MiB 0.12 0.00 5.12303 5.12303 -646.14 -5.12303 5.12303 0.19 0.000916918 0.000858498 0.0697929 0.0654605 -1 -1 -1 -1 80 3637 13 4.93594e+06 1.0962e+06 1.21529e+06 6200.44 1.24 0.346556 0.321815 33264 246902 -1 3285 7 680 743 143030 53497 4.57723 4.57723 -709.755 -4.57723 0 0 1.50824e+06 7695.10 0.03 0.04 0.18 -1 -1 0.03 0.0250628 0.0238864 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common_--router_algorithm_parallel 3.25 vpr 75.23 MiB -1 -1 0.18 18304 1 0.05 -1 -1 31636 -1 -1 12 130 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77032 130 40 596 562 1 355 185 14 14 196 dsp_top auto 36.1 MiB 0.09 3373 1886 37005 12673 19524 4808 75.2 MiB 0.12 0.00 5.12303 5.12303 -646.14 -5.12303 5.12303 0.19 0.000943675 0.000883542 0.0696327 0.0652863 -1 -1 -1 -1 80 3614 31 4.93594e+06 1.0962e+06 1.21529e+06 6200.44 1.29 0.380851 0.353915 33264 246902 -1 3269 7 690 753 144671 54345 4.57723 4.57723 -668.704 -4.57723 0 0 1.50824e+06 7695.10 0.03 0.04 0.18 -1 -1 0.03 0.025089 0.0239052 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt index 4e167973fd..e5f0a5ef17 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 9.61 vpr 79.62 MiB -1 -1 0.81 23308 1 0.11 -1 -1 37544 -1 -1 23 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 81536 130 40 1147 997 1 585 196 14 14 196 dsp_top auto 40.6 MiB 0.64 2711 47992 15247 26403 6342 79.6 MiB 0.47 0.01 6.04823 -699.558 -6.04823 6.04823 0.48 0.00203985 0.00179993 0.208906 0.186707 -1 -1 -1 -1 108 5255 25 4.93594e+06 1.40315e+06 1.55765e+06 7947.21 4.22 0.825967 0.736098 36552 325092 -1 4721 19 2233 2309 243533 83581 7.64092 7.64092 -760.756 -7.64092 0 0 1.93951e+06 9895.46 0.09 0.19 0.61 -1 -1 0.09 0.108869 0.100506 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 4.56 vpr 77.94 MiB -1 -1 0.40 19460 1 0.06 -1 -1 33392 -1 -1 23 130 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79808 130 40 1147 997 1 592 196 14 14 196 dsp_top auto 38.9 MiB 0.28 5185 2742 51406 16747 29054 5605 77.9 MiB 0.19 0.00 7.18035 6.03913 -683.447 -6.03913 6.03913 0.19 0.000994417 0.00090745 0.0955057 0.0872879 -1 -1 -1 -1 118 5148 28 4.93594e+06 1.40315e+06 1.66654e+06 8502.75 1.82 0.398108 0.356929 37820 362924 -1 5094 24 2395 2501 322053 103825 7.0462 7.0462 -729.408 -7.0462 0 0 2.11586e+06 10795.2 0.05 0.11 0.28 -1 -1 0.05 0.0596597 0.0549484 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt index b1825addf7..b4be4f88fe 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 48.72 vpr 1.18 GiB 42 758 0 0 0 0 success v8.0.0-12506-gd5dc5f7b8 release IPO VTR_ASSERT_LEVEL=2 GNU 11.5.0 on Linux-5.4.0-171-generic x86_64 2025-04-26T07:14:03 qlsof01.quicklogic.com /home/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 1240720 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1075.1 MiB 12.14 186170 63157 219808 34278 166444 19086 1191.3 MiB 7.46 0.11 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.02 0.0246574 0.0210761 1.78411 1.4367 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 7.54 -1 -1 1191.3 MiB 4.03 3.22991 2.72734 1191.3 MiB -1 1.82 +3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 36.90 vpr 1.18 GiB 42 749 0 0 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1239156 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1076.1 MiB 8.02 181772 63669 220151 34297 170189 15665 1190.0 MiB 5.97 0.09 5.43671 4.9834 -5379.72 -3.9834 2.7577 0.01 0.021728 0.0171066 1.5315 1.23086 74208 5.86903 18737 1.48189 26177 36020 11211877 1692426 0 0 2.60031e+07 21349.0 16 354380 4692432 -1 5.06256 2.57234 -4972.33 -4.06256 0 0 4.92 -1 -1 1190.0 MiB 3.24 2.67847 2.24237 1190.0 MiB -1 1.11 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt index 2ba2885179..fccdbcc238 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 73.49 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12506-gd5dc5f7b8 release IPO VTR_ASSERT_LEVEL=2 GNU 11.5.0 on Linux-5.4.0-171-generic x86_64 2025-04-26T07:14:03 qlsof01.quicklogic.com /home/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 1423216 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1074.8 MiB 12.24 180137 58272 230944 40790 173771 16383 1389.9 MiB 7.97 0.12 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.02551 0.0218529 1.92289 1.55523 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 9.53 -1 -1 1389.9 MiB 9.59 3.30445 2.79009 1389.9 MiB -1 17.61 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 53.85 vpr 1.36 GiB 42 749 0 0 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1421896 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1076.2 MiB 7.99 177076 58479 231119 40825 176329 13965 1388.6 MiB 6.38 0.10 5.0611 5.01815 -4172.98 -4.01815 2.37031 0.04 0.0271112 0.0211186 1.73144 1.39322 100824 7.97406 32812 2.59506 28894 40551 43377071 9674443 0 0 2.54084e+07 20860.8 17 2001132 6214436 -1 5.14007 2.63151 -5380.59 -4.14007 0 0 6.67 -1 -1 1388.6 MiB 7.37 2.93688 2.46247 1388.6 MiB -1 11.48 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt index abc45194ec..0fca53d0af 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 2.31 vpr 72.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74048 130 150 1169 1319 1 886 363 12 12 144 clb auto 32.2 MiB 1.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00628067 0.00572957 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.95 vpr 72.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73772 130 150 1216 1366 1 933 370 12 12 144 clb auto 32.4 MiB 1.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00606424 0.00546366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.01 vpr 70.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 130 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72496 130 150 1169 1319 1 885 365 12 12 144 clb auto 30.7 MiB 0.64 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00297157 0.00275967 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.02 vpr 70.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 94 130 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72360 130 150 1216 1366 1 925 374 12 12 144 clb auto 30.9 MiB 0.64 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00367422 0.00335011 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt index 94e710b87f..22162983f2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.05 vpr 66.01 MiB -1 -1 0.86 26896 5 0.23 -1 -1 36624 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67592 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 152 432 67 335 30 66.0 MiB 0.02 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000412775 0.000360271 0.0136111 0.012803 -1 -1 -1 -1 138 4.31250 57 1.78125 181 343 11634 2077 646728 646728 138825. 3856.24 15 3164 19284 -1 2.14648 2.14648 -94.9192 -2.14648 0 0 0.04 -1 -1 66.0 MiB 0.03 0.0339384 0.0288063 66.0 MiB -1 0.00 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.21 vpr 69.14 MiB -1 -1 0.76 26288 4 0.18 -1 -1 36060 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70796 11 2 303 283 2 78 28 7 7 49 clb auto 29.6 MiB 0.27 285 784 175 539 70 69.1 MiB 0.05 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000707376 0.000615193 0.0194274 0.0173585 -1 -1 -1 -1 313 4.34722 112 1.55556 114 177 3842 1019 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.07112 1.86791 -165.31 -2.07112 0 0 0.05 -1 -1 69.1 MiB 0.03 0.0450009 0.0414951 69.1 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.14 vpr 64.26 MiB -1 -1 0.43 23432 5 0.11 -1 -1 32996 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65804 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.03 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.00065772 0.000611252 0.00512282 0.00475225 -1 -1 -1 -1 136 4.12121 61 1.84848 149 320 10235 1961 646728 646728 138825. 3856.24 17 3164 19284 -1 2.10277 2.10277 -91.6521 -2.10277 0 0 0.01 -1 -1 64.3 MiB 0.01 0.015528 0.0140237 64.3 MiB -1 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.26 vpr 67.65 MiB -1 -1 0.42 23076 4 0.10 -1 -1 32996 -1 -1 15 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69272 11 2 303 283 2 85 28 7 7 49 clb auto 28.3 MiB 0.11 462 289 1204 263 848 93 67.6 MiB 0.02 0.00 2.20327 2.04719 -154.888 -2.04719 1.90466 0.00 0.000393064 0.000350687 0.0147201 0.0132752 -1 -1 -1 -1 314 3.97468 124 1.56962 130 211 4049 1168 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.02047 1.86775 -152.224 -2.02047 0 0 0.02 -1 -1 67.6 MiB 0.01 0.0289116 0.0265626 67.6 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt index 7f41d46c07..59b50f5fb2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analytic_placer/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.75 vpr 67.64 MiB -1 -1 0.42 22416 3 0.08 -1 -1 36896 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69264 99 130 344 474 1 227 298 12 12 144 clb auto 28.8 MiB 0.22 846 1293 248 869 176 67.6 MiB 0.10 0.00 1.87518 -117.076 -1.87518 1.87518 0.33 0.000961535 0.000869555 0.00580355 0.00550747 -1 -1 -1 -1 38 1541 12 5.66058e+06 4.21279e+06 319130. 2216.18 1.43 0.231487 0.210357 12522 62564 -1 1321 9 430 670 30619 10041 1.9175 1.9175 -131.199 -1.9175 -0.126268 -0.104429 406292. 2821.48 0.02 0.04 0.09 -1 -1 0.02 0.0283489 0.0264305 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.75 vpr 66.56 MiB -1 -1 0.22 18444 3 0.07 -1 -1 33084 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68156 99 130 344 474 1 228 298 12 12 144 clb auto 27.1 MiB 0.11 863 800 1293 264 867 162 66.6 MiB 0.05 0.00 1.86362 1.90582 -117.68 -1.90582 1.90582 0.10 0.00141467 0.00134058 0.00469469 0.00450069 -1 -1 -1 -1 40 1473 16 5.66058e+06 4.21279e+06 333335. 2314.82 0.41 0.158549 0.14543 12666 64609 -1 1318 11 405 616 29250 9869 1.99389 1.99389 -129.176 -1.99389 -0.260939 -0.108257 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0188218 0.0176413 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt index f90dc9de59..ef929ce944 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.63 vpr 75.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77436 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.6 MiB 3.56 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00332256 0.00272635 0.0920151 0.0793873 75.6 MiB 3.56 75.6 MiB 2.42 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.33 -1 -1 75.6 MiB 0.47 0.288973 0.25613 75.6 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.81 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78036 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.93 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00365979 0.00331889 0.047619 0.043593 76.2 MiB 0.93 76.2 MiB 0.59 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.37 -1 -1 76.2 MiB 0.25 0.188446 0.174077 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 11.93 vpr 105.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108360 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.8 MiB 9.23 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.16 0.00660438 0.00519941 0.309592 0.257376 105.8 MiB 9.23 105.8 MiB 4.50 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.18 -1 -1 105.8 MiB 0.93 0.709043 0.615207 105.8 MiB -1 0.16 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.73 vpr 76.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78628 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.8 MiB 3.59 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.09 0.0040653 0.00347069 0.103188 0.0899686 76.8 MiB 3.59 76.8 MiB 2.31 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.37 -1 -1 76.8 MiB 0.47 0.321818 0.287107 76.8 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.99 vpr 73.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75272 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.5 MiB 1.50 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00134793 0.00116895 0.0412726 0.037508 73.5 MiB 1.50 73.5 MiB 1.00 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.5 MiB 0.21 0.133986 0.123306 73.5 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.85 vpr 74.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76012 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 74.2 MiB 0.45 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00194689 0.00183966 0.0262428 0.0250777 74.2 MiB 0.45 74.2 MiB 0.31 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 74.2 MiB 0.14 0.109517 0.104558 74.2 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.97 vpr 103.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 105908 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.4 MiB 5.51 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.10 0.0040146 0.00321723 0.20058 0.169138 103.4 MiB 5.51 103.4 MiB 3.08 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.37 -1 -1 103.4 MiB 0.62 0.478593 0.423018 103.4 MiB -1 0.10 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.96 vpr 74.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75928 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 74.1 MiB 1.48 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00146362 0.00127004 0.0414903 0.0377687 74.1 MiB 1.48 74.1 MiB 0.94 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 74.1 MiB 0.19 0.132442 0.12228 74.1 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt index 91c3630a8a..254e8980d3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.88 vpr 75.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77168 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.4 MiB 3.73 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00371221 0.00305644 0.097355 0.0840965 75.4 MiB 3.73 75.4 MiB 2.65 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.34 -1 -1 75.4 MiB 0.50 0.299102 0.265267 75.4 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.04 vpr 75.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77776 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.0 MiB 1.04 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00356373 0.00322411 0.0543939 0.0472155 76.0 MiB 1.04 76.0 MiB 0.69 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.39 -1 -1 76.0 MiB 0.32 0.22263 0.205375 76.0 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 14.50 vpr 105.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108280 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.7 MiB 11.89 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.16 0.0066784 0.00535245 0.30231 0.252682 105.7 MiB 11.89 105.7 MiB 7.07 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.11 -1 -1 105.7 MiB 0.94 0.707357 0.615217 105.7 MiB -1 0.16 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.83 vpr 76.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78264 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.4 MiB 3.68 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.11 0.00384755 0.00327555 0.103123 0.0900634 76.4 MiB 3.68 76.4 MiB 2.39 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.4 MiB 0.48 0.323332 0.288275 76.4 MiB -1 0.11 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.96 vpr 73.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75256 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.5 MiB 1.50 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00130999 0.0011343 0.0398538 0.0363276 73.5 MiB 1.50 73.5 MiB 0.99 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.5 MiB 0.20 0.125485 0.115291 73.5 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.83 vpr 73.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75488 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 73.7 MiB 0.44 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.0018618 0.0017582 0.0252235 0.0241253 73.7 MiB 0.44 73.7 MiB 0.30 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 73.7 MiB 0.13 0.105434 0.100685 73.7 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.83 vpr 103.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106096 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.6 MiB 5.44 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.10 0.00400719 0.00318597 0.197496 0.166668 103.6 MiB 5.44 103.6 MiB 3.03 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.36 -1 -1 103.6 MiB 0.61 0.470152 0.416048 103.6 MiB -1 0.10 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.96 vpr 74.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76680 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 74.9 MiB 1.46 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.0014072 0.0012202 0.0401495 0.0365056 74.9 MiB 1.46 74.9 MiB 0.93 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.14 -1 -1 74.9 MiB 0.18 0.129084 0.119139 74.9 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt index e03594be3e..644aaef3ed 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.66 vpr 75.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77168 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.4 MiB 3.54 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00377685 0.0031064 0.0971738 0.0840095 75.4 MiB 3.54 75.4 MiB 2.44 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.35 -1 -1 75.4 MiB 0.49 0.299893 0.266532 75.4 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.87 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78040 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.95 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.12 0.00361228 0.00324116 0.0472811 0.0432415 76.2 MiB 0.95 76.2 MiB 0.63 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.40 -1 -1 76.2 MiB 0.27 0.192439 0.178374 76.2 MiB -1 0.12 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 15.92 vpr 105.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108344 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.8 MiB 13.27 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.27 0.0064285 0.00513075 0.474187 0.399734 105.8 MiB 13.27 105.8 MiB 7.54 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.15 -1 -1 105.8 MiB 0.91 0.870133 0.753188 105.8 MiB -1 0.27 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.70 vpr 76.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78576 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.7 MiB 3.57 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.10 0.00387961 0.00328771 0.108944 0.0952913 76.7 MiB 3.57 76.7 MiB 2.29 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.32 -1 -1 76.7 MiB 0.51 0.337895 0.301103 76.7 MiB -1 0.10 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.98 vpr 73.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75508 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.7 MiB 1.51 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00129419 0.00112139 0.0396012 0.0361189 73.7 MiB 1.51 73.7 MiB 1.02 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.7 MiB 0.20 0.125649 0.115436 73.7 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.85 vpr 74.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76048 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 74.3 MiB 0.46 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00193898 0.00183351 0.0259418 0.0247952 74.3 MiB 0.46 74.3 MiB 0.31 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 74.3 MiB 0.13 0.106572 0.101755 74.3 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.86 vpr 103.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106320 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.8 MiB 5.47 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.10 0.00409629 0.0032917 0.204809 0.173341 103.8 MiB 5.47 103.8 MiB 3.02 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.36 -1 -1 103.8 MiB 0.62 0.480522 0.425743 103.8 MiB -1 0.10 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.93 vpr 74.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76676 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 74.9 MiB 1.46 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.0014319 0.00124465 0.0408116 0.037185 74.9 MiB 1.46 74.9 MiB 0.93 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 74.9 MiB 0.18 0.128752 0.118883 74.9 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt index 260e0e2c05..1f46ee94c8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 11.76 vpr 75.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77216 9 19 897 28 0 575 109 16 16 256 -1 mcnc_medium -1 -1 7102 6246 3749 356 2360 1033 75.4 MiB 10.60 0.01 5.59875 5.15754 -83.6777 -5.15754 nan 0.09 0.00367809 0.00303729 0.0800582 0.0701494 75.4 MiB 10.60 75.4 MiB 2.58 9765 17.0122 2613 4.55226 4147 20677 658214 114215 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.35541 nan -88.358 -5.35541 0 0 0.32 -1 -1 75.4 MiB 0.48 0.288075 0.253539 75.4 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.95 vpr 76.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 57 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77892 256 245 954 501 0 585 558 22 22 484 -1 mcnc_large -1 -1 7568 7468 23518 202 3225 20091 76.1 MiB 1.06 0.02 4.58215 4.06321 -789.076 -4.06321 nan 0.17 0.00395794 0.00352194 0.0546633 0.0494666 76.1 MiB 1.06 76.1 MiB 0.64 10448 17.8598 2871 4.90769 2610 5820 337031 73978 2.15576e+07 3.07196e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.29926 nan -860.162 -4.29926 0 0 0.37 -1 -1 76.1 MiB 0.29 0.21912 0.199431 76.1 MiB -1 0.17 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 34.79 vpr 105.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 284 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108284 10 10 2659 20 0 1371 304 22 22 484 -1 mcnc_large -1 -1 32736 26176 50333 12484 33100 4749 105.7 MiB 32.12 0.02 8.62387 6.83404 -65.9282 -6.83404 nan 0.15 0.0053571 0.00415525 0.333874 0.272699 105.7 MiB 32.12 105.7 MiB 4.39 39078 28.5033 10004 7.29686 9032 54400 2294214 310826 2.15576e+07 1.53059e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.03175 nan -67.1956 -7.03175 0 0 1.19 -1 -1 105.7 MiB 0.86 0.709263 0.607527 105.7 MiB -1 0.15 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 12.51 vpr 76.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78100 41 35 1006 76 0 566 161 16 16 256 -1 mcnc_medium -1 -1 7257 6649 5842 273 2922 2647 76.3 MiB 11.37 0.02 5.58018 4.9431 -137.944 -4.9431 nan 0.09 0.00696141 0.00638215 0.115593 0.094552 76.3 MiB 11.37 76.3 MiB 2.39 10043 17.7438 2739 4.83922 3885 20440 636556 113525 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.06598 nan -144.027 -5.06598 0 0 0.35 -1 -1 76.3 MiB 0.47 0.340764 0.297617 76.3 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.77 vpr 73.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75492 9 19 897 28 0 573 109 16 16 256 -1 mcnc_medium -1 -1 6908 6255 4529 398 2936 1195 73.7 MiB 4.30 0.00 5.79498 4.95412 -82.8956 -4.95412 nan 0.04 0.00152532 0.00135451 0.0426663 0.0389156 73.7 MiB 4.30 73.7 MiB 1.10 9742 17.0315 2618 4.57692 4440 22553 733607 128435 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.29908 nan -85.521 -5.29908 0 0 0.11 -1 -1 73.7 MiB 0.20 0.131945 0.121002 73.7 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.84 vpr 74.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76064 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7554 7460 5137 56 892 4189 74.3 MiB 0.44 0.01 5.01539 4.43785 -787.81 -4.43785 nan 0.05 0.00195616 0.00184187 0.0141376 0.0136883 74.3 MiB 0.44 74.3 MiB 0.31 10209 17.4812 2812 4.81507 2325 5207 293343 64225 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 16 47664 245996 -1 4.5769 nan -866.798 -4.5769 0 0 0.13 -1 -1 74.3 MiB 0.13 0.0984378 0.0940982 74.3 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.75 vpr 103.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 281 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106352 10 10 2659 20 0 1385 301 22 22 484 -1 mcnc_large -1 -1 32437 26329 47677 11320 31685 4672 103.9 MiB 15.31 0.01 7.86298 6.97012 -66.6328 -6.97012 nan 0.10 0.00397088 0.00318949 0.231283 0.19425 103.9 MiB 15.31 103.9 MiB 3.13 39327 28.3949 10114 7.30253 9446 56175 2430685 325649 2.15576e+07 1.51442e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.25735 nan -68.7995 -7.25735 0 0 0.36 -1 -1 103.9 MiB 0.65 0.507466 0.446109 103.9 MiB -1 0.10 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.44 vpr 74.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76644 41 35 1006 76 0 564 161 16 16 256 -1 mcnc_medium -1 -1 7552 6671 7590 431 3792 3367 74.8 MiB 3.98 0.00 5.51469 5.01871 -140.744 -5.01871 nan 0.04 0.00144175 0.00124531 0.0424494 0.0384452 74.8 MiB 3.98 74.8 MiB 0.90 10043 17.8067 2733 4.84574 3791 19758 636928 113707 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.42495 nan -150.307 -5.42495 0 0 0.12 -1 -1 74.8 MiB 0.18 0.132169 0.121825 74.8 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt index e9dd4dbf47..9650b13954 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.77 vpr 75.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77552 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.7 MiB 3.65 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00374471 0.00311178 0.0942637 0.0815881 75.7 MiB 3.65 75.7 MiB 2.54 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.34 -1 -1 75.7 MiB 0.49 0.296978 0.264335 75.7 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.88 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78040 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.98 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.14 0.0035648 0.00318679 0.0499558 0.0460383 76.2 MiB 0.98 76.2 MiB 0.63 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.38 -1 -1 76.2 MiB 0.27 0.197871 0.183716 76.2 MiB -1 0.14 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.47 vpr 105.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108040 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.5 MiB 12.86 0.04 9.04847 6.65923 -63.8387 -6.65923 nan 0.29 0.0116739 0.00965721 0.534688 0.455619 105.5 MiB 12.86 105.5 MiB 7.17 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.12 -1 -1 105.5 MiB 1.62 1.25142 1.10117 105.5 MiB -1 0.28 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.88 vpr 76.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78644 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.8 MiB 3.64 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.10 0.00418085 0.00352692 0.113479 0.0974767 76.8 MiB 3.64 76.8 MiB 2.34 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.8 MiB 0.56 0.365085 0.323172 76.8 MiB -1 0.10 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.98 vpr 73.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75156 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.4 MiB 1.50 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00128454 0.00111303 0.0395362 0.0360246 73.4 MiB 1.50 73.4 MiB 1.00 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.4 MiB 0.20 0.12461 0.114379 73.4 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.88 vpr 73.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75600 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 73.8 MiB 0.46 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00192489 0.00182045 0.0260401 0.0248881 73.8 MiB 0.46 73.8 MiB 0.32 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 73.8 MiB 0.13 0.10889 0.104001 73.8 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 7.07 vpr 103.13 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 105608 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.1 MiB 5.54 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.11 0.00435779 0.00356447 0.210495 0.178632 103.1 MiB 5.54 103.1 MiB 3.03 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.37 -1 -1 103.1 MiB 0.71 0.536104 0.475656 103.1 MiB -1 0.10 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.95 vpr 74.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76676 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 74.9 MiB 1.48 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00146993 0.00127676 0.0412975 0.0376274 74.9 MiB 1.48 74.9 MiB 0.94 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 74.9 MiB 0.18 0.131172 0.120916 74.9 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt index c179a99eb7..9c476d8cf9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.02 vpr 75.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77392 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.6 MiB 3.80 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.10 0.00366255 0.00300248 0.0988722 0.0856346 75.6 MiB 3.80 75.6 MiB 2.67 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.33 -1 -1 75.6 MiB 0.58 0.329873 0.296269 75.6 MiB -1 0.10 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.88 vpr 76.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77908 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.1 MiB 0.98 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00361625 0.00323438 0.0481778 0.0440548 76.1 MiB 0.98 76.1 MiB 0.62 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.38 -1 -1 76.1 MiB 0.27 0.193703 0.179342 76.1 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.93 vpr 105.69 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108228 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.7 MiB 13.43 0.04 9.04847 6.65923 -63.8387 -6.65923 nan 0.25 0.0114469 0.00942196 0.523317 0.437298 105.7 MiB 13.43 105.7 MiB 7.67 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.08 -1 -1 105.7 MiB 1.54 1.21056 1.05802 105.7 MiB -1 0.25 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.95 vpr 76.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78780 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.9 MiB 3.70 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.11 0.00501429 0.0044287 0.113755 0.0975648 76.9 MiB 3.70 76.9 MiB 2.39 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.35 -1 -1 76.9 MiB 0.54 0.357802 0.31714 76.9 MiB -1 0.11 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.98 vpr 73.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75376 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 7063 6058 5107 505 3249 1353 73.6 MiB 1.50 0.00 5.86674 5.06655 -84.1154 -5.06655 nan 0.04 0.00131826 0.00112811 0.0396638 0.0361588 73.6 MiB 1.50 73.6 MiB 1.00 9718 17.3226 2608 4.64884 4802 24486 815662 139279 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.26809 nan -87.1269 -5.26809 0 0 0.11 -1 -1 73.6 MiB 0.20 0.125368 0.115196 73.6 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.84 vpr 74.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76048 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 7547 7526 18877 167 2072 16638 74.3 MiB 0.44 0.01 5.52179 4.16523 -782.008 -4.16523 nan 0.05 0.00177936 0.00167561 0.0243357 0.0232049 74.3 MiB 0.44 74.3 MiB 0.31 10323 17.6764 2836 4.85616 2378 5665 320238 68793 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 15 47664 245996 -1 4.41619 nan -842.585 -4.41619 0 0 0.13 -1 -1 74.3 MiB 0.13 0.100987 0.0961912 74.3 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.86 vpr 103.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 106296 10 10 2659 20 0 1335 308 22 22 484 -1 mcnc_large -1 -1 29594 25215 39790 8187 27516 4087 103.8 MiB 5.45 0.01 8.26681 6.54748 -64.031 -6.54748 nan 0.10 0.00399373 0.00319673 0.19842 0.1673 103.8 MiB 5.45 103.8 MiB 3.05 37789 28.3064 9714 7.27640 8647 53317 2224368 295725 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75359 nan -65.2231 -6.75359 0 0 0.37 -1 -1 103.8 MiB 0.62 0.4737 0.418915 103.8 MiB -1 0.10 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.98 vpr 74.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76628 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 7718 6599 7104 383 3537 3184 74.8 MiB 1.51 0.00 5.60618 5.02988 -143.324 -5.02988 nan 0.04 0.00142071 0.00122298 0.0409288 0.0370286 74.8 MiB 1.51 74.8 MiB 0.93 9956 16.9320 2725 4.63435 4001 20451 637770 113848 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.3225 nan -147.435 -5.3225 0 0 0.11 -1 -1 74.8 MiB 0.18 0.129258 0.1191 74.8 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt index 5bcf12189e..870d467dea 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.03 vpr 75.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 114 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77596 9 19 897 28 0 606 142 16 16 256 -1 mcnc_medium -1 -1 6550 6536 3472 155 2648 669 75.8 MiB 3.88 0.01 5.7154 5.4597 -89.3112 -5.4597 nan 0.10 0.00370216 0.00307222 0.0661479 0.0591146 75.8 MiB 3.88 75.8 MiB 2.88 10481 17.3240 2782 4.59835 4539 23483 740476 125213 1.05632e+07 6.14392e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.72947 nan -94.1462 -5.72947 0 0 0.32 -1 -1 75.8 MiB 0.50 0.310788 0.282654 75.8 MiB -1 0.10 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 3.32 vpr 76.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 179 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78468 256 245 954 501 0 742 680 22 22 484 -1 mcnc_large -1 -1 9274 7572 60460 2284 20333 37843 76.6 MiB 2.36 0.02 5.23911 4.2903 -840.323 -4.2903 nan 0.13 0.00384619 0.00344153 0.09353 0.0842417 76.6 MiB 2.36 76.6 MiB 1.70 11049 14.8908 3078 4.14825 2733 6987 297544 68761 2.15576e+07 9.64703e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.65189 nan -884.263 -4.65189 0 0 0.41 -1 -1 76.6 MiB 0.28 0.244915 0.224675 76.6 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 18.12 vpr 106.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108712 10 10 2659 20 0 1430 382 22 22 484 -1 mcnc_large -1 -1 30097 26681 50242 8485 37651 4106 106.2 MiB 14.49 0.06 9.5895 7.11784 -67.5602 -7.11784 nan 0.29 0.0120588 0.0101618 0.577448 0.487406 106.2 MiB 14.49 106.2 MiB 8.21 40770 28.5105 10462 7.31608 8938 61030 2640427 332495 2.15576e+07 1.95096e+07 3.51389e+06 7260.09 17 64568 594370 -1 7.68543 nan -70.9452 -7.68543 0 0 1.09 -1 -1 106.2 MiB 1.70 1.23429 1.08029 106.2 MiB -1 0.29 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.65 vpr 76.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 124 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78780 41 35 1006 76 0 665 200 16 16 256 -1 mcnc_medium -1 -1 8699 7144 11296 577 6471 4248 76.9 MiB 4.33 0.02 6.42009 5.14527 -151.192 -5.14527 nan 0.09 0.0040038 0.00343256 0.111382 0.0964207 76.9 MiB 4.33 76.9 MiB 3.06 11808 17.7564 3134 4.71278 5035 27959 918932 152826 1.05632e+07 6.68286e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.4847 nan -160.203 -5.4847 0 0 0.34 -1 -1 76.9 MiB 0.64 0.362116 0.322037 76.9 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 2.30 vpr 73.69 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 119 9 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75460 9 19 897 28 0 656 147 16 16 256 -1 mcnc_medium -1 -1 9465 7387 7500 653 5233 1614 73.7 MiB 1.83 0.00 6.84375 5.63197 -90.064 -5.63197 nan 0.04 0.00131718 0.00113322 0.0412125 0.0374588 73.7 MiB 1.83 73.7 MiB 1.31 11218 17.1267 2998 4.57710 4710 22969 767847 128278 1.05632e+07 6.41339e+06 1.26944e+06 4958.75 18 28900 206586 -1 6.05963 nan -96.1476 -6.05963 0 0 0.11 -1 -1 73.7 MiB 0.20 0.124582 0.114375 73.7 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.44 vpr 74.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 179 256 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76536 256 245 954 501 0 743 680 22 22 484 -1 mcnc_large -1 -1 9276 7596 60460 2199 20502 37759 74.7 MiB 1.05 0.01 5.23911 4.36438 -841.143 -4.36438 nan 0.05 0.00190419 0.00179456 0.050434 0.0478291 74.7 MiB 1.05 74.7 MiB 0.80 10985 14.7847 3053 4.10902 2501 6468 260198 59947 2.15576e+07 9.64703e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.95172 nan -902.835 -4.95172 0 0 0.13 -1 -1 74.7 MiB 0.12 0.127516 0.121495 74.7 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 7.61 vpr 103.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 105968 10 10 2659 20 0 1387 386 22 22 484 -1 mcnc_large -1 -1 28407 25969 52334 9214 38970 4150 103.5 MiB 6.11 0.01 8.84225 6.87893 -67.3793 -6.87893 nan 0.11 0.00402499 0.00321975 0.204491 0.172907 103.5 MiB 6.11 103.5 MiB 3.61 40223 29.0000 10345 7.45854 8587 59599 2538983 323136 2.15576e+07 1.97252e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.19431 nan -69.2992 -7.19431 0 0 0.37 -1 -1 103.5 MiB 0.68 0.486628 0.42993 103.5 MiB -1 0.10 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 2.41 vpr 75.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 125 41 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77028 41 35 1006 76 0 665 201 16 16 256 -1 mcnc_medium -1 -1 9806 7711 9021 479 5180 3362 75.2 MiB 1.92 0.00 7.51244 5.32876 -152.164 -5.32876 nan 0.04 0.00139746 0.00121371 0.038505 0.0351175 75.2 MiB 1.92 75.2 MiB 1.38 12022 18.0782 3251 4.88872 4219 22486 741180 125076 1.05632e+07 6.73675e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.72072 nan -160.849 -5.72072 0 0 0.11 -1 -1 75.2 MiB 0.19 0.125713 0.115984 75.2 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt index e8dd91ee6a..e6f574ed41 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt @@ -1,6 +1,6 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 25.85 vpr 83.03 MiB -1 -1 18.57 47636 3 1.01 -1 -1 38980 -1 -1 48 196 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 85020 196 193 800 0 1 594 438 20 20 400 -1 vtr_extra_small -1 -1 4169 3142 106806 24519 69152 13135 83.0 MiB 3.45 0.01 2.78642 2.3599 -1119.38 -2.3599 2.3599 0.11 0.00336886 0.00290601 0.267623 0.235425 83.0 MiB 3.45 83.0 MiB 1.54 5164 8.82735 1542 2.63590 1808 2713 166829 48700 2.07112e+07 3.13491e+06 1.26946e+06 3173.65 11 38988 203232 -1 2.79177 2.79177 -1205.37 -2.79177 0 0 0.33 -1 -1 83.0 MiB 0.20 0.427611 0.384897 83.0 MiB -1 0.11 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.71 vpr 77.02 MiB -1 -1 0.44 22136 3 0.13 -1 -1 37044 -1 -1 68 99 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78864 99 130 264 0 1 227 298 20 20 400 -1 vtr_extra_small -1 -1 1534 732 61988 20558 27121 14309 77.0 MiB 1.17 0.01 1.84094 1.63182 -117.029 -1.63182 1.63182 0.10 0.00116098 0.00102609 0.0719437 0.0636329 77.0 MiB 1.17 77.0 MiB 0.48 1289 7.67262 408 2.42857 432 671 35594 10787 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 12 39388 210115 -1 2.0326 2.0326 -137.711 -2.0326 0 0 0.32 -1 -1 77.0 MiB 0.12 0.146262 0.115522 77.0 MiB -1 0.10 - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 45.09 vpr 132.19 MiB -1 -1 6.50 65292 8 5.27 -1 -1 44656 -1 -1 246 385 2 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 135364 385 362 3324 0 1 2378 996 30 30 900 -1 vtr_small -1 -1 45961 31243 503168 167206 308523 27439 132.2 MiB 27.49 0.08 11.3485 9.24445 -10104.3 -9.24445 9.24445 0.52 0.0110533 0.00983869 1.90464 1.67809 132.2 MiB 27.49 132.2 MiB 14.11 42437 17.9590 11048 4.67541 10359 33405 1843617 333376 4.8774e+07 1.47499e+07 6.56785e+06 7297.61 17 120772 1084977 -1 9.50495 9.50495 -10508.2 -9.50495 0 0 2.27 -1 -1 132.2 MiB 0.99 2.49904 2.2274 132.2 MiB -1 0.52 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 13.73 vpr 86.61 MiB -1 -1 3.85 35472 16 0.66 -1 -1 39332 -1 -1 61 45 3 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 88684 45 32 936 0 1 764 142 20 20 400 -1 vtr_extra_small -1 -1 7941 6580 16792 4505 10418 1869 86.6 MiB 7.12 0.02 11.8934 10.8778 -6730.96 -10.8778 10.8778 0.15 0.00604523 0.0052746 0.299411 0.249607 86.6 MiB 7.12 86.6 MiB 4.84 11265 14.8029 2859 3.75690 3304 9224 705116 168424 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 16 44576 305072 -1 11.1238 11.1238 -7296.13 -11.1238 0 0 0.55 -1 -1 86.6 MiB 0.49 0.557197 0.483674 86.6 MiB -1 0.15 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.92 vpr 76.71 MiB -1 -1 0.85 26400 4 0.19 -1 -1 36732 -1 -1 15 11 0 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78556 11 2 140 0 2 80 28 20 20 400 -1 vtr_extra_small -1 -1 371 277 994 274 621 99 76.7 MiB 0.79 0.00 2.14417 2.10685 -170.205 -2.10685 1.95087 0.09 0.000829747 0.000696435 0.0253099 0.0218497 76.7 MiB 0.79 76.7 MiB 0.47 484 6.54054 125 1.68919 154 271 5642 1534 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.24362 1.99822 -177.023 -2.24362 0 0 0.28 -1 -1 76.7 MiB 0.04 0.058266 0.0520206 76.7 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 10.93 vpr 81.47 MiB -1 -1 8.17 44960 3 0.58 -1 -1 35420 -1 -1 49 196 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 83424 196 193 800 0 1 601 439 20 20 400 -1 vtr_extra_small -1 -1 4328 3107 92124 17877 63452 10795 81.5 MiB 1.40 0.00 2.56454 2.37946 -1137.82 -2.37946 2.37946 0.04 0.00178127 0.00165821 0.10902 0.100911 81.5 MiB 1.40 81.5 MiB 0.67 5067 8.55912 1503 2.53885 1660 2444 142383 40675 2.07112e+07 3.18881e+06 1.26946e+06 3173.65 10 38988 203232 -1 2.76727 2.76727 -1220.28 -2.76727 0 0 0.11 -1 -1 81.5 MiB 0.09 0.177856 0.166478 81.5 MiB -1 0.04 +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.25 vpr 75.09 MiB -1 -1 0.22 18120 3 0.06 -1 -1 33376 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76888 99 130 264 0 1 226 298 20 20 400 -1 vtr_extra_small -1 -1 998 719 42088 12988 22077 7023 75.1 MiB 0.53 0.00 2.00298 1.89487 -117.095 -1.89487 1.89487 0.04 0.000554324 0.000520099 0.0266827 0.0251102 75.1 MiB 0.53 75.1 MiB 0.26 1273 7.62275 391 2.34132 403 645 32624 10084 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 11 39388 210115 -1 2.02782 2.02782 -132.929 -2.02782 0 0 0.12 -1 -1 75.1 MiB 0.03 0.0463242 0.0435356 75.1 MiB -1 0.04 +k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 19.55 vpr 130.40 MiB -1 -1 2.98 61476 8 2.69 -1 -1 42300 -1 -1 244 385 2 1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 133528 385 362 3324 0 1 2373 994 30 30 900 -1 vtr_small -1 -1 44934 30685 486878 158175 303508 25195 130.4 MiB 11.33 0.04 10.9569 9.14069 -10026.4 -9.14069 9.14069 0.18 0.0077434 0.00718841 0.881181 0.806571 130.4 MiB 11.33 130.4 MiB 6.18 41636 17.6573 10780 4.57167 10078 33334 1771649 321112 4.8774e+07 1.46421e+07 6.56785e+06 7297.61 16 120772 1084977 -1 9.28426 9.28426 -10368.8 -9.28426 0 0 0.73 -1 -1 130.4 MiB 0.68 1.30657 1.20736 130.4 MiB -1 0.18 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 5.83 vpr 84.36 MiB -1 -1 1.71 31904 16 0.38 -1 -1 35012 -1 -1 59 45 3 1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86380 45 32 936 0 1 764 140 20 20 400 -1 vtr_extra_small -1 -1 7967 6824 18290 3791 13097 1402 84.4 MiB 2.80 0.00 11.7422 10.6015 -6978.52 -10.6015 10.6015 0.06 0.00176941 0.00157755 0.109079 0.0975886 84.4 MiB 2.80 84.4 MiB 1.80 11182 14.6938 2948 3.87385 3523 9991 831731 205110 2.07112e+07 5.21975e+06 1.91495e+06 4787.38 14 44576 305072 -1 11.0577 11.0577 -7502.5 -11.0577 0 0 0.19 -1 -1 84.4 MiB 0.20 0.207642 0.189577 84.4 MiB -1 0.06 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.47 vpr 74.79 MiB -1 -1 0.41 23072 4 0.10 -1 -1 32968 -1 -1 15 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76588 11 2 140 0 2 81 28 20 20 400 -1 vtr_extra_small -1 -1 344 282 1246 289 767 190 74.8 MiB 0.36 0.00 2.1429 2.10685 -161.57 -2.10685 1.95087 0.04 0.000405833 0.000363466 0.0151591 0.0137261 74.8 MiB 0.36 74.8 MiB 0.22 481 6.41333 125 1.66667 162 273 5235 1511 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.13367 2.00787 -169.877 -2.13367 0 0 0.10 -1 -1 74.8 MiB 0.02 0.0317134 0.0289823 74.8 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt index 9155e1a0c2..427c61db82 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.37 vpr 75.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77532 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 75.7 MiB 3.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.7 MiB 3.24 75.7 MiB 2.52 10470 18.5638 2823 5.00532 4441 21451 721238 120368 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.44204 nan -88.1999 -5.44204 0 0 0.32 -1 -1 75.7 MiB 0.45 0.190621 0.172257 75.7 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.70 vpr 76.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78028 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 -1 76.2 MiB 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 76.2 MiB 0.69 76.2 MiB 0.61 10067 17.2380 2785 4.76884 2224 4785 262051 58317 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 14 47664 245996 -1 5.09713 nan -915.356 -5.09713 0 0 0.38 -1 -1 76.2 MiB 0.25 0.146815 0.136123 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.28 vpr 76.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78496 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 76.7 MiB 3.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 76.7 MiB 3.09 76.7 MiB 2.27 10759 18.7766 2936 5.12391 3972 20025 643838 113062 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.52727 nan -151.75 -5.52727 0 0 0.34 -1 -1 76.7 MiB 0.46 0.206081 0.184898 76.7 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.90 vpr 73.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75312 9 19 897 28 0 562 110 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 73.5 MiB 1.40 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 73.5 MiB 1.40 73.5 MiB 1.01 10384 18.5098 2834 5.05169 4200 20769 686232 118555 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.71537 nan -90.8975 -5.71537 0 0 0.11 -1 -1 73.5 MiB 0.19 0.0859551 0.0793351 73.5 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.81 vpr 74.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76044 256 245 954 501 0 584 557 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 -1 74.3 MiB 0.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 74.3 MiB 0.35 74.3 MiB 0.31 10173 17.4195 2800 4.79452 2175 4597 261480 57693 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 19 47664 245996 -1 5.19666 nan -941.622 -5.19666 0 0 0.13 -1 -1 74.3 MiB 0.14 0.0962437 0.0917702 74.3 MiB -1 0.05 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.89 vpr 74.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76296 41 35 1006 76 0 588 160 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 74.5 MiB 1.37 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 74.5 MiB 1.37 74.5 MiB 0.96 11092 18.8639 3046 5.18027 4224 20724 680603 119637 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.63987 nan -156.834 -5.63987 0 0 0.11 -1 -1 74.5 MiB 0.19 0.0932043 0.0862731 74.5 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt index bd1a356f7b..fd08f0ad96 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.48 vpr 75.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 79 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77452 9 19 897 28 0 613 107 16 16 256 -1 mcnc_medium -1 -1 7227 6446 4661 444 2922 1295 75.6 MiB 3.30 0.01 5.83587 5.20235 -84.7514 -5.20235 nan 0.09 0.00365365 0.00308713 0.0953072 0.0828485 75.6 MiB 3.30 75.6 MiB 2.61 9964 16.2810 2709 4.42647 4690 20859 701687 124089 1.05632e+07 4.25763e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.47836 nan -87.8661 -5.47836 0 0 0.35 -1 -1 75.6 MiB 0.51 0.314162 0.28034 75.6 MiB -1 0.09 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.82 vpr 76.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78032 256 245 954 501 0 598 557 22 22 484 -1 mcnc_large -1 -1 8430 8247 28037 277 4264 23496 76.2 MiB 0.95 0.02 5.00844 4.05195 -786.983 -4.05195 nan 0.13 0.00372964 0.0033122 0.0643989 0.0586623 76.2 MiB 0.95 76.2 MiB 0.58 10883 18.1990 2937 4.91137 2442 5565 332488 69751 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 12 47664 245996 -1 4.40791 nan -837.951 -4.40791 0 0 0.37 -1 -1 76.2 MiB 0.26 0.206289 0.19121 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 15.95 vpr 105.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108108 10 10 2659 20 0 1500 308 22 22 484 -1 mcnc_large -1 -1 33647 26777 51219 12453 33951 4815 105.6 MiB 12.21 0.05 7.95426 6.65363 -64.7441 -6.65363 nan 0.32 0.01158 0.00952696 0.683148 0.577318 105.6 MiB 12.21 105.6 MiB 8.23 39550 26.3667 10138 6.75867 10136 56388 2554636 337283 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.10986 nan -67.2122 -7.10986 0 0 1.12 -1 -1 105.6 MiB 1.79 1.41673 1.23449 105.6 MiB -1 0.32 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 3.96 vpr 76.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78624 41 35 1006 76 0 665 161 16 16 256 -1 mcnc_medium -1 -1 7612 6958 7590 343 3947 3300 76.8 MiB 2.84 0.02 6.23108 5.15201 -145.389 -5.15201 nan 0.09 0.00454121 0.00387629 0.099122 0.086103 76.8 MiB 2.84 76.8 MiB 2.13 10685 16.0677 2885 4.33835 4384 18462 592965 106217 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.45169 nan -154.246 -5.45169 0 0 0.32 -1 -1 76.8 MiB 0.51 0.354223 0.314944 76.8 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 1.81 vpr 73.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75240 9 19 897 28 0 628 108 16 16 256 -1 mcnc_medium -1 -1 7133 6654 3706 357 2411 938 73.5 MiB 1.29 0.00 5.58018 4.92812 -82.703 -4.92812 nan 0.04 0.00133109 0.00116537 0.0346442 0.0318046 73.5 MiB 1.29 73.5 MiB 0.99 10212 16.2871 2746 4.37959 5878 26871 986532 171228 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 26 28900 206586 -1 5.21469 nan -86.576 -5.21469 0 0 0.11 -1 -1 73.5 MiB 0.25 0.138514 0.12617 73.5 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.79 vpr 74.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 57 256 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76048 256 245 954 501 0 596 558 22 22 484 -1 mcnc_large -1 -1 8442 8222 21222 240 2369 18613 74.3 MiB 0.43 0.01 4.85109 4.26724 -789.819 -4.26724 nan 0.05 0.00190644 0.00179282 0.0276929 0.0264649 74.3 MiB 0.43 74.3 MiB 0.31 10906 18.2987 2932 4.91946 2356 5389 309032 65263 2.15576e+07 3.07196e+06 1.49107e+06 3080.73 12 47664 245996 -1 4.73179 nan -857.452 -4.73179 0 0 0.13 -1 -1 74.3 MiB 0.12 0.0983845 0.0940581 74.3 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 6.00 vpr 103.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 105968 10 10 2659 20 0 1510 309 22 22 484 -1 mcnc_large -1 -1 31802 27364 49377 11982 32709 4686 103.5 MiB 4.46 0.01 8.38409 6.51429 -63.2845 -6.51429 nan 0.11 0.00399244 0.00319165 0.242268 0.203607 103.5 MiB 4.46 103.5 MiB 3.23 40850 27.0530 10492 6.94834 11089 63641 3035099 392249 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 19 64568 594370 -1 6.78146 nan -65.8802 -6.78146 0 0 0.36 -1 -1 103.5 MiB 0.75 0.532777 0.46754 103.5 MiB -1 0.10 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 1.71 vpr 74.69 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 41 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76480 41 35 1006 76 0 678 159 16 16 256 -1 mcnc_medium -1 -1 7799 7097 7039 323 3443 3273 74.7 MiB 1.24 0.00 5.82238 4.98732 -145.614 -4.98732 nan 0.04 0.00141449 0.00121811 0.0398379 0.0362583 74.7 MiB 1.24 74.7 MiB 0.97 10391 15.3260 2846 4.19764 4879 22033 706386 126210 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.2747 nan -150.182 -5.2747 0 0 0.11 -1 -1 74.7 MiB 0.20 0.134281 0.12341 74.7 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt index 353d272ff5..fb566fc7be 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.96 vpr 75.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77136 9 19 897 28 0 571 109 16 16 256 -1 mcnc_medium -1 -1 6849 6197 3749 306 2447 996 75.3 MiB 3.80 0.01 5.6777 5.15854 -84.4388 -5.15854 nan 0.12 0.00372518 0.00308527 0.0851251 0.0744623 75.3 MiB 3.80 75.3 MiB 2.72 9547 16.7491 2591 4.54561 4007 19117 612422 105847 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.57046 nan -89.3939 -5.57046 0 0 0.36 -1 -1 75.3 MiB 0.45 0.290389 0.260271 75.3 MiB -1 0.12 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.92 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78044 256 245 954 501 0 584 556 22 22 484 -1 mcnc_large -1 -1 7414 7336 16551 117 1750 14684 76.2 MiB 0.96 0.02 4.79868 3.95956 -780.296 -3.95956 nan 0.14 0.0037776 0.00334019 0.0431145 0.0394451 76.2 MiB 0.96 76.2 MiB 0.63 10156 17.3904 2785 4.76884 2499 5829 309976 67350 2.15576e+07 2.96417e+06 1.49107e+06 3080.73 17 47664 245996 -1 4.43922 nan -858.538 -4.43922 0 0 0.40 -1 -1 76.2 MiB 0.31 0.225991 0.20914 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 18.50 vpr 105.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 263 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108088 10 10 2659 20 0 1335 283 22 22 484 -1 mcnc_large -1 -1 29142 24368 34619 6112 24966 3541 105.6 MiB 14.79 0.04 8.99039 6.64595 -64.2305 -6.64595 nan 0.30 0.011351 0.00921126 0.534655 0.453947 105.6 MiB 14.79 105.6 MiB 8.92 36909 27.6472 9531 7.13933 8973 57196 2436221 318880 2.15576e+07 1.41741e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.07899 nan -66.0192 -7.07899 0 0 1.11 -1 -1 105.6 MiB 1.75 1.29851 1.13315 105.6 MiB -1 0.30 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.12 vpr 76.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78196 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7414 6419 7538 405 3643 3490 76.4 MiB 3.99 0.01 5.66659 5.10396 -142.048 -5.10396 nan 0.09 0.00395858 0.00331812 0.0974473 0.0845959 76.4 MiB 3.99 76.4 MiB 2.72 9920 17.3124 2710 4.72949 3957 20035 633461 111527 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.31293 nan -148.764 -5.31293 0 0 0.36 -1 -1 76.4 MiB 0.47 0.311907 0.278187 76.4 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 2.02 vpr 73.69 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75456 9 19 897 28 0 563 111 16 16 256 -1 mcnc_medium -1 -1 7098 5977 5165 481 3314 1370 73.7 MiB 1.56 0.00 5.87393 5.10533 -84.2691 -5.10533 nan 0.04 0.00131956 0.00113694 0.041535 0.0377592 73.7 MiB 1.56 73.7 MiB 1.05 9429 16.7776 2543 4.52491 4233 21427 685976 119142 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.42217 nan -87.2542 -5.42217 0 0 0.11 -1 -1 73.7 MiB 0.19 0.127837 0.117331 73.7 MiB -1 0.04 +k6_frac_N10_40nm.xml des.pre-vpr.blif common 0.81 vpr 74.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 54 256 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75928 256 245 954 501 0 584 555 22 22 484 -1 mcnc_large -1 -1 7542 7463 5115 58 915 4142 74.1 MiB 0.43 0.01 5.52179 4.5111 -812.738 -4.5111 nan 0.05 0.00197039 0.00184439 0.0143901 0.0139178 74.1 MiB 0.43 74.1 MiB 0.31 10180 17.4315 2798 4.79110 2290 5418 289765 61404 2.15576e+07 2.91028e+06 1.49107e+06 3080.73 12 47664 245996 -1 4.73551 nan -877.111 -4.73551 0 0 0.13 -1 -1 74.1 MiB 0.12 0.0864303 0.0827945 74.1 MiB -1 0.05 +k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 7.31 vpr 103.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 269 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 105676 10 10 2659 20 0 1330 289 22 22 484 -1 mcnc_large -1 -1 29067 24555 40399 8417 28233 3749 103.2 MiB 5.84 0.01 8.57662 6.48829 -62.7527 -6.48829 nan 0.10 0.00409594 0.00328245 0.215641 0.181933 103.2 MiB 5.84 103.2 MiB 3.37 37342 28.0767 9643 7.25038 9194 59469 2527516 336331 2.15576e+07 1.44975e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.74005 nan -65.3498 -6.74005 0 0 0.37 -1 -1 103.2 MiB 0.68 0.4971 0.438015 103.2 MiB -1 0.10 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 2.02 vpr 75.24 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 41 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77048 41 35 1006 76 0 592 159 16 16 256 -1 mcnc_medium -1 -1 7434 6630 6609 294 3295 3020 75.2 MiB 1.53 0.00 5.72346 5.17082 -143.976 -5.17082 nan 0.04 0.00146496 0.00126846 0.0396467 0.0361 75.2 MiB 1.53 75.2 MiB 0.99 9848 16.6351 2709 4.57601 4387 22649 730292 125901 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.09467 nan -146.142 -5.09467 0 0 0.11 -1 -1 75.2 MiB 0.21 0.135398 0.124609 75.2 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt index d7bb035e33..ea502a1888 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 24.78 vpr 83.23 MiB -1 -1 18.50 47880 3 1.03 -1 -1 38848 -1 -1 50 196 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 85228 196 193 800 389 1 591 440 20 20 400 -1 vtr_extra_small -1 -1 3715 3554 3784 38 823 2923 83.2 MiB 2.24 0.02 2.85588 2.57265 -1175.96 -2.57265 2.57265 0.10 0.00362627 0.00313967 0.0281499 0.026191 83.2 MiB 2.24 83.2 MiB 1.59 5468 9.39519 1600 2.74914 1643 2642 175568 48502 2.07112e+07 3.2427e+06 1.26946e+06 3173.65 13 38988 203232 -1 2.92546 2.92546 -1279.3 -2.92546 0 0 0.33 -1 -1 83.2 MiB 0.23 0.194282 0.17603 83.2 MiB -1 0.10 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.30 vpr 77.05 MiB -1 -1 0.46 21648 3 0.11 -1 -1 36796 -1 -1 69 99 1 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78904 99 130 240 229 1 219 299 20 20 400 -1 vtr_extra_small -1 -1 897 855 16283 1900 1766 12617 77.1 MiB 0.85 0.01 1.95754 1.93615 -150.064 -1.93615 1.93615 0.10 0.00114824 0.00101953 0.0225391 0.0202679 77.1 MiB 0.85 77.1 MiB 0.55 1415 8.84375 420 2.62500 390 656 29567 8292 2.07112e+07 4.26669e+06 1.31074e+06 3276.84 10 39388 210115 -1 1.99132 1.99132 -170.793 -1.99132 0 0 0.34 -1 -1 77.1 MiB 0.05 0.0576019 0.0526431 77.1 MiB -1 0.10 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 12.74 vpr 86.56 MiB -1 -1 3.84 35864 16 0.69 -1 -1 39076 -1 -1 61 45 3 1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 88636 45 32 936 77 1 765 142 20 20 400 -1 vtr_extra_small -1 -1 7990 6993 2362 101 1016 1245 86.6 MiB 6.20 0.02 12.1921 10.5297 -7133.55 -10.5297 10.5297 0.16 0.00556384 0.00434574 0.083545 0.0720334 86.6 MiB 6.20 86.6 MiB 4.77 11420 14.9869 2979 3.90945 3498 9480 737557 180691 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 14 44576 305072 -1 10.8282 10.8282 -7490.44 -10.8282 0 0 0.55 -1 -1 86.6 MiB 0.48 0.322984 0.290732 86.6 MiB -1 0.16 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.69 vpr 76.73 MiB -1 -1 0.87 26256 4 0.17 -1 -1 36604 -1 -1 15 11 0 0 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78576 11 2 140 13 2 79 28 20 20 400 -1 vtr_extra_small -1 -1 425 276 658 98 289 271 76.7 MiB 0.68 0.00 2.38519 2.10685 -169.375 -2.10685 1.95087 0.09 0.000833002 0.000701647 0.018572 0.0162134 76.7 MiB 0.68 76.7 MiB 0.44 404 5.53425 120 1.64384 174 291 5454 1630 2.07112e+07 808410 1.12964e+06 2824.09 11 37792 180905 -1 2.17742 1.95241 -171.997 -2.17742 0 0 0.30 -1 -1 76.7 MiB 0.04 0.0564754 0.0510591 76.7 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 10.30 vpr 80.81 MiB -1 -1 7.98 44580 3 0.55 -1 -1 35600 -1 -1 50 196 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 82748 196 193 800 389 1 589 440 20 20 400 -1 vtr_extra_small -1 -1 3998 3782 18832 248 3091 15493 80.8 MiB 0.98 0.00 2.85588 2.47185 -1156.3 -2.47185 2.47185 0.04 0.00168497 0.00156454 0.0301984 0.0284919 80.8 MiB 0.98 80.8 MiB 0.63 5632 9.71035 1634 2.81724 1596 2379 162444 45554 2.07112e+07 3.2427e+06 1.26946e+06 3173.65 13 38988 203232 -1 2.84177 2.84177 -1268.87 -2.84177 0 0 0.11 -1 -1 80.8 MiB 0.09 0.10219 0.0967507 80.8 MiB -1 0.04 +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.10 vpr 75.12 MiB -1 -1 0.22 18848 3 0.06 -1 -1 33092 -1 -1 69 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76928 99 130 240 229 1 222 299 20 20 400 -1 vtr_extra_small -1 -1 1001 943 16283 1928 655 13700 75.1 MiB 0.38 0.00 1.95754 1.93615 -151.243 -1.93615 1.93615 0.04 0.000560801 0.000528944 0.0125238 0.0118835 75.1 MiB 0.38 75.1 MiB 0.25 1463 8.97546 433 2.65644 390 644 29549 8534 2.07112e+07 4.26669e+06 1.31074e+06 3276.84 9 39388 210115 -1 1.99132 1.99132 -165.748 -1.99132 0 0 0.12 -1 -1 75.1 MiB 0.02 0.0301514 0.0284658 75.1 MiB -1 0.04 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 5.50 vpr 84.62 MiB -1 -1 1.70 32288 16 0.37 -1 -1 34992 -1 -1 59 45 3 1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86648 45 32 936 77 1 764 140 20 20 400 -1 vtr_extra_small -1 -1 8308 6790 6311 196 3112 3003 84.6 MiB 2.52 0.00 11.697 10.6608 -7088.74 -10.6608 10.6608 0.06 0.0017212 0.00152119 0.0484439 0.0441852 84.6 MiB 2.52 84.6 MiB 1.84 11366 14.9356 2988 3.92641 3444 9377 809880 202958 2.07112e+07 5.21975e+06 1.91495e+06 4787.38 14 44576 305072 -1 10.968 10.968 -7522.1 -10.968 0 0 0.18 -1 -1 84.6 MiB 0.19 0.144731 0.133909 84.6 MiB -1 0.06 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.43 vpr 74.66 MiB -1 -1 0.41 23076 4 0.10 -1 -1 32720 -1 -1 15 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76452 11 2 140 13 2 79 28 20 20 400 -1 vtr_extra_small -1 -1 441 361 112 19 45 48 74.7 MiB 0.32 0.00 2.32519 2.16196 -166.836 -2.16196 1.97742 0.04 0.000423315 0.000366933 0.00431636 0.00409724 74.7 MiB 0.32 74.7 MiB 0.21 486 6.65753 142 1.94521 190 278 5599 1612 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.17143 1.9491 -169.271 -2.17143 0 0 0.10 -1 -1 74.7 MiB 0.02 0.0206881 0.0191795 74.7 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index 37ed89929f..5828cffe60 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 1.86 vpr 61.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62636 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.05 1288 4445 682 3619 144 61.2 MiB 0.05 0.00 5.46014 -72.9505 -5.46014 5.46014 0.08 0.000682102 0.000589331 0.0191204 0.0168271 -1 -1 -1 -1 14 2036 29 2.43e+06 2.07e+06 -1 -1 0.92 0.219017 0.188624 3402 27531 -1 1911 15 1185 4098 215222 27160 6.9309 6.9309 -92.2142 -6.9309 0 0 -1 -1 0.01 0.09 0.03 -1 -1 0.01 0.0322472 0.0293972 - k4_n4_v7_longline_bidir.xml styr.blif common 1.71 vpr 60.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61932 10 10 253 263 1 165 89 11 11 121 clb auto 21.2 MiB 0.08 1219 4247 600 3483 164 60.5 MiB 0.06 0.00 4.42494 -53.3169 -4.42494 4.42494 0.10 0.000822212 0.000745517 0.0200899 0.0175819 -1 -1 -1 -1 18 2215 40 2.43e+06 2.07e+06 -1 -1 0.71 0.217702 0.191181 3282 34431 -1 2139 18 1151 3756 254207 31830 9.07319 9.07319 -108.035 -9.07319 0 0 -1 -1 0.02 0.11 0.03 -1 -1 0.02 0.0360271 0.0325274 - k4_n4_v7_l1_bidir.xml styr.blif common 2.28 vpr 61.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62500 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.06 1285 7613 1616 5547 450 61.0 MiB 0.11 0.00 6.9252 -85.9419 -6.9252 6.9252 0.14 0.00083663 0.000735935 0.0404209 0.0365528 -1 -1 -1 -1 10 1481 31 2.43e+06 2.07e+06 -1 -1 1.11 0.183783 0.164876 4482 22551 -1 1268 22 1168 4312 263452 47622 7.30329 7.30329 -93.8299 -7.30329 0 0 -1 -1 0.01 0.12 0.02 -1 -1 0.01 0.0404434 0.0363816 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.36 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61916 10 10 253 263 1 165 89 11 11 121 clb auto 21.3 MiB 0.09 1234 4643 666 3821 156 60.5 MiB 0.06 0.00 3.51175 -43.7413 -3.51175 3.51175 0.10 0.000796689 0.00069941 0.0254117 0.0229956 -1 -1 -1 -1 16 1911 27 2.43e+06 2.07e+06 -1 -1 2.14 0.308921 0.270668 3522 30407 -1 1965 30 1263 4698 759011 126866 28.7744 28.7744 -241.883 -28.7744 0 0 -1 -1 0.01 0.28 0.03 -1 -1 0.01 0.0527885 0.0460513 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_n4_v7_bidir.xml styr.blif common 1.10 vpr 59.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61076 10 10 253 263 1 171 92 11 11 121 clb auto 19.8 MiB 0.03 1829 1341 4439 719 3525 195 59.6 MiB 0.03 0.00 8.75156 5.95188 -76.2362 -5.95188 5.95188 0.04 0.000375655 0.00033896 0.0124555 0.0115006 -1 -1 -1 -1 14 2179 38 2.43e+06 2.16e+06 -1 -1 0.53 0.116142 0.100634 3402 27531 -1 1923 17 1033 3494 176707 22465 7.58177 7.58177 -95.383 -7.58177 0 0 -1 -1 0.00 0.04 0.01 -1 -1 0.00 0.0165416 0.0148353 +k4_n4_v7_longline_bidir.xml styr.blif common 0.94 vpr 59.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61128 10 10 253 263 1 171 92 11 11 121 clb auto 19.6 MiB 0.03 1829 1318 3611 426 3020 165 59.7 MiB 0.02 0.00 5.19817 4.47516 -54.2373 -4.47516 4.47516 0.04 0.000371685 0.000341208 0.00904562 0.00829329 -1 -1 -1 -1 17 2528 41 2.43e+06 2.16e+06 -1 -1 0.37 0.0884443 0.076351 3202 31699 -1 2252 25 1472 4968 313575 40767 9.40236 9.40236 -107.704 -9.40236 0 0 -1 -1 0.01 0.06 0.01 -1 -1 0.01 0.021414 0.0189892 +k4_n4_v7_l1_bidir.xml styr.blif common 1.08 vpr 59.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60748 10 10 253 263 1 171 92 11 11 121 clb auto 19.8 MiB 0.03 1829 1340 8579 1857 6361 361 59.3 MiB 0.04 0.00 11.3865 6.30908 -81.1511 -6.30908 6.30908 0.04 0.000363613 0.000327585 0.0176128 0.0160722 -1 -1 -1 -1 11 1565 28 2.43e+06 2.16e+06 -1 -1 0.46 0.0850231 0.0739457 4842 26035 -1 1365 23 1309 5061 314893 55846 8.55913 8.55913 -101.511 -8.55913 0 0 -1 -1 0.00 0.07 0.01 -1 -1 0.00 0.0200137 0.0177187 +k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.41 vpr 59.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60744 10 10 253 263 1 171 92 11 11 121 clb auto 19.4 MiB 0.03 1829 1326 4025 528 3322 175 59.3 MiB 0.03 0.00 4.50889 3.47884 -44.786 -3.47884 3.47884 0.04 0.00039629 0.000356464 0.0106549 0.00981345 -1 -1 -1 -1 16 2193 28 2.43e+06 2.16e+06 -1 -1 0.77 0.108064 0.0936688 3522 30407 -1 2061 19 1236 4213 766518 139225 14.4125 14.4125 -146.898 -14.4125 0 0 -1 -1 0.00 0.13 0.01 -1 -1 0.00 0.0175708 0.0157051 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt index 99bb28a826..508c613bc2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 2.33 vpr 66.02 MiB -1 -1 0.85 26768 5 0.17 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 432 67 335 30 66.0 MiB 0.03 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000423798 0.000369821 0.00844968 0.00761151 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.19 0.07328 0.0645326 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.03 0.01 -1 -1 0.00 0.0168546 0.0152174 - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 2.62 vpr 65.81 MiB -1 -1 0.84 26884 5 0.22 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67392 10 2 181 183 1 35 24 6 6 36 clb auto 26.8 MiB 0.05 152 432 67 335 30 65.8 MiB 0.02 0.00 2.14643 -92.8849 -2.14643 2.14643 0.05 0.000430785 0.000371967 0.00760808 0.00673261 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.40 0.162173 0.135998 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.05 0.01 -1 -1 0.00 0.0294148 0.0268014 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.33 vpr 64.67 MiB -1 -1 0.42 23428 5 0.11 -1 -1 33004 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66220 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 151 500 122 353 25 64.7 MiB 0.01 0.00 2.24217 2.14643 -91.6412 -2.14643 2.14643 0.01 0.000221696 0.000202947 0.00464158 0.00428583 -1 -1 -1 -1 12 169 17 646728 646728 19965.4 554.594 0.05 0.0321659 0.0276773 1696 3924 -1 165 16 218 500 9678 3037 2.12594 2.12594 -92.801 -2.12594 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.0098766 0.00881143 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 1.41 vpr 64.67 MiB -1 -1 0.41 23284 5 0.11 -1 -1 32956 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66220 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 151 500 122 353 25 64.7 MiB 0.01 0.00 2.24217 2.14643 -91.6412 -2.14643 2.14643 0.01 0.000229772 0.000210569 0.0047415 0.00439094 -1 -1 -1 -1 12 169 17 646728 646728 19965.4 554.594 0.12 0.0677947 0.0573383 1696 3924 -1 165 16 218 500 9678 3037 2.12594 2.12594 -92.801 -2.12594 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.00984046 0.00876813 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt index 5d7f440c1d..2c9677eeaf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary_heap/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_heap_binary 2.91 vpr 67.98 MiB -1 -1 0.40 22276 3 0.11 -1 -1 36796 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69616 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.20 0.00 1.86472 -118.834 -1.86472 1.86472 0.22 0.000979117 0.000879056 0.0638803 0.0581045 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.56 0.199818 0.181639 12522 62564 -1 1120 9 399 643 21323 6785 1.90702 1.90702 -133.259 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.10 -1 -1 0.02 0.0304906 0.0285332 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_heap_binary 1.68 vpr 66.47 MiB -1 -1 0.22 18824 3 0.06 -1 -1 33048 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68064 99 130 344 474 1 228 298 12 12 144 clb auto 27.1 MiB 0.10 1675 704 66963 20370 32791 13802 66.5 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.00058725 0.000551589 0.0407714 0.0382615 -1 -1 -1 -1 40 1452 18 5.66058e+06 4.21279e+06 333335. 2314.82 0.33 0.161727 0.148556 12666 64609 -1 1219 12 447 673 30224 10238 2.02932 2.02932 -138.474 -2.02932 -0.424985 -0.298787 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0189734 0.017725 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt index c1c2066692..027e0bb64c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.54 vpr 67.39 MiB -1 -1 0.42 22156 3 0.16 -1 -1 36544 -1 -1 71 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69008 99 130 344 474 1 225 301 13 13 169 clb auto 27.8 MiB 0.09 709 69853 20089 36202 13562 67.4 MiB 0.23 0.00 2.16096 -124.938 -2.16096 2.16096 0.29 0.000913323 0.000821579 0.0687918 0.0619499 -1 -1 -1 -1 30 1301 10 6.63067e+06 4.37447e+06 308771. 1827.05 1.05 0.343222 0.313014 11444 57198 -1 1153 11 545 813 32907 9964 1.99803 1.99803 -136.313 -1.99803 -0.30784 -0.0857401 382024. 2260.50 0.04 0.06 0.10 -1 -1 0.04 0.0301423 0.0279655 - k6_N10_mem32K_40nm.xml diffeq1.v common 13.02 vpr 70.71 MiB -1 -1 0.61 26808 15 0.59 -1 -1 38128 -1 -1 61 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72412 162 96 1009 950 1 665 324 16 16 256 mult_36 auto 31.1 MiB 0.36 5686 93732 25708 60129 7895 70.7 MiB 0.92 0.01 21.5854 -1586.88 -21.5854 21.5854 0.47 0.00359311 0.00328994 0.373845 0.344857 -1 -1 -1 -1 42 11019 36 1.21132e+07 5.26753e+06 637230. 2489.18 7.15 1.94736 1.79599 20148 122574 -1 9118 25 3874 8580 1140724 318272 22.5245 22.5245 -1660.58 -22.5245 0 0 799729. 3123.94 0.07 0.71 0.15 -1 -1 0.07 0.298338 0.280888 - k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 65.29 MiB -1 -1 0.11 20620 1 0.02 -1 -1 33040 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 1 1 1 2 0 1 2 3 3 9 -1 auto 27.0 MiB 0.00 2 3 0 3 0 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0264e-05 6.201e-06 6.8769e-05 4.6066e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00116982 0.00111262 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00106891 0.001042 - k6_N10_mem32K_40nm.xml single_ff.v common 0.54 vpr 65.06 MiB -1 -1 0.09 21000 1 0.02 -1 -1 33296 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66620 2 1 3 4 1 3 4 3 3 9 -1 auto 26.6 MiB 0.00 6 9 3 5 1 65.1 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.01 2.0617e-05 1.4741e-05 0.000141684 0.000107774 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.00168512 0.00158841 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00172391 0.0016612 - k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 5.58 vpr 67.37 MiB -1 -1 0.39 22284 3 0.08 -1 -1 36712 -1 -1 71 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68984 99 130 344 474 1 225 301 19 19 361 o auto 27.9 MiB 0.07 850 78925 21699 38013 19213 67.4 MiB 0.30 0.00 2.16428 -129.737 -2.16428 2.16428 1.74 0.000907451 0.000818758 0.097179 0.0888059 -1 -1 -1 -1 36 1162 10 1.79173e+07 4.37447e+06 833707. 2309.44 1.42 0.329975 0.298327 24998 161561 -1 1074 10 581 868 36231 9318 1.99581 1.99581 -134.677 -1.99581 -0.182839 -0.0660558 1.02328e+06 2834.56 0.12 0.05 0.23 -1 -1 0.12 0.0286893 0.0266338 - k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 20.39 vpr 77.82 MiB -1 -1 0.54 26812 15 0.47 -1 -1 38260 -1 -1 61 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79688 162 96 1009 950 1 665 324 24 24 576 i auto 30.8 MiB 0.33 7393 99292 28927 58867 11498 77.8 MiB 1.03 0.02 21.7254 -1657.33 -21.7254 21.7254 3.05 0.00462453 0.00428627 0.416981 0.375188 -1 -1 -1 -1 38 12380 31 3.08128e+07 5.26753e+06 1.42563e+06 2475.05 11.34 2.12533 1.94729 42274 284153 -1 10868 19 3672 8078 1198132 301968 22.4983 22.4983 -1725.65 -22.4983 0 0 1.79535e+06 3116.93 0.13 0.60 0.50 -1 -1 0.13 0.215504 0.199648 - k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.51 vpr 65.29 MiB -1 -1 0.10 20720 1 0.02 -1 -1 33044 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 1 1 1 2 0 1 2 4 4 16 i auto 26.9 MiB 0.00 3 3 0 0 3 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1044e-05 6.598e-06 7.3231e-05 5.0487e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.00113801 0.00107607 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.00158495 0.00154688 - k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.64 vpr 65.29 MiB -1 -1 0.10 20876 1 0.03 -1 -1 33324 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 2 1 3 4 1 3 4 4 4 16 i auto 27.0 MiB 0.00 7 9 0 1 8 65.3 MiB 0.00 0.00 0.55247 -0.955943 -0.55247 0.55247 0.00 1.4352e-05 9.526e-06 0.000103801 7.6571e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00161569 0.00152133 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00155787 0.00150496 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.50 vpr 65.64 MiB -1 -1 0.22 18108 3 0.06 -1 -1 33100 -1 -1 72 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67220 99 130 344 474 1 224 302 13 13 169 clb auto 25.6 MiB 0.04 1746 762 68106 19514 34631 13961 65.6 MiB 0.11 0.00 2.21168 1.87164 -122.901 -1.87164 1.87164 0.11 0.000566824 0.000532196 0.0404518 0.0379608 -1 -1 -1 -1 32 1396 14 6.63067e+06 4.42837e+06 323148. 1912.12 0.21 0.107686 0.0992932 11612 59521 -1 1378 10 517 775 49020 15288 2.04417 2.04417 -145.25 -2.04417 -0.103145 -0.0426347 396943. 2348.77 0.01 0.03 0.03 -1 -1 0.01 0.0164416 0.0153265 +k6_N10_mem32K_40nm.xml diffeq1.v common 6.00 vpr 69.36 MiB -1 -1 0.32 23432 15 0.29 -1 -1 33860 -1 -1 61 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71020 162 96 1009 950 1 667 324 16 16 256 mult_36 auto 29.4 MiB 0.17 9690 5422 80388 23076 51132 6180 69.4 MiB 0.37 0.01 24.8942 21.9154 -1692.2 -21.9154 21.9154 0.18 0.00173812 0.00163329 0.153793 0.144287 -1 -1 -1 -1 40 11149 48 1.21132e+07 5.26753e+06 612675. 2393.26 3.36 0.813007 0.753839 19892 118481 -1 8842 23 4046 9257 1093658 327616 22.4259 22.4259 -1741.35 -22.4259 0 0 771607. 3014.09 0.02 0.24 0.07 -1 -1 0.02 0.0906176 0.0849673 +k6_N10_mem32K_40nm.xml single_wire.v common 0.54 vpr 63.29 MiB -1 -1 0.07 16944 1 0.02 -1 -1 29952 -1 -1 0 1 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64812 1 1 1 2 0 1 2 3 3 9 -1 auto 25.1 MiB 0.00 2 2 3 0 3 0 63.3 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 9.856e-06 6.322e-06 6.7156e-05 4.5906e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.000919758 0.000860736 254 297 -1 1 1 1 1 15 7 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00100306 0.000968797 +k6_N10_mem32K_40nm.xml single_ff.v common 0.52 vpr 63.41 MiB -1 -1 0.07 17668 1 0.02 -1 -1 30356 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64936 2 1 3 4 1 3 4 3 3 9 -1 auto 24.8 MiB 0.00 6 6 9 3 5 1 63.4 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.785e-06 6.38e-06 7.7223e-05 5.8106e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.000973824 0.000911867 254 297 -1 2 2 3 3 56 20 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000905256 0.00086685 +k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 2.65 vpr 65.76 MiB -1 -1 0.22 18436 3 0.06 -1 -1 33052 -1 -1 72 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67336 99 130 344 474 1 224 302 19 19 361 o auto 26.0 MiB 0.04 2630 951 69118 18569 36933 13616 65.8 MiB 0.12 0.00 2.44032 1.89487 -136.14 -1.89487 1.89487 0.68 0.000539766 0.00050646 0.0406492 0.0379279 -1 -1 -1 -1 36 1362 12 1.79173e+07 4.42837e+06 833707. 2309.44 0.53 0.151737 0.13884 24998 161561 -1 1242 10 542 821 37855 9195 1.91637 1.91637 -141.984 -1.91637 -0.260117 -0.143334 1.02328e+06 2834.56 0.03 0.02 0.09 -1 -1 0.03 0.0162551 0.0151598 +k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 5.61 vpr 76.35 MiB -1 -1 0.32 23120 15 0.29 -1 -1 33824 -1 -1 61 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78180 162 96 1009 950 1 667 324 24 24 576 i auto 29.6 MiB 0.16 14162 6905 91508 24620 57078 9810 76.3 MiB 0.36 0.01 26.8808 21.7286 -1710.39 -21.7286 21.7286 1.13 0.00161823 0.00150226 0.14277 0.13281 -1 -1 -1 -1 32 12694 37 3.08128e+07 5.26753e+06 1.24505e+06 2161.54 1.58 0.433469 0.402017 39974 242477 -1 10860 26 4768 10723 1400040 362149 22.9048 22.9048 -1885.36 -22.9048 0 0 1.54255e+06 2678.04 0.05 0.28 0.13 -1 -1 0.05 0.0996599 0.0932181 +k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.53 vpr 63.49 MiB -1 -1 0.07 17292 1 0.02 -1 -1 29952 -1 -1 0 1 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65012 1 1 1 2 0 1 2 4 4 16 i auto 25.2 MiB 0.00 3 3 3 0 0 3 63.5 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.934e-06 3.883e-06 5.0918e-05 3.3941e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.000893435 0.000837561 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.000872761 0.000842502 +k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.52 vpr 63.87 MiB -1 -1 0.07 17284 1 0.02 -1 -1 30212 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65400 2 1 3 4 1 3 4 4 4 16 i auto 25.3 MiB 0.00 7 7 9 0 1 8 63.9 MiB 0.00 0.00 0.55247 0.55247 -0.955943 -0.55247 0.55247 0.00 9.45e-06 6.055e-06 7.4128e-05 5.5007e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.00 0.000962945 0.000893513 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.000900946 0.000865662 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt index 278399cb6d..36213e8953 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.77 vpr 65.95 MiB -1 -1 0.64 26892 5 0.17 -1 -1 36964 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67536 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 568 210 329 29 66.0 MiB 0.00 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 12 168 36 646728 646728 19965.4 554.594 0.12 0.0658358 0.0559906 1696 3924 -1 165 24 236 544 12437 3707 2.26842 2.26842 -94.6601 -2.26842 0 0 25971.8 721.439 0.00 0.03 0.00 -1 -1 0.00 0.0200385 0.0180231 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.33 vpr 63.90 MiB -1 -1 0.42 23044 5 0.11 -1 -1 32976 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65436 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 165 874 360 491 23 63.9 MiB 0.00 0.00 -1 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 12 194 14 646728 646728 19965.4 554.594 0.06 0.0291443 0.0248563 1696 3924 -1 170 14 189 408 8500 2615 2.16176 2.16176 -92.1884 -2.16176 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.00935016 0.00839602 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt index b44eab4cd1..ce4bad13f4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common_--check_route_full 14.98 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 13.82 4.4449e-05 3.636e-05 0.000492339 0.000302558 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.14 0.00246861 0.00204917 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00171876 0.00162871 - sub_tiles.xml sub_tiles.blif common_--check_route_quick 17.28 vpr 59.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60472 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.88 4.5558e-05 3.7864e-05 0.000392587 0.000316954 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00226581 0.00204304 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00121674 0.00115171 - sub_tiles.xml sub_tiles.blif common_--check_route_off 16.44 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.5 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.05 6.9962e-05 5.8494e-05 0.000570046 0.000472887 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.09 0.00239105 0.00217713 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00134624 0.00127449 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common_--check_route_full 4.64 vpr 56.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58356 6 7 19 26 0 19 26 3 3 9 -1 auto 18.2 MiB 0.00 51 51 216 43 63 110 57.0 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.91 2.1974e-05 1.7872e-05 0.000214717 0.000174149 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.0014845 0.00135375 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.02 -1 -1 0.00 0.00104161 0.000981047 +sub_tiles.xml sub_tiles.blif common_--check_route_quick 4.60 vpr 56.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58264 6 7 19 26 0 19 26 3 3 9 -1 auto 18.2 MiB 0.00 51 51 216 43 63 110 56.9 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.88 2.2618e-05 1.8402e-05 0.000210582 0.000169286 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00148036 0.00134883 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00104184 0.000979065 +sub_tiles.xml sub_tiles.blif common_--check_route_off 4.60 vpr 57.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58508 6 7 19 26 0 19 26 3 3 9 -1 auto 18.7 MiB 0.00 51 51 216 43 63 110 57.1 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.87 2.2558e-05 1.8397e-05 0.000209425 0.000168444 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00150663 0.00137577 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.02 -1 -1 0.00 0.0010416 0.000983957 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index 124aaee2a0..3046cedc5c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.66 vpr 66.09 MiB -1 -1 0.12 21064 1 0.03 -1 -1 33388 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67676 9 8 75 70 1 34 20 5 5 25 clb auto 27.2 MiB 0.65 100 74 24 47 3 66.1 MiB 0.00 0.00 2.48207 -28.4593 -2.48207 2.48207 0.02 0.000164662 0.000145718 0.00164144 0.00155216 -1 -1 -1 -1 38 129 6 151211 75605.7 48493.3 1939.73 0.18 0.0548944 0.0466047 2100 8065 -1 122 13 105 125 3874 2046 2.74837 2.74837 -33.9524 -2.74837 0 0 61632.8 2465.31 0.00 0.01 0.01 -1 -1 0.00 0.00954243 0.00888996 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 7.16 vpr 67.19 MiB -1 -1 0.14 21572 1 0.04 -1 -1 34020 -1 -1 6 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68800 19 18 308 249 1 134 43 5 5 25 clb auto 27.7 MiB 5.80 445 2068 454 1604 10 67.2 MiB 0.04 0.00 4.5386 -91.3528 -4.5386 4.5386 0.02 0.000449316 0.000397091 0.0186893 0.0169167 -1 -1 -1 -1 50 721 33 151211 151211 61632.8 2465.31 0.30 0.144091 0.126311 2268 9834 -1 620 20 733 1185 38218 18241 5.03997 5.03997 -109.631 -5.03997 0 0 77226.2 3089.05 0.00 0.04 0.01 -1 -1 0.00 0.0288144 0.0262691 53 83 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.13 vpr 64.34 MiB -1 -1 0.07 17600 1 0.02 -1 -1 30512 -1 -1 3 9 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65888 9 8 75 70 1 34 20 5 5 25 clb auto 25.5 MiB 0.38 114 98 74 21 50 3 64.3 MiB 0.00 0.00 2.48207 2.48207 -27.0891 -2.48207 2.48207 0.01 9.0311e-05 8.1778e-05 0.00107183 0.00102445 -1 -1 -1 -1 38 138 12 151211 75605.7 48493.3 1939.73 0.06 0.0196681 0.0164901 2100 8065 -1 119 12 82 91 2625 1383 2.45975 2.45975 -29.6014 -2.45975 0 0 61632.8 2465.31 0.00 0.01 0.01 -1 -1 0.00 0.00502351 0.0045985 13 18 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 4.95 vpr 65.34 MiB -1 -1 0.09 18368 1 0.03 -1 -1 30244 -1 -1 9 19 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66908 19 18 308 249 1 135 46 6 6 36 clb auto 25.7 MiB 3.72 587 468 1358 299 1048 11 65.3 MiB 0.02 0.00 4.87574 4.8546 -99.0856 -4.8546 4.8546 0.02 0.000303711 0.000279559 0.0077034 0.00724435 -1 -1 -1 -1 40 1040 31 403230 226817 88484.8 2457.91 0.38 0.12651 0.109515 3734 16003 -1 750 18 631 1001 35065 15346 5.69994 5.69994 -115.447 -5.69994 0 0 110337. 3064.92 0.00 0.02 0.01 -1 -1 0.00 0.0166944 0.0153494 54 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt index e2bde77991..817c60035f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.40 vpr 59.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61208 1 4 28 32 2 10 9 4 4 16 clb auto 21.3 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.9684e-05 6.8866e-05 0.000576703 0.000522527 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00940561 0.00796331 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.01 0.00 -1 -1 0.00 0.00917782 0.00398665 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.34 vpr 59.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61228 1 4 28 32 2 10 9 4 4 16 clb auto 21.3 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.4384e-05 5.704e-05 0.000402489 0.000366894 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.0100179 0.00835542 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00286153 0.00265955 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.31 vpr 59.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61188 1 4 28 32 2 10 9 4 4 16 clb auto 21.1 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 6.4879e-05 5.7282e-05 0.000404422 0.000368079 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00971796 0.00808787 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00303232 0.00280678 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.32 vpr 57.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59156 1 4 28 32 2 10 9 4 4 16 clb auto 18.8 MiB 0.00 22 21 27 10 10 7 57.8 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 4.0741e-05 3.552e-05 0.000370665 0.000341625 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00517377 0.00438326 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00187468 0.00172425 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.30 vpr 57.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59300 1 4 28 32 2 10 9 4 4 16 clb auto 18.8 MiB 0.00 22 21 27 10 10 7 57.9 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 4.0187e-05 3.4848e-05 0.000357031 0.000328785 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00519969 0.00440737 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00177188 0.00164255 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.31 vpr 58.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59476 1 4 28 32 2 10 9 4 4 16 clb auto 19.1 MiB 0.00 22 21 27 10 10 7 58.1 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.1244e-05 3.5883e-05 0.000359972 0.000330606 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00495679 0.00417745 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00172922 0.00160172 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt index 9d76eedbd0..189aa4e29d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.31 vpr 59.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61216 2 2 22 24 2 4 6 4 4 16 clb auto 21.3 MiB 0.00 8 15 5 7 3 59.8 MiB 0.00 0.00 1.297 0 0 1.297 0.01 5.264e-05 4.5649e-05 0.000308634 0.000273818 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.002301 0.00212354 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00265986 0.00219441 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.30 vpr 58.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59408 2 2 22 24 2 4 6 4 4 16 clb auto 19.1 MiB 0.00 8 8 15 5 7 3 58.0 MiB 0.00 0.00 1.297 1.297 0 0 1.297 0.00 3.4591e-05 2.9141e-05 0.000263335 0.000234214 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.00 0.00164969 0.00150335 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.0015794 0.00146098 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt index 55f3e1dd3b..b7e6584d84 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt index 948d09b747..7dee7b0e1e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.26 vpr 59.66 MiB -1 -1 0.07 21096 1 0.02 -1 -1 33168 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61096 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 6 9 6 3 0 59.7 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.5934e-05 1.0639e-05 9.4808e-05 6.8481e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00119359 0.00110751 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.27 vpr 59.66 MiB -1 -1 0.08 20840 1 0.02 -1 -1 33340 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61096 2 1 3 4 1 3 4 3 3 9 -1 auto 21.2 MiB 0.00 9 9 5 2 2 59.7 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.6744e-05 1.0373e-05 9.4261e-05 6.634e-05 -1 -1 -1 -1 -1 4 1 18000 18000 15707.9 1745.32 0.00 0.00132946 0.0012632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 31.57 parmys 210.75 MiB -1 -1 25.18 215804 2 1.59 -1 -1 60048 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63168 5 156 191 347 1 163 316 15 15 225 clb auto 22.1 MiB 0.04 31 86316 62145 3320 20851 61.7 MiB 0.22 0.02 1.49664 -15.0848 -1.49664 1.49664 0.00 0.000537912 0.000491594 0.0397632 0.036381 -1 -1 -1 -1 -1 50 5 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0494991 0.045404 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 25.71 parmys 210.82 MiB -1 -1 22.20 215880 2 0.99 -1 -1 60300 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62916 5 156 191 347 1 163 316 15 15 225 clb auto 21.9 MiB 0.02 33 86316 61936 3548 20832 61.4 MiB 0.10 0.00 1.51877 -14.6769 -1.51877 1.51877 0.00 0.000236107 0.000213852 0.0263786 0.0239723 -1 -1 -1 -1 -1 59 7 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0328145 0.0299576 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.41 vpr 65.16 MiB -1 -1 0.11 20748 1 0.02 -1 -1 33304 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 6 9 6 2 1 65.2 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.6453e-05 1.1342e-05 0.000108728 7.9328e-05 -1 -1 -1 -1 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.0015946 0.00150943 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.41 vpr 65.16 MiB -1 -1 0.11 21132 1 0.02 -1 -1 33192 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 9 9 5 2 2 65.2 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.8934e-05 1.2137e-05 0.000113982 8.1444e-05 -1 -1 -1 -1 -1 8 1 53894 53894 14028.3 1558.70 0.00 0.00161693 0.00153615 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 5.07 vpr 72.77 MiB -1 -1 1.12 29456 2 0.10 -1 -1 37868 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74516 311 156 972 1128 1 953 525 28 28 784 memory auto 32.5 MiB 0.54 8655 197406 67882 119014 10510 72.8 MiB 1.23 0.02 3.83315 -4315.62 -3.83315 3.83315 0.00 0.0052551 0.00459042 0.542684 0.463052 -1 -1 -1 -1 -1 12421 13 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.41 0.761716 0.663478 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 5.34 vpr 72.84 MiB -1 -1 1.44 29580 2 0.14 -1 -1 38000 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74592 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.55 8675 193172 64013 116396 12763 72.8 MiB 0.82 0.01 3.94715 -3504.6 -3.94715 3.94715 0.00 0.00308193 0.00262987 0.364549 0.310746 -1 -1 -1 -1 -1 12709 18 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.33 0.5457 0.474589 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.32 vpr 57.64 MiB -1 -1 0.05 17508 1 0.02 -1 -1 30432 -1 -1 1 2 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59028 2 1 3 4 1 3 4 3 3 9 -1 auto 19.1 MiB 0.00 6 6 9 6 3 0 57.6 MiB 0.00 0.00 0.631526 0.55447 -0.91031 -0.55447 0.55447 0.00 1.487e-05 1.0877e-05 0.000100565 7.7819e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00106927 0.000996487 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.33 vpr 57.87 MiB -1 -1 0.05 17120 1 0.02 -1 -1 29984 -1 -1 1 2 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59260 2 1 3 4 1 3 4 3 3 9 -1 auto 19.1 MiB 0.00 9 9 9 5 2 2 57.9 MiB 0.00 0.00 0.50194 0.48631 -0.91031 -0.48631 0.48631 0.00 1.0735e-05 6.272e-06 7.637e-05 5.4972e-05 -1 -1 -1 -1 -1 4 1 18000 18000 15707.9 1745.32 0.00 0.00101448 0.000953971 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 18.30 parmys 207.93 MiB -1 -1 15.05 212920 2 0.89 -1 -1 56028 -1 -1 155 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60684 5 156 191 347 1 163 316 15 15 225 clb auto 20.0 MiB 0.02 93 31 86316 62044 3278 20994 59.3 MiB 0.07 0.00 1.75726 1.49664 -15.0848 -1.49664 1.49664 0.00 0.000214904 0.000201619 0.0186732 0.0175157 -1 -1 -1 -1 -1 46 7 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0239391 0.0223789 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 18.08 parmys 207.56 MiB -1 -1 14.99 212540 2 0.89 -1 -1 56404 -1 -1 155 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61304 5 156 191 347 1 163 316 15 15 225 clb auto 20.2 MiB 0.02 102 33 86316 61971 3553 20792 59.9 MiB 0.07 0.00 1.51873 1.47673 -14.6018 -1.47673 1.47673 0.00 0.000222719 0.000209166 0.0188844 0.0176832 -1 -1 -1 -1 -1 49 5 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0235668 0.0220374 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.36 vpr 62.75 MiB -1 -1 0.07 17268 1 0.02 -1 -1 29968 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64260 2 1 3 4 1 3 4 3 3 9 -1 auto 24.5 MiB 0.00 6 6 9 6 2 1 62.8 MiB 0.00 0.00 0.629525 0.55247 -0.90831 -0.55247 0.55247 0.00 9.686e-06 6.129e-06 7.5115e-05 5.4701e-05 -1 -1 -1 -1 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.000944497 0.000880055 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.37 vpr 63.49 MiB -1 -1 0.07 17268 1 0.02 -1 -1 29988 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65016 2 1 3 4 1 3 4 3 3 9 -1 auto 25.2 MiB 0.00 9 9 9 5 2 2 63.5 MiB 0.00 0.00 0.49994 0.48631 -0.90831 -0.48631 0.48631 0.00 1.0794e-05 6.366e-06 7.9944e-05 5.6278e-05 -1 -1 -1 -1 -1 8 1 53894 53894 14028.3 1558.70 0.00 0.000935848 0.000872317 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 2.86 vpr 71.51 MiB -1 -1 0.74 25732 2 0.09 -1 -1 33696 -1 -1 43 311 15 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73224 311 156 972 1128 1 953 525 28 28 784 memory auto 32.0 MiB 0.27 18876 8963 212225 78866 122905 10454 71.5 MiB 0.60 0.01 4.92557 4.25856 -4308.38 -4.25856 4.25856 0.00 0.00246158 0.00217726 0.266516 0.235597 -1 -1 -1 -1 -1 12922 12 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.19 0.358434 0.320375 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 2.89 vpr 71.05 MiB -1 -1 0.75 25976 2 0.09 -1 -1 33696 -1 -1 43 311 15 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72752 311 156 972 1128 1 953 525 28 28 784 memory auto 31.5 MiB 0.27 19048 9147 216459 76243 126716 13500 71.0 MiB 0.58 0.01 5.19493 4.54954 -3411.74 -4.54954 4.54954 0.00 0.00243523 0.00216432 0.266541 0.235263 -1 -1 -1 -1 -1 13132 15 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.19 0.368168 0.328809 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt index 9cebacaf78..6a499b50fd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.85 vpr 66.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67612 8 4 25 28 5 19 19 6 6 36 clb auto 27.5 MiB 0.60 51 194 39 119 36 66.0 MiB 0.01 0.00 1.41795 -5.85435 -1.41795 0.545 0.00 8.3509e-05 6.4713e-05 0.00086545 0.000699438 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 675 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.01 -1 -1 66.0 MiB 0.00 0.00307466 0.00275514 66.0 MiB -1 0.00 - k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 vpr 20.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 21296 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.34 vpr 64.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65820 8 4 25 28 5 19 19 6 6 36 clb auto 25.6 MiB 0.18 73 51 194 39 119 36 64.3 MiB 0.00 0.00 1.51369 1.41795 -5.85435 -1.41795 0.545 0.00 3.4225e-05 2.6328e-05 0.000449957 0.000366026 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 673 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.00 -1 -1 64.3 MiB 0.00 0.0017393 0.0015598 64.3 MiB -1 0.00 +k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.04 vpr 18.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 18956 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt index c751724ac2..6a0a3fac0b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.30 vpr 65.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66556 -1 2 2 4 0 2 4 4 4 16 clb auto 26.8 MiB 0.00 0 9 0 2 7 65.0 MiB 0.00 0.00 nan 0 0 nan 0.01 9.099e-06 4.802e-06 6.6245e-05 4.4664e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.00112148 0.00105568 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00152182 0.00148612 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.32 vpr 63.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65016 -1 2 2 4 0 2 4 4 4 16 clb auto 25.2 MiB 0.00 0 0 9 0 2 7 63.5 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.956e-06 4.158e-06 6.0036e-05 4.0485e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.000880341 0.000826711 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.000881555 0.000851341 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt index 19c7fb784a..311432e9c1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_grid.xml raygentop.v common 36.32 vpr 86.72 MiB -1 -1 4.05 45484 3 0.90 -1 -1 40972 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88800 236 305 3199 3011 1 1520 677 25 25 625 -1 25x25 45.9 MiB 3.77 14108 309661 104995 184095 20571 86.7 MiB 2.82 0.04 4.79923 -2884.9 -4.79923 4.79923 1.31 0.00890658 0.00798503 1.05545 0.927146 -1 -1 -1 -1 58 25094 44 3.19446e+07 9.87633e+06 2.35761e+06 3772.18 18.23 4.76599 4.25993 69363 480205 -1 22477 18 6375 16887 1571491 383129 5.01505 5.01505 -3124.26 -5.01505 0 0 3.00727e+06 4811.63 0.12 0.58 0.43 -1 -1 0.12 0.287158 0.267873 - column_io.xml raygentop.v common 21.72 vpr 86.87 MiB -1 -1 3.94 45412 3 0.59 -1 -1 40804 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88956 236 305 3199 3011 1 1520 677 25 25 625 io auto 46.1 MiB 2.22 12585 268067 93998 147700 26369 86.9 MiB 1.58 0.02 4.73901 -2866.75 -4.73901 4.73901 0.71 0.00580557 0.00496502 0.564483 0.497852 -1 -1 -1 -1 54 26673 50 2.82259e+07 9.87633e+06 2.01770e+06 3228.33 9.11 2.60416 2.32669 60384 399159 -1 22031 17 6221 15823 1566992 390050 4.92063 4.92063 -3214.76 -4.92063 0 0 2.61977e+06 4191.64 0.11 0.57 0.36 -1 -1 0.11 0.283045 0.264698 - multiwidth_blocks.xml raygentop.v common 24.35 vpr 86.45 MiB -1 -1 4.29 45400 3 0.88 -1 -1 40680 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88524 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.5 MiB 3.44 13659 253212 84696 147080 21436 86.4 MiB 2.39 0.03 4.97053 -2888.67 -4.97053 4.97053 0.57 0.0095941 0.00864195 0.904905 0.798443 -1 -1 -1 -1 70 23087 25 1.65001e+07 9.87633e+06 1.31889e+06 3653.42 9.29 3.5266 3.16984 37321 246261 -1 21189 14 5796 14717 1380152 383870 5.13329 5.13329 -3164.24 -5.13329 0 0 1.66774e+06 4619.77 0.06 0.50 0.26 -1 -1 0.06 0.248992 0.232939 - non_column.xml raygentop.v common 55.37 vpr 101.45 MiB -1 -1 4.51 45384 3 0.78 -1 -1 40740 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103880 236 305 3188 3000 1 1523 673 33 33 1089 io auto 46.9 MiB 3.81 15255 254201 81770 140693 31738 97.7 MiB 2.36 0.03 4.86131 -2900.08 -4.86131 4.86131 2.27 0.00977579 0.00884174 0.917497 0.805822 -1 -1 -1 -1 48 30162 49 5.44432e+07 9.66075e+06 2.98548e+06 2741.49 34.00 4.50443 4.0188 95950 575791 -1 25045 20 6804 18118 1664218 433730 5.45028 5.45028 -3158.16 -5.45028 0 0 3.81303e+06 3501.40 0.21 0.95 0.95 -1 -1 0.21 0.482241 0.44347 - non_column_tall_aspect_ratio.xml raygentop.v common 44.05 vpr 108.02 MiB -1 -1 4.73 45644 3 0.86 -1 -1 40856 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 110616 236 305 3188 3000 1 1523 673 23 46 1058 io auto 47.3 MiB 3.74 14790 242409 83942 122709 35758 98.8 MiB 2.21 0.03 4.6713 -2947.44 -4.6713 4.6713 2.10 0.00881355 0.00803567 0.866396 0.762137 -1 -1 -1 -1 54 27998 49 5.05849e+07 9.66075e+06 3.28516e+06 3105.07 22.44 5.06657 4.53255 98319 656086 -1 23970 19 6505 16966 1638977 432992 5.05886 5.05886 -3281.32 -5.05886 0 0 4.26512e+06 4031.31 0.30 0.98 1.19 -1 -1 0.30 0.480325 0.442198 - non_column_wide_aspect_ratio.xml raygentop.v common 55.14 vpr 115.98 MiB -1 -1 4.85 45536 3 0.89 -1 -1 40604 -1 -1 125 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 118764 236 305 3188 3000 1 1523 673 53 27 1431 io auto 47.2 MiB 4.13 15438 292525 96949 170972 24604 116.0 MiB 2.79 0.04 4.87363 -3002.95 -4.87363 4.87363 2.83 0.00999099 0.00902684 1.12807 0.98489 -1 -1 -1 -1 46 32183 50 7.18852e+07 9.66075e+06 3.81039e+06 2662.74 30.50 4.16688 3.69158 125381 744275 -1 26057 24 7716 19635 2034521 534369 5.1816 5.1816 -3336.75 -5.1816 0 0 4.88937e+06 3416.75 0.38 1.34 1.15 -1 -1 0.38 0.614347 0.564321 - custom_sbloc.xml raygentop.v common 26.06 vpr 86.32 MiB -1 -1 4.50 45448 3 1.04 -1 -1 40804 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88392 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.3 MiB 4.20 13741 271038 86813 158916 25309 86.3 MiB 2.67 0.04 4.66207 -2945.67 -4.66207 4.66207 0.62 0.0101306 0.00867476 0.964821 0.865378 -1 -1 -1 -1 68 24218 46 1.65001e+07 9.87633e+06 1.26689e+06 3509.39 7.14 3.30943 2.96886 36601 241349 -1 21082 17 5846 15055 1419293 377571 4.86127 4.86127 -3204.17 -4.86127 0 0 1.57833e+06 4372.12 0.09 0.93 0.49 -1 -1 0.09 0.46499 0.431595 - multiple_io_types.xml raygentop.v common 162.68 vpr 512.77 MiB -1 -1 4.59 44868 3 0.91 -1 -1 40632 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 525072 236 305 3199 3011 1 1520 677 70 70 4900 io_left auto 46.0 MiB 4.88 29540 98720 5114 25125 68481 512.8 MiB 0.75 0.03 4.77694 -3775.91 -4.77694 4.77694 29.11 0.00955143 0.00822118 0.265489 0.23233 -1 -1 -1 -1 46 47171 45 2.76175e+08 9.87633e+06 1.25363e+07 2558.43 103.39 4.74809 4.24216 425698 2387761 -1 40627 18 8645 22202 3622069 899914 5.14884 5.14884 -4109.51 -5.14884 0 0 1.61910e+07 3304.29 1.21 1.53 3.08 -1 -1 1.21 0.445697 0.411568 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_grid.xml raygentop.v common 17.79 vpr 85.09 MiB -1 -1 2.14 42456 3 0.53 -1 -1 36860 -1 -1 127 236 1 6 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87128 236 305 3199 3011 1 1523 675 25 25 625 -1 25x25 45.9 MiB 1.90 30826 14481 296575 101967 175892 18716 85.1 MiB 1.15 0.01 7.09553 4.79307 -2895.89 -4.79307 4.79307 0.49 0.00365179 0.0033636 0.416808 0.376019 -1 -1 -1 -1 56 27441 32 3.19446e+07 9.76854e+06 2.27235e+06 3635.76 8.75 1.40736 1.27772 68115 457904 -1 23429 18 6422 16721 1633043 414220 4.92066 4.92066 -3228.39 -4.92066 0 0 2.89946e+06 4639.14 0.08 0.43 0.25 -1 -1 0.08 0.223472 0.210718 +column_io.xml raygentop.v common 13.37 vpr 84.46 MiB -1 -1 2.14 42840 3 0.53 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86484 236 305 3199 3011 1 1523 675 25 25 625 io auto 45.5 MiB 1.91 28947 12805 264026 93507 163068 7451 84.5 MiB 1.08 0.02 6.19083 4.92182 -2798.47 -4.92182 4.92182 0.45 0.00393872 0.00362651 0.385023 0.350411 -1 -1 -1 -1 54 25735 23 2.82259e+07 9.76854e+06 2.01770e+06 3228.33 4.48 1.33409 1.21791 60384 399159 -1 22144 15 5803 15289 1517391 375232 5.17726 5.17726 -3105.16 -5.17726 0 0 2.61977e+06 4191.64 0.07 0.38 0.24 -1 -1 0.07 0.201471 0.190828 +multiwidth_blocks.xml raygentop.v common 11.61 vpr 84.85 MiB -1 -1 2.15 42644 3 0.54 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86888 236 305 3199 3011 1 1523 675 19 19 361 io clb auto 45.9 MiB 1.92 27296 13664 243313 79797 144041 19475 84.9 MiB 1.05 0.02 7.04872 4.69621 -2916.6 -4.69621 4.69621 0.22 0.00449624 0.00401214 0.401073 0.36631 -1 -1 -1 -1 70 24143 30 1.65001e+07 9.76854e+06 1.31889e+06 3653.42 3.31 1.50248 1.37681 37321 246261 -1 21464 15 6203 15799 1529026 424169 4.71101 4.71101 -3112.78 -4.71101 0 0 1.66774e+06 4619.77 0.04 0.38 0.16 -1 -1 0.04 0.204177 0.193211 +non_column.xml raygentop.v common 15.65 vpr 101.04 MiB -1 -1 2.36 41940 3 0.51 -1 -1 38416 -1 -1 126 236 1 6 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 103468 236 305 3188 3000 1 1520 674 33 33 1089 io auto 47.1 MiB 2.03 36533 15061 269488 91860 157197 20431 98.0 MiB 1.04 0.01 7.4161 4.90918 -2943.89 -4.90918 4.90918 0.85 0.00376346 0.00345776 0.383465 0.34753 -1 -1 -1 -1 54 27586 33 5.44432e+07 9.71464e+06 3.30487e+06 3034.77 5.05 1.37792 1.25366 100302 649205 -1 23881 20 6491 17318 1529311 414224 6.12281 6.12281 -3223.84 -6.12281 0 0 4.28921e+06 3938.67 0.13 0.43 0.46 -1 -1 0.13 0.229549 0.215027 +non_column_tall_aspect_ratio.xml raygentop.v common 16.60 vpr 97.97 MiB -1 -1 2.34 41884 3 0.55 -1 -1 38032 -1 -1 126 236 1 6 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 100324 236 305 3188 3000 1 1520 674 23 46 1058 io auto 47.4 MiB 2.03 38199 14733 245856 82760 136190 26906 96.5 MiB 0.94 0.01 8.90911 4.95032 -2931.23 -4.95032 4.95032 0.81 0.00371055 0.00340195 0.346059 0.31414 -1 -1 -1 -1 52 28730 41 5.05849e+07 9.71464e+06 3.17293e+06 2998.99 6.26 1.38308 1.25917 97261 632982 -1 24184 19 6976 18077 1589447 411584 5.61027 5.61027 -3209.89 -5.61027 0 0 4.15960e+06 3931.57 0.13 0.42 0.43 -1 -1 0.13 0.220476 0.206505 +non_column_wide_aspect_ratio.xml raygentop.v common 16.28 vpr 114.39 MiB -1 -1 2.35 42456 3 0.50 -1 -1 38416 -1 -1 126 236 1 6 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 117136 236 305 3188 3000 1 1520 674 53 27 1431 io auto 47.0 MiB 2.04 41800 15715 293120 96558 176401 20161 114.4 MiB 1.11 0.02 8.75852 4.83208 -2966.14 -4.83208 4.83208 1.10 0.00389154 0.00356387 0.423507 0.383324 -1 -1 -1 -1 50 29305 30 7.18852e+07 9.71464e+06 4.09444e+06 2861.24 5.07 1.42289 1.29694 128243 787897 -1 25411 18 6656 17052 1503266 383226 5.17928 5.17928 -3293.35 -5.17928 0 0 5.23266e+06 3656.65 0.17 0.42 0.52 -1 -1 0.17 0.215733 0.203239 +custom_sbloc.xml raygentop.v common 11.30 vpr 84.98 MiB -1 -1 2.09 41816 3 0.53 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87016 236 305 3199 3011 1 1523 675 19 19 361 io clb auto 45.9 MiB 1.91 27296 13137 255149 87552 148387 19210 85.0 MiB 1.04 0.02 7.00084 4.99197 -2892.82 -4.99197 4.99197 0.22 0.00409426 0.00376216 0.392163 0.357469 -1 -1 -1 -1 68 22261 27 1.65001e+07 9.76854e+06 1.26689e+06 3509.39 3.16 1.43007 1.31051 36601 241349 -1 20367 15 5668 14466 1281380 334598 4.957 4.957 -3115.31 -4.957 0 0 1.57833e+06 4372.12 0.04 0.34 0.16 -1 -1 0.04 0.203089 0.19197 +multiple_io_types.xml raygentop.v common 41.55 vpr 510.68 MiB -1 -1 2.24 42452 3 0.53 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 522936 236 305 3199 3011 1 1523 675 70 70 4900 io_left auto 45.6 MiB 2.42 68337 27793 95363 4323 24983 66057 510.7 MiB 0.47 0.01 10.4866 5.00659 -3523.06 -5.00659 5.00659 12.98 0.00404977 0.0037296 0.172258 0.158132 -1 -1 -1 -1 52 42943 37 2.76175e+08 9.76854e+06 1.39708e+07 2851.19 13.77 1.40622 1.28897 445294 2682153 -1 37901 18 8291 21706 3271061 840277 5.11058 5.11058 -3856.44 -5.11058 0 0 1.83718e+07 3749.35 0.61 0.73 1.80 -1 -1 0.61 0.232067 0.21795 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt index 9ad80c43a9..9286f2ca3d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 3.10 vpr 67.93 MiB -1 -1 0.36 22040 3 0.12 -1 -1 36928 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69560 99 130 344 474 1 227 298 12 12 144 clb auto 28.6 MiB 0.23 673 63978 19550 30341 14087 67.9 MiB 0.25 0.01 1.86472 -118.834 -1.86472 1.86472 0.23 0.00124652 0.00114654 0.0791433 0.0725521 -1 -1 -1 -1 38 1384 9 5.66058e+06 4.21279e+06 328943. 2284.32 0.66 0.24355 0.222932 12522 66188 -1 1114 9 395 636 21516 6871 1.90702 1.90702 -133.439 -1.90702 -1.20917 -0.320482 418267. 2904.63 0.04 0.05 0.10 -1 -1 0.04 0.0351893 0.0324309 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 1.65 vpr 66.56 MiB -1 -1 0.22 18448 3 0.06 -1 -1 33108 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68156 99 130 344 474 1 228 298 12 12 144 clb auto 26.7 MiB 0.10 1675 704 66963 20370 32791 13802 66.6 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.10 0.000544054 0.000509023 0.0401106 0.0375452 -1 -1 -1 -1 40 1447 14 5.66058e+06 4.21279e+06 343462. 2385.15 0.33 0.155796 0.142975 12666 68385 -1 1229 9 430 657 29320 9898 2.03042 2.03042 -138.775 -2.03042 -0.436676 -0.298787 431791. 2998.55 0.01 0.02 0.04 -1 -1 0.01 0.0160312 0.0150481 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt index 88d0cc3626..b2665a3b14 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_sb_loc/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 65.74 vpr 1.17 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1222776 13 29 26295 20086 1 12439 800 40 32 1280 -1 EP4SGX110 1063.6 MiB 14.29 72376 238368 44187 187356 6825 1172.1 MiB 12.27 0.21 5.14869 -5574.19 -4.14869 2.7734 0.01 0.0513395 0.0444487 3.37672 2.67885 83490 6.71303 20017 1.60947 25863 35776 9229792 1644713 0 0 2.34683e+07 18334.6 15 375646 4004209 -1 5.37962 2.85331 -5732.11 -4.37962 0 0 7.55 -1 -1 1172.1 MiB 6.09 5.72718 4.67253 1172.1 MiB -1 3.79 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 34.80 vpr 1.17 GiB 42 749 0 0 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1222084 13 29 26295 20086 1 12646 791 40 32 1280 -1 EP4SGX110 1077.1 MiB 7.73 239076 73734 242087 47102 187997 6988 1170.4 MiB 6.12 0.08 5.63444 5.39011 -5538.73 -4.39011 2.81304 0.01 0.0205072 0.017934 1.73703 1.42727 84889 6.71378 20487 1.62029 25867 34992 8975854 1601365 0 0 2.34683e+07 18334.6 16 375646 4004209 -1 5.63353 2.99154 -5719.81 -4.63353 0 0 3.92 -1 -1 1170.4 MiB 2.69 2.87777 2.4428 1170.4 MiB -1 1.20 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt index f8dbe6d76d..59b815b831 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.26 vpr 64.63 MiB -1 -1 0.36 22472 3 0.08 -1 -1 36672 -1 -1 72 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66184 99 130 353 483 1 273 302 15 15 225 memory auto 25.1 MiB 0.03 836 70130 21082 33527 15521 64.6 MiB 0.28 0.00 1.52582 -78.5706 -1.52582 1.52582 0.00 0.00103975 0.000940046 0.0805857 0.0730912 -1 -1 -1 -1 1163 5.43458 640 2.99065 663 1535 177334 49638 1.16234e+06 363548 2.18283e+06 9701.45 10 48952 428016 -1 1.65868 1.65868 -90.7494 -1.65868 -2.16982 -0.309514 0.64 -1 -1 64.6 MiB 0.08 0.105372 0.095866 64.6 MiB -1 0.38 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 1.25 vpr 62.95 MiB -1 -1 0.21 18752 3 0.06 -1 -1 33072 -1 -1 72 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64456 99 130 353 483 1 273 302 15 15 225 memory auto 23.2 MiB 0.02 2130 858 65070 19636 30261 15173 62.9 MiB 0.12 0.00 1.71828 1.52582 -77.3355 -1.52582 1.52582 0.00 0.000546677 0.000512061 0.0383668 0.0358856 -1 -1 -1 -1 1238 5.78505 678 3.16822 700 1565 188506 51086 1.16234e+06 363548 2.18283e+06 9701.45 11 48952 428016 -1 1.60126 1.60126 -87.5381 -1.60126 -2.22487 -0.375057 0.28 -1 -1 62.9 MiB 0.04 0.054652 0.0509441 62.9 MiB -1 0.13 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt index 01809a06f1..d67d1edba5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 22.14 vpr 81.82 MiB -1 -1 1.50 29500 2 0.12 -1 -1 37736 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83780 311 156 1015 1158 1 965 514 28 28 784 memory auto 35.0 MiB 0.98 9365 202198 74776 117229 10193 76.8 MiB 1.40 0.02 4.8046 -3913.87 -4.8046 4.8046 1.69 0.00610306 0.00535177 0.650008 0.562031 -1 -1 -1 -1 46 14326 15 4.25198e+07 9.94461e+06 2.42825e+06 3097.26 10.53 2.95135 2.62498 81963 495902 -1 13813 11 2359 2703 832718 314081 4.94363 4.94363 -4384.42 -4.94363 -367.864 -1.26276 3.12000e+06 3979.60 0.25 1.49 0.70 -1 -1 0.25 0.183604 0.168791 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 21.14 vpr 85.34 MiB -1 -1 1.46 29488 2 0.17 -1 -1 37984 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 87384 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.6 MiB 1.02 9365 202198 74776 117229 10193 77.2 MiB 1.49 0.03 4.8046 -3913.87 -4.8046 4.8046 1.72 0.00745529 0.00636204 0.709181 0.610899 -1 -1 -1 -1 46 14531 14 4.25198e+07 9.94461e+06 2.47848e+06 3161.33 10.27 3.22179 2.86209 81963 509322 -1 13895 10 2295 2641 564364 164225 5.2138 5.2138 -4583.26 -5.2138 -149.396 -1.20609 3.17357e+06 4047.92 0.16 0.89 0.46 -1 -1 0.16 0.127663 0.117099 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 25.61 vpr 78.92 MiB -1 -1 1.51 29244 2 0.15 -1 -1 37516 -1 -1 32 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80812 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.8 MiB 0.83 9442 200140 70475 118412 11253 78.1 MiB 1.44 0.02 4.10149 -3784.12 -4.10149 4.10149 1.51 0.00620655 0.00547017 0.672177 0.575194 -1 -1 -1 -1 40 16586 15 4.25198e+07 9.94461e+06 2.15085e+06 2743.43 14.64 1.95101 1.72006 78831 435812 -1 15579 11 2621 3012 1218850 719774 5.45816 5.45816 -4586.28 -5.45816 -1608.52 -3.17721 2.68809e+06 3428.68 0.23 1.76 0.54 -1 -1 0.23 0.216383 0.199419 15 950 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 8.08 vpr 74.94 MiB -1 -1 0.73 25744 2 0.09 -1 -1 34208 -1 -1 32 311 15 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76740 311 156 1015 1158 1 965 514 28 28 784 memory auto 33.3 MiB 0.50 19865 9549 204256 72417 120221 11618 73.8 MiB 0.59 0.01 5.60967 3.86883 -3854.15 -3.86883 3.86883 0.65 0.0025034 0.00222081 0.270168 0.238726 -1 -1 -1 -1 38 15620 13 4.25198e+07 9.94461e+06 2.06185e+06 2629.91 2.77 0.840096 0.752974 78047 421269 -1 14413 13 2666 3203 1457933 704363 4.53757 4.53757 -4350.73 -4.53757 -517.68 -1.45296 2.60823e+06 3326.82 0.09 0.73 0.23 -1 -1 0.09 0.103809 0.0965537 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 7.66 vpr 76.55 MiB -1 -1 0.74 25744 2 0.09 -1 -1 34464 -1 -1 32 311 15 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78388 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.3 MiB 0.47 19865 9549 204256 72417 120221 11618 75.4 MiB 0.60 0.01 5.60967 3.86883 -3854.15 -3.86883 3.86883 0.64 0.00269702 0.00241691 0.283834 0.252091 -1 -1 -1 -1 36 16026 28 4.25198e+07 9.94461e+06 2.00618e+06 2558.90 2.55 0.987702 0.892581 76483 403003 -1 14763 13 2964 3560 850058 256440 4.32275 4.32275 -4167.47 -4.32275 -202.025 -1.15486 2.47848e+06 3161.33 0.08 0.52 0.21 -1 -1 0.08 0.101865 0.0948384 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 9.57 vpr 76.66 MiB -1 -1 0.74 26124 2 0.09 -1 -1 34472 -1 -1 32 311 15 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78496 311 156 1015 1158 1 965 514 28 28 784 memory auto 34.3 MiB 0.47 19865 9322 210430 75479 122755 12196 76.7 MiB 0.61 0.01 5.60967 3.96043 -3633.05 -3.96043 3.96043 0.62 0.00266556 0.00227834 0.277828 0.245371 -1 -1 -1 -1 36 16853 27 4.25198e+07 9.94461e+06 1.96702e+06 2508.96 4.31 0.904437 0.809862 76483 392433 -1 15496 13 2658 3060 1573658 1035121 5.75178 5.75178 -4622.22 -5.75178 -1616.18 -3.24966 2.42368e+06 3091.42 0.08 0.79 0.20 -1 -1 0.08 0.0999127 0.093 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt index 6c7432d3e1..e184cb8001 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 16.52 vpr 71.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73256 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.4 MiB 0.33 10472 141533 36950 100839 3744 71.5 MiB 1.36 0.02 7.46482 -1369.01 -7.46482 7.46482 0.53 0.00499636 0.00433729 0.369387 0.30729 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 10.94 2.01193 1.71604 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.85 0.23 -1 -1 0.04 0.262211 0.23364 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 5.02 vpr 70.13 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71812 64 39 1935 1974 1 1075 542 23 23 529 clb auto 30.8 MiB 0.17 24088 10407 135291 36283 95683 3325 70.1 MiB 0.56 0.01 23.0912 7.70338 -1562.28 -7.70338 7.70338 0.21 0.00212327 0.00180505 0.140403 0.121205 -1 -1 -1 -1 24 13067 26 983127 978669 797780. 1508.09 2.53 0.431893 0.375189 39018 137339 -1 11571 16 6466 23559 1530116 397333 7.70338 7.70338 -1636.85 -7.70338 0 0 1.04508e+06 1975.57 0.02 0.32 0.08 -1 -1 0.02 0.0914491 0.0827973 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt index 15d40a35dd..9b26913fb5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 34.16 vpr 84.50 MiB -1 -1 7.12 54432 5 2.11 -1 -1 42788 -1 -1 153 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 86528 193 205 2718 2652 1 1312 556 20 20 400 memory auto 43.4 MiB 1.85 10543 233626 82676 126206 24744 84.5 MiB 2.72 0.04 4.85425 -2733.64 -4.85425 4.85425 0.66 0.00818288 0.00722228 1.06716 0.90034 -1 -1 -1 -1 76 20844 33 2.07112e+07 1.09858e+07 2.02110e+06 5052.76 15.57 4.03457 3.54046 52074 423490 -1 18742 16 4982 13549 1088379 246430 5.27071 5.27071 -2903.22 -5.27071 -6.49744 -0.292146 2.51807e+06 6295.18 0.11 0.47 0.38 -1 -1 0.11 0.260053 0.24125 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 14.82 vpr 83.52 MiB -1 -1 3.44 51988 5 1.38 -1 -1 39324 -1 -1 152 193 5 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85524 193 205 2718 2652 1 1315 555 20 20 400 memory auto 43.3 MiB 1.00 22187 10660 223995 81694 118286 24015 83.5 MiB 1.03 0.01 7.82756 5.10197 -2914.56 -5.10197 5.10197 0.32 0.00334273 0.00299401 0.368182 0.329453 -1 -1 -1 -1 76 21455 22 2.07112e+07 1.09319e+07 2.02110e+06 5052.76 5.00 1.1701 1.04968 52074 423490 -1 19292 16 5251 14325 1187541 264668 5.21056 5.21056 -3121.27 -5.21056 -9.98113 -0.359474 2.51807e+06 6295.18 0.07 0.32 0.25 -1 -1 0.07 0.187805 0.176004 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt index d0e64cbc17..161e9bc507 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.94 vpr 67.99 MiB -1 -1 0.39 22036 3 0.12 -1 -1 36636 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69620 99 130 344 474 1 227 298 12 12 144 clb auto 28.6 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.21 0.00 1.86472 -118.834 -1.86472 1.86472 0.24 0.000996678 0.000900839 0.0648293 0.0586504 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.58 0.202532 0.183764 12522 62564 -1 1116 11 409 682 22304 6997 1.90702 1.90702 -133.281 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.06 0.09 -1 -1 0.02 0.0346978 0.0324594 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.71 vpr 66.55 MiB -1 -1 0.21 18828 3 0.06 -1 -1 33112 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68148 99 130 344 474 1 228 298 12 12 144 clb auto 27.1 MiB 0.10 1675 704 66963 20370 32791 13802 66.6 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000555368 0.000520652 0.0409597 0.0384123 -1 -1 -1 -1 40 1453 15 5.66058e+06 4.21279e+06 333335. 2314.82 0.32 0.156865 0.144076 12666 64609 -1 1222 11 442 668 30453 10334 2.02932 2.02932 -138.236 -2.02932 -0.424985 -0.298787 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0219703 0.0206786 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt index 2abafbec4a..c8291e655b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_40nm.xml stereovision0.v common 151.16 vpr 252.22 MiB -1 -1 13.65 124444 5 69.06 -1 -1 68628 -1 -1 1352 169 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 258272 169 197 21117 21314 1 6442 1718 39 39 1521 clb auto 120.8 MiB 5.85 49865 999363 355164 624898 19301 252.2 MiB 12.58 0.10 3.94387 -15329.6 -3.94387 3.94387 5.65 0.0282487 0.0224608 3.71486 2.98245 -1 -1 -1 -1 38 62474 28 2.4642e+07 2.4336e+07 4.29790e+06 2825.71 27.54 18.235 14.9379 119030 883757 -1 58887 28 30785 67364 2647531 463217 3.72242 3.72242 -16216.3 -3.72242 0 0 5.41627e+06 3561.00 0.27 2.70 0.65 -1 -1 0.27 1.99577 1.72788 - k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 145.25 vpr 237.36 MiB -1 -1 13.92 124256 5 67.78 -1 -1 68500 -1 -1 1342 169 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 243060 169 197 21117 21314 1 6530 1708 39 39 1521 clb auto 120.5 MiB 3.79 49914 971183 338147 610049 22987 237.4 MiB 14.52 0.10 3.63479 -14732.8 -3.63479 3.63479 5.35 0.02794 0.0220913 4.48744 3.66675 -1 -1 -1 -1 40 62766 41 7.37824e+07 7.23272e+07 4.31957e+06 2839.95 22.87 16.3688 13.4703 120550 875283 -1 59263 24 31348 67380 2546099 475966 3.57863 3.57863 -15572.9 -3.57863 0 0 5.40678e+06 3554.75 0.57 4.00 1.03 -1 -1 0.57 2.85785 2.46864 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_40nm.xml stereovision0.v common 73.95 vpr 246.61 MiB -1 -1 8.51 121540 5 30.03 -1 -1 65020 -1 -1 1352 169 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 252524 169 197 21117 21314 1 6509 1718 39 39 1521 clb auto 132.2 MiB 3.09 188600 47945 958223 329930 610922 17371 246.6 MiB 6.41 0.07 7.48908 3.85395 -15165.3 -3.85395 3.85395 3.37 0.0168369 0.0143938 1.85357 1.54221 -1 -1 -1 -1 36 61910 50 2.4642e+07 2.4336e+07 4.11737e+06 2707.01 12.99 6.85213 5.69049 115990 821377 -1 57410 21 30914 66833 2643745 477357 3.6821 3.6821 -15912.4 -3.6821 0 0 5.03985e+06 3313.51 0.18 1.65 0.40 -1 -1 0.18 1.15883 1.02171 +k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 73.45 vpr 248.34 MiB -1 -1 7.80 121452 5 29.25 -1 -1 65020 -1 -1 1363 169 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 254296 169 197 21117 21314 1 6565 1729 39 39 1521 clb auto 132.5 MiB 2.97 190099 51107 987164 353007 612737 21420 248.3 MiB 6.49 0.07 9.87654 3.59906 -14959.3 -3.59906 3.59906 3.32 0.0160576 0.0137899 1.86794 1.55614 -1 -1 -1 -1 38 67057 39 7.37824e+07 7.3459e+07 4.16760e+06 2740.04 13.65 6.42848 5.35178 119030 845795 -1 61286 30 33152 70295 2804113 519856 3.34587 3.34587 -15492.9 -3.34587 0 0 5.22668e+06 3436.35 0.18 2.03 0.45 -1 -1 0.18 1.43033 1.26218 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index 3a5d60de35..74a8cf9a4f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.36 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 3 1 5 6 1 4 5 3 3 9 -1 auto 22.0 MiB 0.00 9 12 4 4 4 60.5 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.3168e-05 1.5881e-05 0.000156154 0.000121512 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00179937 0.00168173 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00151021 0.00147037 - k6_frac_N10_40nm.xml conn_order.eblif common 0.33 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 2 1 4 5 1 3 4 3 3 9 -1 auto 22.1 MiB 0.00 6 9 4 1 4 60.5 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.6567e-05 1.1555e-05 0.000123665 9.5691e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00181279 0.00171778 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154282 0.00150229 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml test_eblif.eblif common 0.27 vpr 57.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59360 3 1 5 6 1 4 5 3 3 9 -1 auto 19.2 MiB 0.00 9 9 12 4 4 4 58.0 MiB 0.00 0.00 0.52647 0.52647 -0.88231 -0.52647 0.52647 0.00 1.1248e-05 7.778e-06 8.8386e-05 6.9957e-05 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.00 0.000991439 0.00092344 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000938997 0.000900722 +k6_frac_N10_40nm.xml conn_order.eblif common 0.29 vpr 58.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 2 1 4 5 1 3 4 3 3 9 -1 auto 19.9 MiB 0.00 6 6 9 4 1 4 58.7 MiB 0.00 0.00 0.69084 0.69084 -1.21731 -0.69084 0.69084 0.00 1.0554e-05 7.171e-06 8.2682e-05 6.4223e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00103314 0.000963782 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000913079 0.000880425 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt index 6afcd280a0..d36a682ae7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml eblif_write.eblif common 0.28 vpr 58.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60388 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 20.5 MiB 0.00 14 18 7 10 1 59.0 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 2.2578e-05 1.4571e-05 0.000133192 9.8031e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00167256 0.00156119 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00133191 0.00129055 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml eblif_write.eblif common 0.27 vpr 56.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58184 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.1 MiB 0.00 16 14 18 7 10 1 56.8 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3318e-05 8.286e-06 8.998e-05 6.7511e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00122033 0.00113744 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00090809 0.000873103 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt index 826beb46c2..47e6c74398 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.94 vpr 66.02 MiB -1 -1 0.82 27148 5 0.18 -1 -1 36836 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.09 152 432 67 335 30 66.0 MiB 0.04 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000434946 0.000380309 0.00759691 0.00679441 -1 -1 -1 -1 -1 145 18 646728 646728 60312.4 1675.34 0.03 0.0281069 0.0251327 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.19 vpr 63.95 MiB -1 -1 0.43 23432 5 0.11 -1 -1 32956 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65480 10 2 181 183 1 36 24 6 6 36 clb auto 24.6 MiB 0.04 196 151 534 120 387 27 63.9 MiB 0.04 0.00 2.24505 2.14835 -91.7778 -2.14835 2.14835 0.00 0.000225098 0.000205609 0.00485356 0.00448646 -1 -1 -1 -1 -1 141 16 646728 646728 60312.4 1675.34 0.01 0.0147522 0.0133084 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt index 106e5784d6..c32f95ef0f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - equivalent.xml equivalent.blif common 0.33 vpr 58.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60324 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 20.4 MiB 0.00 9 9 3 6 0 58.9 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 1.5162e-05 1.0275e-05 0.00029282 0.000262472 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00144752 0.00135246 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00148764 0.00144592 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +equivalent.xml equivalent.blif common 0.27 vpr 57.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58424 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 18.3 MiB 0.00 11 9 9 3 6 0 57.1 MiB 0.00 0.00 3.98683 3.8649 -3.8649 -3.8649 nan 0.00 8.813e-06 5.472e-06 6.2906e-05 4.3679e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00109903 0.0010306 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000878238 0.00084565 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt index f0909e951d..a65b4d3cce 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 2.12 vpr 65.83 MiB -1 -1 0.80 26828 5 0.17 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67408 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.03 152 432 67 335 30 65.8 MiB 0.01 0.00 2.15218 -93.3318 -2.15218 2.15218 0.04 0.000541794 0.000472344 0.00646942 0.00583397 -1 -1 -1 -1 8 206 22 646728 646728 33486.6 930.184 0.18 0.0650705 0.0566044 1588 8314 -1 169 20 235 523 16218 5641 2.44258 2.44258 -104.337 -2.44258 0 0 42482.2 1180.06 0.00 0.03 0.01 -1 -1 0.00 0.0191215 0.0169186 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.36 vpr 64.27 MiB -1 -1 0.42 23164 5 0.11 -1 -1 33216 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65812 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 164 398 79 297 22 64.3 MiB 0.01 0.00 2.2508 2.15218 -91.8425 -2.15218 2.15218 0.02 0.000227783 0.000206793 0.00390619 0.00362792 -1 -1 -1 -1 14 175 18 646728 646728 52871.9 1468.66 0.06 0.0313989 0.0271262 1728 14180 -1 158 12 158 364 11157 4123 2.26022 2.26022 -100.753 -2.26022 0 0 63794.4 1772.07 0.00 0.01 0.01 -1 -1 0.00 0.00841703 0.00759816 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/apex2_block_locations.place b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/apex2_block_locations.place index 70ff5b0f62..84ede063b4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/apex2_block_locations.place +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/apex2_block_locations.place @@ -1,175 +1,181 @@ #block name x y subblk layer block number #---------- -- -- ------ ----- ------------ -o_1_ 4 3 0 0 #0 -o_2_ 1 2 1 0 #1 -o_0_ 3 3 4 0 #2 -n_n1827 3 1 5 0 #3 -n_n1829 3 1 0 0 #4 -n_n1812 1 1 3 0 #5 -n_n1866 3 1 3 0 #6 -n_n1865 4 1 5 0 #7 -[493] 5 4 4 0 #8 -n_n544 4 4 3 0 #9 -n_n416 2 2 2 0 #10 -n_n394 2 1 3 0 #11 -n_n391 2 1 0 0 #12 -n_n300 2 1 1 0 #13 -[260] 3 5 3 0 #14 -n_n437 5 1 3 0 #15 -[223] 3 4 2 0 #16 -[79] 3 5 0 0 #17 -[410] 3 5 4 0 #18 -[516] 4 5 4 0 #19 -[245] 5 5 3 0 #20 -[340] 3 3 5 0 #21 -[432] 3 5 1 0 #22 -[80] 4 4 4 0 #23 -[541] 5 4 2 0 #24 -n_n309 2 1 5 0 #25 -[8] 4 5 1 0 #26 -[546] 4 5 3 0 #27 -n_n706 3 1 2 0 #28 -[261] 3 1 4 0 #29 -[463] 5 2 3 0 #30 -n_n1575 4 5 0 0 #31 -n_n1571 3 4 1 0 #32 -[132] 2 5 4 0 #33 -[355] 3 4 0 0 #34 -[214] 5 3 4 0 #35 -[267] 5 4 0 0 #36 -n_n329 5 1 4 0 #37 -[420] 5 3 1 0 #38 -n_n849 3 1 1 0 #39 -[478] 5 5 0 0 #40 -[578] 1 2 5 0 #41 -[253] 2 3 0 0 #42 -[4] 4 2 0 0 #43 -[56] 1 1 2 0 #44 -[226] 2 2 4 0 #45 -[282] 3 3 2 0 #46 -[377] 1 1 0 0 #47 -[71] 1 1 1 0 #48 -[319] 5 2 0 0 #49 -[233] 2 4 3 0 #50 -[246] 2 4 0 0 #51 -[301] 3 5 5 0 #52 -[441] 2 5 1 0 #53 -[608] 5 4 5 0 #54 -[21] 2 1 2 0 #55 -[311] 4 1 4 0 #56 -[344] 3 2 1 0 #57 -[310] 4 1 3 0 #58 -[315] 4 1 1 0 #59 -[29] 3 2 4 0 #60 -[273] 3 4 5 0 #61 -n_n1690 2 4 4 0 #62 -[383] 4 4 1 0 #63 -[390] 3 2 3 0 #64 -[705] 5 4 3 0 #65 -[41] 5 3 2 0 #66 -[351] 5 2 4 0 #67 -[484] 5 2 5 0 #68 -[437] 5 5 1 0 #69 -[349] 2 3 4 0 #70 -[65] 5 5 4 0 #71 -[221] 4 5 5 0 #72 -[402] 2 4 2 0 #73 -[521] 1 2 0 0 #74 -[767] 4 2 3 0 #75 -[133] 2 5 2 0 #76 -[234] 4 3 4 0 #77 -[868] 3 3 3 0 #78 -[904] 4 3 1 0 #79 -[906] 5 3 3 0 #80 -[919] 4 2 1 0 #81 -[1253] 4 1 0 0 #82 -[1283] 1 2 4 0 #83 -[1340] 3 2 0 0 #84 -[1382] 2 2 5 0 #85 -[1404] 3 2 2 0 #86 -[1417] 1 2 3 0 #87 -[1534] 4 4 2 0 #88 -[1615] 2 5 5 0 #89 -[6947] 3 4 4 0 #90 -[7082] 4 4 0 0 #91 -[7159] 5 2 1 0 #92 -[7165] 5 4 1 0 #93 -[7191] 4 3 2 0 #94 -[7319] 1 3 1 0 #95 -[7321] 3 3 0 0 #96 -[7351] 2 3 5 0 #97 -[7388] 2 2 3 0 #98 -[7423] 2 1 4 0 #99 -[7466] 3 2 5 0 #100 -[7782] 4 3 3 0 #101 -[7822] 3 4 3 0 #102 -[7885] 3 5 2 0 #103 -[7888] 4 2 4 0 #104 -[7997] 5 5 2 0 #105 -[8027] 5 3 0 0 #106 -[50] 2 3 3 0 #107 -[288] 2 3 1 0 #108 -[539] 5 3 5 0 #109 -[372] 4 3 5 0 #110 -n_n1584 2 4 5 0 #111 -[196] 2 3 2 0 #112 -[585] 1 3 2 0 #113 -[365] 4 4 5 0 #114 -[492] 4 2 2 0 #115 -[616] 3 3 1 0 #116 -[430] 2 2 1 0 #117 -[663] 2 2 0 0 #118 -[700] 4 2 5 0 #119 -[322] 1 3 5 0 #120 -[739] 1 3 4 0 #121 -[745] 4 1 2 0 #122 -[771] 2 4 1 0 #123 -[95] 4 5 2 0 #124 -[345] 1 2 2 0 #125 -[759] 1 3 0 0 #126 -[1066] 1 4 3 0 #127 -[7199] 5 2 2 0 #128 -[7969] 2 5 3 0 #129 -[7328] 1 3 3 0 #130 -[7559] 1 4 4 0 #131 -out:o_1_ 6 3 3 0 #132 -out:o_2_ 0 2 3 0 #133 -out:o_0_ 3 6 5 0 #134 -i_30_ 3 6 3 0 #135 -i_20_ 6 5 2 0 #136 -i_9_ 2 0 5 0 #137 -i_10_ 4 0 1 0 #138 -i_7_ 3 6 1 0 #139 -i_8_ 2 0 7 0 #140 -i_5_ 2 0 1 0 #141 -i_6_ 3 0 7 0 #142 -i_27_ 4 6 6 0 #143 -i_14_ 4 6 3 0 #144 -i_3_ 4 6 5 0 #145 -i_28_ 3 0 6 0 #146 -i_13_ 4 6 0 0 #147 -i_4_ 6 1 6 0 #148 -i_25_ 2 6 1 0 #149 -i_12_ 2 0 4 0 #150 -i_1_ 6 1 5 0 #151 -i_26_ 4 0 4 0 #152 -i_11_ 2 0 3 0 #153 -i_2_ 6 1 7 0 #154 -i_23_ 3 6 4 0 #155 -i_18_ 2 0 2 0 #156 -i_24_ 3 0 5 0 #157 -i_17_ 3 6 2 0 #158 -i_0_ 4 0 0 0 #159 -i_21_ 4 6 4 0 #160 -i_16_ 3 6 6 0 #161 -i_22_ 2 0 0 0 #162 -i_32_ 3 0 0 0 #163 -i_31_ 3 6 7 0 #164 -i_34_ 3 6 0 0 #165 -i_33_ 3 0 3 0 #166 -i_19_ 2 0 6 0 #167 -i_36_ 5 6 7 0 #168 -i_35_ 3 0 4 0 #169 -i_38_ 3 0 2 0 #170 -i_29_ 4 6 1 0 #171 -i_37_ 4 0 5 0 #172 +o_1_ 4 1 4 0 #0 +o_2_ 4 3 4 0 #1 +o_0_ 2 2 0 0 #2 +n_n1829 3 5 4 0 #3 +n_n1812 5 3 5 0 #4 +n_n1866 4 5 1 0 #5 +n_n1865 4 5 3 0 #6 +[493] 2 1 2 0 #7 +n_n544 3 1 0 0 #8 +n_n416 4 4 0 0 #9 +n_n394 5 4 5 0 #10 +n_n391 5 3 4 0 #11 +n_n300 4 5 5 0 #12 +[260] 3 2 4 0 #13 +[223] 3 1 4 0 #14 +[79] 2 2 4 0 #15 +[410] 1 3 1 0 #16 +[516] 1 3 2 0 #17 +[530] 1 1 1 0 #18 +[245] 1 2 0 0 #19 +[340] 1 4 4 0 #20 +[432] 3 1 2 0 #21 +[533] 2 3 3 0 #22 +[80] 2 2 5 0 #23 +[535] 1 2 1 0 #24 +n_n316 4 2 4 0 #25 +[541] 1 2 5 0 #26 +n_n1563 2 2 1 0 #27 +n_n1585 2 3 4 0 #28 +[38] 2 3 2 0 #29 +n_n706 4 2 3 0 #30 +n_n608 2 1 1 0 #31 +[261] 4 1 0 0 #32 +[463] 5 1 3 0 #33 +n_n1578 1 2 3 0 #34 +[124] 2 3 1 0 #35 +[132] 3 3 2 0 #36 +[227] 1 1 3 0 #37 +[267] 2 2 2 0 #38 +n_n329 2 2 3 0 #39 +n_n849 4 5 0 0 #40 +[478] 2 3 0 0 #41 +[578] 5 5 0 0 #42 +[253] 5 3 2 0 #43 +[4] 5 4 3 0 #44 +[56] 4 4 3 0 #45 +[226] 4 2 5 0 #46 +[282] 5 4 2 0 #47 +[377] 5 5 4 0 #48 +[71] 5 3 3 0 #49 +[246] 3 2 1 0 #50 +[301] 3 1 1 0 #51 +[311] 4 4 4 0 #52 +[344] 4 4 1 0 #53 +[310] 4 2 2 0 #54 +[315] 4 3 0 0 #55 +[78] 3 5 5 0 #56 +[656] 5 3 0 0 #57 +[29] 2 4 1 0 #58 +[273] 3 1 3 0 #59 +[668] 1 2 4 0 #60 +[674] 5 3 1 0 #61 +[74] 1 2 2 0 #62 +n_n1704 4 1 3 0 #63 +[327] 4 5 2 0 #64 +[305] 1 4 3 0 #65 +n_n1702 4 1 5 0 #66 +[351] 5 2 3 0 #67 +[437] 3 3 3 0 #68 +[349] 5 1 5 0 #69 +[65] 1 1 0 0 #70 +[221] 2 1 5 0 #71 +[343] 3 4 5 0 #72 +[406] 5 2 5 0 #73 +[521] 5 4 0 0 #74 +[161] 3 1 5 0 #75 +[189] 2 4 2 0 #76 +[906] 2 4 3 0 #77 +[977] 4 3 5 0 #78 +[1340] 4 4 5 0 #79 +[1426] 5 2 1 0 #80 +[1435] 5 4 1 0 #81 +[1542] 4 3 3 0 #82 +[1615] 3 4 3 0 #83 +[1619] 4 1 2 0 #84 +[6958] 1 4 2 0 #85 +[7025] 5 2 4 0 #86 +[7082] 1 1 5 0 #87 +[7160] 3 2 2 0 #88 +[7319] 3 4 0 0 #89 +[7321] 4 5 4 0 #90 +[7388] 3 3 0 0 #91 +[7390] 3 5 2 0 #92 +[7787] 1 3 3 0 #93 +[7791] 2 3 5 0 #94 +[7811] 2 1 3 0 #95 +[7822] 4 2 0 0 #96 +[7829] 2 1 4 0 #97 +[7885] 3 4 4 0 #98 +[7899] 1 3 5 0 #99 +[7901] 1 1 4 0 #100 +[7997] 1 3 4 0 #101 +[8027] 2 1 0 0 #102 +[8042] 1 4 1 0 #103 +[50] 3 5 3 0 #104 +[307] 3 2 5 0 #105 +[275] 3 2 3 0 #106 +[372] 3 4 1 0 #107 +[503] 3 5 0 0 #108 +[585] 2 4 4 0 #109 +[63] 2 5 3 0 #110 +[431] 5 2 2 0 #111 +[447] 3 3 1 0 #112 +[615] 2 4 5 0 #113 +n_n1716 1 3 0 0 #114 +[254] 4 3 2 0 #115 +[381] 5 4 4 0 #116 +[430] 4 3 1 0 #117 +[276] 4 4 2 0 #118 +[760] 3 4 2 0 #119 +[768] 4 1 1 0 #120 +[792] 2 5 2 0 #121 +[721] 5 2 0 0 #122 +[877] 3 2 0 0 #123 +[884] 4 2 1 0 #124 +[1021] 3 3 5 0 #125 +[1077] 3 3 4 0 #126 +[1700] 1 4 0 0 #127 +[7108] 2 4 0 0 #128 +[7211] 5 1 1 0 #129 +[7516] 2 5 0 0 #130 +[7531] 2 5 4 0 #131 +[7820] 1 4 5 0 #132 +[7917] 2 5 5 0 #133 +[7028] 2 5 1 0 #134 +[7774] 1 5 5 0 #135 +[7778] 1 5 2 0 #136 +[177] 1 1 2 0 #137 +out:o_1_ 4 0 0 0 #138 +out:o_2_ 4 6 1 0 #139 +out:o_0_ 2 0 4 0 #140 +i_30_ 2 6 7 0 #141 +i_20_ 2 0 3 0 #142 +i_9_ 5 6 5 0 #143 +i_10_ 3 6 6 0 #144 +i_7_ 2 0 5 0 #145 +i_8_ 4 6 4 0 #146 +i_5_ 5 6 6 0 #147 +i_6_ 3 0 3 0 #148 +i_27_ 3 0 1 0 #149 +i_14_ 2 0 1 0 #150 +i_3_ 6 4 5 0 #151 +i_28_ 3 0 7 0 #152 +i_13_ 2 0 2 0 #153 +i_4_ 6 2 7 0 #154 +i_25_ 4 6 0 0 #155 +i_12_ 1 0 4 0 #156 +i_1_ 6 2 2 0 #157 +i_26_ 3 6 2 0 #158 +i_11_ 4 0 1 0 #159 +i_2_ 4 6 7 0 #160 +i_23_ 2 0 7 0 #161 +i_18_ 5 6 4 0 #162 +i_24_ 2 0 6 0 #163 +i_17_ 3 0 0 0 #164 +i_0_ 4 0 5 0 #165 +i_21_ 2 6 1 0 #166 +i_16_ 0 3 0 0 #167 +i_22_ 3 6 0 0 #168 +i_32_ 3 6 7 0 #169 +i_31_ 2 6 5 0 #170 +i_34_ 1 0 6 0 #171 +i_33_ 4 0 7 0 #172 +i_19_ 6 4 6 0 #173 +i_36_ 1 0 1 0 #174 +i_35_ 1 0 7 0 #175 +i_38_ 4 6 3 0 #176 +i_29_ 3 6 1 0 #177 +i_37_ 3 0 6 0 #178 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt index e41ab909d3..d90ada2602 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fix_clusters_test_arch.xml apex2.blif common 14.77 vpr 75.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76916 38 3 1916 1919 0 1054 173 7 7 49 clb auto 34.4 MiB 4.62 5572 1135 0 0 1135 75.1 MiB 0.08 0.01 5.10521 -15.0504 -5.10521 nan 0.19 0.00530639 0.00465724 0.0561264 0.0529208 -1 -1 -1 -1 164 7542 34 1.34735e+06 7.11401e+06 957298. 19536.7 7.09 2.13567 1.82713 18546 296938 -1 6979 21 5560 22630 961929 323712 5.65021 nan -16.5347 -5.65021 0 0 1.19720e+06 24432.6 0.05 0.66 0.37 -1 -1 0.05 0.343651 0.311264 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fix_clusters_test_arch.xml apex2.blif common 6.61 vpr 73.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 138 38 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75188 38 3 1916 1919 0 1057 179 7 7 49 clb auto 33.4 MiB 2.49 5571 5572 1187 0 0 1187 73.4 MiB 0.04 0.00 4.76188 4.76188 -14.2451 -4.76188 nan 0.08 0.00203898 0.00182919 0.0306807 0.029482 -1 -1 -1 -1 158 7466 37 1.34735e+06 7.43737e+06 924312. 18863.5 2.54 0.731546 0.634858 18354 286522 -1 7089 17 5844 24589 1071101 337183 5.3663 nan -15.678 -5.3663 0 0 1.15416e+06 23554.3 0.02 0.30 0.14 -1 -1 0.02 0.147027 0.135635 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt index c4013f9bc8..28c9522e97 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.09 vpr 66.02 MiB -1 -1 0.81 27020 5 0.18 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67608 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.06 152 364 33 322 9 66.0 MiB 0.01 0.00 2.14643 -90.9948 -2.14643 2.14643 0.04 0.000424487 0.000372936 0.00685813 0.00616631 -1 -1 -1 -1 12 186 21 646728 646728 19965.4 554.594 0.11 0.0652242 0.0564867 1696 3924 -1 174 15 217 480 10553 3153 2.17275 2.17275 -93.6282 -2.17275 0 0 25971.8 721.439 0.00 0.02 0.01 -1 -1 0.00 0.0180304 0.016231 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.32 vpr 63.74 MiB -1 -1 0.41 23432 5 0.11 -1 -1 32968 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65272 10 2 181 183 1 36 24 6 6 36 clb auto 24.3 MiB 0.02 196 160 296 27 253 16 63.7 MiB 0.01 0.00 2.24217 2.14643 -91.5793 -2.14643 2.14643 0.01 0.000221516 0.000202499 0.00321232 0.00299107 -1 -1 -1 -1 14 192 17 646728 646728 22986.6 638.518 0.05 0.0309908 0.0267298 1728 4488 -1 182 16 236 481 10669 3290 2.16575 2.16575 -94.0923 -2.16575 0 0 30529.5 848.041 0.00 0.01 0.00 -1 -1 0.00 0.00976176 0.00870492 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt index ce66e9945a..a7c5718064 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_placement/read_write/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 1.95 vpr 67.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 79 14 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69432 14 8 926 934 0 494 101 11 11 121 -1 mcnc_small 28.1 MiB 0.87 4705 3156 292 2673 191 67.8 MiB 0.15 0.01 4.69669 -33.5098 -4.69669 nan 0.00 0.00334751 0.00291356 0.0814872 0.072816 -1 -1 -1 -1 -1 6609 17 4.36541e+06 4.25763e+06 511363. 4226.14 0.32 0.279395 0.254136 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 1.12 vpr 65.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67508 14 8 926 934 0 487 100 11 11 121 -1 mcnc_small 27.4 MiB 0.57 4953 4661 2884 275 2439 170 65.9 MiB 0.06 0.00 4.90946 4.65107 -32.6907 -4.65107 nan 0.00 0.00129958 0.00112134 0.0315588 0.0290293 -1 -1 -1 -1 -1 6424 17 4.36541e+06 4.20373e+06 511363. 4226.14 0.13 0.111922 0.10317 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt index e37401667f..44513bafe3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flat_router/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 11.85 vpr 79.08 MiB -1 -1 3.58 35500 16 0.65 -1 -1 38580 -1 -1 60 45 3 1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80980 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.0 MiB 3.23 6742 28689 8224 17037 3428 79.1 MiB 0.65 0.01 10.7103 -7090.32 -10.7103 10.7103 0.00 0.00310914 0.00279648 0.314019 0.270375 -1 -1 -1 -1 -1 10349 13 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 1.50 0.423776 0.367585 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 12.82 vpr 78.98 MiB -1 -1 3.48 35500 16 0.73 -1 -1 38088 -1 -1 60 45 3 1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80880 45 32 1192 1151 1 782 141 14 14 196 memory auto 40.1 MiB 3.28 6742 28689 8224 17037 3428 79.0 MiB 0.59 0.01 10.7103 -7090.32 -10.7103 10.7103 0.00 0.00230907 0.0018852 0.209392 0.171163 -1 -1 -1 -1 -1 10313 15 9.20055e+06 5.27364e+06 1.47691e+06 7535.23 2.42 0.342057 0.287674 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 6.16 vpr 78.76 MiB -1 -1 1.71 32288 16 0.37 -1 -1 34608 -1 -1 61 45 3 1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 80648 45 32 1192 1151 1 792 142 14 14 196 memory auto 40.6 MiB 1.64 10043 6801 30482 8149 18842 3491 78.8 MiB 0.35 0.00 13.3138 11.1501 -7129.64 -11.1501 11.1501 0.00 0.00174904 0.00155806 0.163194 0.145181 -1 -1 -1 -1 -1 10299 11 9.20055e+06 5.32753e+06 1.47691e+06 7535.23 0.92 0.203266 0.180044 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common_--router_algorithm_parallel_--num_workers_4 6.33 vpr 77.97 MiB -1 -1 1.76 32288 16 0.37 -1 -1 34608 -1 -1 61 45 3 1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 79844 45 32 1192 1151 1 792 142 14 14 196 memory auto 39.7 MiB 1.66 10043 6801 30482 8149 18842 3491 78.0 MiB 0.38 0.00 13.3138 11.1501 -7129.64 -11.1501 11.1501 0.00 0.002096 0.00193612 0.189184 0.169223 -1 -1 -1 -1 -1 10115 13 9.20055e+06 5.32753e+06 1.47691e+06 7535.23 0.94 0.241728 0.212629 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt index 120190057e..c73c30f4e7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - shorted_flyover_wires.xml raygentop.v common 28.09 vpr 86.75 MiB -1 -1 4.22 45380 3 0.89 -1 -1 40652 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88832 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.9 MiB 3.72 13488 259154 85177 151229 22748 86.8 MiB 1.98 0.02 4.96832 -2863.05 -4.96832 4.96832 0.58 0.00616009 0.0056108 0.73686 0.651724 -1 -1 -1 -1 70 25183 26 1.65001e+07 9.87633e+06 1.20853e+06 3347.73 11.82 3.63311 3.252 37321 249029 -1 22818 16 6009 15172 1561129 440571 5.14889 5.14889 -3166.68 -5.14889 0 0 1.52253e+06 4217.55 0.11 0.96 0.44 -1 -1 0.11 0.466679 0.43649 - buffered_flyover_wires.xml raygentop.v common 23.51 vpr 86.14 MiB -1 -1 4.32 45316 3 0.90 -1 -1 40936 -1 -1 129 236 1 6 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88212 236 305 3199 3011 1 1520 677 19 19 361 io clb auto 45.3 MiB 3.23 13888 238357 80681 139370 18306 86.1 MiB 2.42 0.04 5.12299 -3013.43 -5.12299 5.12299 0.55 0.0104225 0.00890059 0.853806 0.753587 -1 -1 -1 -1 68 27200 39 1.65001e+07 9.87633e+06 1.22105e+06 3382.40 7.94 3.27933 2.93318 36601 236909 -1 22538 20 6241 16122 1654804 449740 5.13382 5.13382 -3162.81 -5.13382 0 0 1.52022e+06 4211.15 0.06 0.81 0.27 -1 -1 0.06 0.458331 0.421893 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +shorted_flyover_wires.xml raygentop.v common 13.05 vpr 84.58 MiB -1 -1 2.12 42452 3 0.54 -1 -1 36992 -1 -1 127 236 1 6 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 86608 236 305 3199 3011 1 1523 675 19 19 361 io clb auto 45.8 MiB 2.00 27296 13779 258108 83434 152259 22415 84.6 MiB 1.01 0.01 7.04327 4.6633 -2876.07 -4.6633 4.6633 0.22 0.00384162 0.00353538 0.373809 0.341059 -1 -1 -1 -1 66 28548 38 1.65001e+07 9.76854e+06 1.15238e+06 3192.19 4.66 1.67708 1.52521 36241 234685 -1 23562 17 7064 18761 2090675 558075 5.13544 5.13544 -3151.56 -5.13544 0 0 1.43513e+06 3975.42 0.04 0.47 0.15 -1 -1 0.04 0.217891 0.205807 +buffered_flyover_wires.xml raygentop.v common 11.55 vpr 85.09 MiB -1 -1 2.10 42460 3 0.53 -1 -1 37000 -1 -1 127 236 1 6 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87132 236 305 3199 3011 1 1523 675 19 19 361 io clb auto 45.5 MiB 1.92 27785 13427 264026 91487 153189 19350 85.1 MiB 1.10 0.01 6.32496 5.30188 -3110.04 -5.30188 5.30188 0.22 0.00381565 0.00339367 0.399911 0.362007 -1 -1 -1 -1 68 25731 48 1.65001e+07 9.76854e+06 1.22105e+06 3382.40 3.29 1.47331 1.33967 36601 236909 -1 21906 18 6197 16350 1514118 406281 5.17215 5.17215 -3213.24 -5.17215 0 0 1.52022e+06 4211.15 0.04 0.40 0.15 -1 -1 0.04 0.208871 0.19661 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt index dabc7597d4..b5335622c0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - hard_fpu_arch_timing.xml mm3.v common 6.82 vpr 64.38 MiB -1 -1 0.19 22024 1 0.04 -1 -1 33832 -1 -1 0 193 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 65924 193 32 545 422 1 386 228 22 22 484 block_FPU auto 25.0 MiB 5.38 4984 53124 22938 29850 336 64.4 MiB 0.31 0.00 2.985 -851.626 -2.985 2.985 0.00 0.00244064 0.00235262 0.159831 0.149979 -1 -1 -1 -1 6456 16.7688 1716 4.45714 553 553 191807 53335 882498 103149 1.07647e+06 2224.11 4 26490 217099 -1 2.985 2.985 -877.692 -2.985 -13.5705 -0.0851 0.36 -1 -1 64.4 MiB 0.06 0.186546 0.175569 64.4 MiB -1 0.10 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +hard_fpu_arch_timing.xml mm3.v common 1.28 vpr 62.56 MiB -1 -1 0.12 18296 1 0.03 -1 -1 30596 -1 -1 0 193 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64064 193 32 545 422 1 385 229 30 30 900 block_FPU auto 23.0 MiB 0.17 8272 4968 58329 25699 32293 337 62.6 MiB 0.17 0.00 2.985 2.985 -855.954 -2.985 2.985 0.00 0.00102514 0.000966269 0.0891074 0.0841771 -1 -1 -1 -1 6670 17.3698 1756 4.57292 533 533 185005 50756 1.6779e+06 137533 2.03108e+06 2256.75 5 48532 406344 -1 2.985 2.985 -882.014 -2.985 -13.6953 -0.0851 0.29 -1 -1 62.6 MiB 0.04 0.10822 0.102432 62.6 MiB -1 0.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt index e047740054..099d93a64b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 4.15 vpr 68.14 MiB -1 -1 0.41 22436 3 0.11 -1 -1 37108 -1 -1 67 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69772 99 130 344 474 1 216 297 13 13 169 clb auto 28.7 MiB 1.30 640 27027 4243 10587 12197 68.1 MiB 0.05 0.00 34 1346 6 0 0 460544. 2725.11 1.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 2.04 vpr 66.23 MiB -1 -1 0.22 19108 3 0.06 -1 -1 33092 -1 -1 67 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67820 99 130 344 474 1 217 297 13 13 169 clb auto 26.3 MiB 0.77 1670 634 27027 2767 7163 17097 66.2 MiB 0.02 0.00 34 1203 16 0 0 460544. 2725.11 0.24 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt index cf73f2ff4e..f434dcaae8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.78 vpr 66.14 MiB -1 -1 0.81 27148 5 0.18 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67724 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000401166 0.00034964 0.00709766 0.00632609 -1 -1 -1 -1 -1 145 18 646728 646728 60312.4 1675.34 0.03 0.027091 0.0241271 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.18 vpr 64.26 MiB -1 -1 0.49 23432 5 0.11 -1 -1 33120 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65804 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 151 534 120 387 27 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.7778 -2.14835 2.14835 0.00 0.000227776 0.000204652 0.00485329 0.00448661 -1 -1 -1 -1 -1 141 16 646728 646728 60312.4 1675.34 0.01 0.0147473 0.0132924 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt index f56e6001d5..e1dcab4cc0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.43 vpr 60.44 MiB -1 -1 -1 -1 0 0.02 -1 -1 33044 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61892 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.1 MiB 0.00 0 3 0 0 3 60.4 MiB 0.00 0.00 nan 0 0 nan 0.00 1.4987e-05 8.361e-06 8.9733e-05 6.0433e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00144709 0.00137547 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.48 vpr 60.32 MiB -1 -1 -1 -1 0 0.02 -1 -1 33032 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61768 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.0 MiB 0.00 0 3 0 0 3 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3826e-05 7.652e-06 8.7137e-05 5.7527e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00164227 0.00157106 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.51 vpr 60.30 MiB -1 -1 -1 -1 0 0.02 -1 -1 33252 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61752 6 1 1 8 0 1 8 3 3 9 -1 auto 22.1 MiB 0.00 0 21 0 10 11 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2976e-05 6.744e-06 7.713e-05 4.9652e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00173371 0.00166423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.39 vpr 60.55 MiB -1 -1 -1 -1 0 0.02 -1 -1 33080 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62004 6 1 1 8 0 1 8 3 3 9 -1 auto 22.1 MiB 0.00 0 21 0 10 11 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2909e-05 6.758e-06 8.8443e-05 5.844e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00166613 0.00149072 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and.blif common 0.39 vpr 60.46 MiB -1 -1 -1 -1 1 0.02 -1 -1 33424 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 2 1 3 4 0 3 4 3 3 9 -1 auto 22.1 MiB 0.00 9 9 3 3 3 60.5 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.603e-05 1.0932e-05 0.000113667 8.4174e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00156248 0.00148561 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.53 vpr 60.38 MiB -1 -1 -1 -1 1 0.06 -1 -1 35020 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61832 5 1 6 7 0 6 7 3 3 9 -1 auto 22.0 MiB 0.00 18 18 13 5 0 60.4 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.1156e-05 1.5721e-05 0.000164706 0.000132685 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.0021653 0.00196366 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.54 vpr 60.58 MiB -1 -1 -1 -1 1 0.06 -1 -1 35532 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 5 1 6 7 0 6 7 3 3 9 -1 auto 22.3 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.769e-05 2.1131e-05 0.000172602 0.000136847 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00216675 0.00196156 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and_latch.blif common 0.35 vpr 60.45 MiB -1 -1 -1 -1 1 0.02 -1 -1 33200 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61900 3 1 5 6 1 4 5 3 3 9 -1 auto 22.1 MiB 0.00 9 12 7 1 4 60.4 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.0212e-05 1.4682e-05 0.000132923 0.000102253 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00163341 0.00154977 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml false_path_mux.blif common 0.52 vpr 60.54 MiB -1 -1 -1 -1 1 0.06 -1 -1 35376 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61992 4 1 4 6 0 4 6 3 3 9 -1 auto 22.1 MiB 0.00 12 15 9 3 3 60.5 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.9387e-05 1.4052e-05 0.000137513 0.000106148 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00195643 0.00179437 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 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60.4 MiB 0.00 0.00 0.69831 -4.13786 -0.69831 nan 0.00 5.0007e-05 4.1034e-05 0.000382344 0.000335402 -1 -1 -1 -1 -1 17 12 53894 53894 38783.3 4309.26 0.00 0.00342842 0.00312147 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x4.blif common 0.46 vpr 60.50 MiB -1 -1 -1 -1 2 0.06 -1 -1 35480 -1 -1 3 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61952 7 8 22 30 0 15 18 4 4 16 clb auto 22.0 MiB 0.01 51 64 26 37 1 60.5 MiB 0.00 0.00 1.24888 -7.62396 -1.24888 nan 0.00 9.577e-05 8.3665e-05 0.00076909 0.000710256 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.00462233 0.00417537 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_4x4.blif common 0.59 vpr 60.60 MiB -1 -1 -1 -1 4 0.09 -1 -1 35628 -1 -1 2 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62056 8 8 29 37 0 21 18 4 4 16 clb auto 22.1 MiB 0.02 74 64 20 44 0 60.6 MiB 0.00 0.00 2.04839 -11.7951 -2.04839 nan 0.00 0.000130354 0.000112521 0.00109012 0.00100934 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.01 0.00751475 0.0068714 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x5.blif common 0.62 vpr 61.08 MiB -1 -1 -1 -1 4 0.10 -1 -1 36048 -1 -1 4 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62548 10 10 47 57 0 39 24 4 4 16 clb auto 22.1 MiB 0.02 149 92 35 57 0 61.1 MiB 0.00 0.00 2.73035 -18.1288 -2.73035 nan 0.00 0.000192825 0.000170363 0.0016493 0.0015433 -1 -1 -1 -1 -1 123 10 215576 215576 99039.1 6189.95 0.01 0.00945092 0.00871858 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x6.blif common 0.78 vpr 61.08 MiB -1 -1 -1 -1 5 0.12 -1 -1 36408 -1 -1 5 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62544 11 11 61 72 0 51 27 5 5 25 clb auto 22.1 MiB 0.04 192 547 116 431 0 61.1 MiB 0.01 0.00 3.17925 -21.2667 -3.17925 nan 0.00 0.000440575 0.000406236 0.00673609 0.00616031 -1 -1 -1 -1 -1 163 16 485046 269470 186194. 7447.77 0.02 0.0214973 0.0195896 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_1bit.blif common 0.44 vpr 60.18 MiB -1 -1 -1 -1 1 0.05 -1 -1 34452 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61628 3 2 5 7 0 5 6 3 3 9 -1 auto 22.0 MiB 0.00 15 15 9 5 1 60.2 MiB 0.00 0.00 0.67231 -1.34462 -0.67231 nan 0.00 1.5359e-05 1.1242e-05 0.000119111 9.5167e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00191506 0.00178438 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_2bit.blif common 0.51 vpr 60.47 MiB -1 -1 -1 -1 1 0.06 -1 -1 35224 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61920 5 3 8 11 0 8 9 3 3 9 -1 auto 22.0 MiB 0.00 24 27 21 6 0 60.5 MiB 0.00 0.00 0.67231 -2.01693 -0.67231 nan 0.00 5.5301e-05 4.4627e-05 0.000313259 0.000267198 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00296269 0.00261801 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_3bit.blif common 0.50 vpr 60.56 MiB -1 -1 -1 -1 2 0.05 -1 -1 35444 -1 -1 1 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62016 7 4 12 16 0 11 12 3 3 9 -1 auto 22.1 MiB 0.01 33 38 24 11 3 60.6 MiB 0.00 0.00 1.08437 -4.00246 -1.08437 nan 0.00 2.6083e-05 2.0859e-05 0.000215587 0.000188913 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00234895 0.0022029 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_4bit.blif common 0.54 vpr 60.64 MiB -1 -1 -1 -1 2 0.06 -1 -1 35364 -1 -1 1 9 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62096 9 5 15 20 0 14 15 3 3 9 -1 auto 22.1 MiB 0.01 42 51 29 17 5 60.6 MiB 0.00 0.00 1.00731 -4.36655 -1.00731 nan 0.00 0.000111332 9.9634e-05 0.000559539 0.000502391 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.00 0.00351338 0.00318651 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_5bit.blif common 0.52 vpr 60.46 MiB -1 -1 -1 -1 3 0.07 -1 -1 35520 -1 -1 1 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 11 6 19 25 0 17 18 3 3 9 -1 auto 22.0 MiB 0.01 51 64 33 24 7 60.5 MiB 0.00 0.00 1.34231 -6.71386 -1.34231 nan 0.00 0.000697205 8.3358e-05 0.00115444 0.000499005 -1 -1 -1 -1 -1 25 11 53894 53894 38783.3 4309.26 0.00 0.00500091 0.00398839 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.34 vpr 57.98 MiB -1 -1 -1 -1 0 0.02 -1 -1 29676 -1 -1 1 0 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59368 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.5 MiB 0.00 0 0 3 0 0 3 58.0 MiB 0.00 0.00 nan nan 0 0 nan 0.00 6.996e-06 3.223e-06 5.3211e-05 3.4398e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000863794 0.000812483 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.33 vpr 58.66 MiB -1 -1 -1 -1 0 0.02 -1 -1 29680 -1 -1 1 0 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60072 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.9 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.371e-06 3.49e-06 5.5398e-05 3.5823e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000878581 0.000826543 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.33 vpr 58.58 MiB -1 -1 -1 -1 0 0.02 -1 -1 29952 -1 -1 1 0 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59988 6 1 1 8 0 1 8 3 3 9 -1 auto 20.0 MiB 0.00 0 0 21 0 10 11 58.6 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.077e-06 3.333e-06 5.2548e-05 3.4112e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000853936 0.000803623 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.34 vpr 58.66 MiB -1 -1 -1 -1 0 0.02 -1 -1 29952 -1 -1 1 0 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60072 6 1 1 8 0 1 8 3 3 9 -1 auto 20.2 MiB 0.00 0 0 21 0 10 11 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.282e-06 3.474e-06 5.2727e-05 3.3796e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000847143 0.000796207 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and.blif common 0.35 vpr 58.66 MiB -1 -1 -1 -1 1 0.02 -1 -1 29952 -1 -1 1 2 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60064 2 1 3 4 0 3 4 3 3 9 -1 auto 20.2 MiB 0.00 9 9 9 3 3 3 58.7 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.4427e-05 9.773e-06 9.9493e-05 7.2807e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.000960488 0.000893376 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.39 vpr 58.67 MiB -1 -1 -1 -1 1 0.03 -1 -1 31488 -1 -1 1 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 5 1 6 7 0 6 7 3 3 9 -1 auto 20.3 MiB 0.00 18 18 18 13 5 0 58.7 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.1789e-05 8.386e-06 0.000103966 8.3373e-05 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00116429 0.00105081 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.37 vpr 58.66 MiB -1 -1 -1 -1 1 0.03 -1 -1 31460 -1 -1 1 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60072 5 1 6 7 0 6 7 3 3 9 -1 auto 19.8 MiB 0.00 18 18 18 13 5 0 58.7 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.1368e-05 7.936e-06 9.4974e-05 7.4684e-05 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00115152 0.00104027 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and_latch.blif common 0.31 vpr 58.66 MiB -1 -1 -1 -1 1 0.02 -1 -1 30004 -1 -1 1 3 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60072 3 1 5 6 1 4 5 3 3 9 -1 auto 20.2 MiB 0.00 9 9 12 7 1 4 58.7 MiB 0.00 0.00 0.603526 0.52647 -0.88231 -0.52647 0.52647 0.00 1.1309e-05 7.805e-06 8.7741e-05 6.7206e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.000941428 0.000881861 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml false_path_mux.blif common 0.40 vpr 58.66 MiB -1 -1 -1 -1 1 0.03 -1 -1 31816 -1 -1 1 3 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60072 4 1 4 6 0 4 6 3 3 9 -1 auto 19.9 MiB 0.00 12 12 15 9 3 3 58.7 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 9.785e-06 6.479e-06 8.1527e-05 6.1448e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00107399 0.000971187 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_2x2.blif common 0.40 vpr 58.67 MiB -1 -1 -1 -1 1 0.03 -1 -1 31872 -1 -1 1 4 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 4 4 8 12 0 8 9 3 3 9 -1 auto 19.9 MiB 0.00 24 24 27 18 6 3 58.7 MiB 0.00 0.00 0.749366 0.67231 -2.68924 -0.67231 nan 0.00 1.9294e-05 1.3929e-05 0.000154322 0.000130844 -1 -1 -1 -1 -1 12 10 53894 53894 38783.3 4309.26 0.00 0.00137251 0.00124772 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x3.blif common 0.40 vpr 58.66 MiB -1 -1 -1 -1 1 0.04 -1 -1 31964 -1 -1 1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60064 6 6 12 18 0 12 13 3 3 9 -1 auto 20.4 MiB 0.00 36 36 43 32 7 4 58.7 MiB 0.00 0.00 0.775365 0.69831 -4.13786 -0.69831 nan 0.00 2.7112e-05 2.257e-05 0.00024967 0.000223666 -1 -1 -1 -1 -1 15 12 53894 53894 38783.3 4309.26 0.00 0.00184655 0.00166813 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x4.blif common 0.41 vpr 58.84 MiB -1 -1 -1 -1 2 0.04 -1 -1 32088 -1 -1 3 7 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60252 7 8 22 30 0 15 18 4 4 16 clb auto 19.9 MiB 0.01 62 51 64 26 37 1 58.8 MiB 0.00 0.00 1.24888 1.24888 -7.62396 -1.24888 nan 0.00 4.8354e-05 4.2277e-05 0.000477835 0.000444964 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.00247686 0.00230254 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_4x4.blif common 0.44 vpr 58.40 MiB -1 -1 -1 -1 4 0.05 -1 -1 32372 -1 -1 2 8 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59804 8 8 29 37 0 21 18 4 4 16 clb auto 19.8 MiB 0.01 82 74 64 20 44 0 58.4 MiB 0.00 0.00 2.04839 2.04839 -11.7951 -2.04839 nan 0.00 6.6106e-05 5.7401e-05 0.000669463 0.000632029 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.00 0.00381812 0.00349849 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x5.blif common 0.50 vpr 59.05 MiB -1 -1 -1 -1 4 0.06 -1 -1 32828 -1 -1 4 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60468 10 10 47 57 0 39 24 4 4 16 clb auto 20.2 MiB 0.01 161 149 92 35 57 0 59.1 MiB 0.00 0.00 2.80144 2.73035 -18.1288 -2.73035 nan 0.00 9.8264e-05 8.8722e-05 0.000988768 0.000940007 -1 -1 -1 -1 -1 120 10 215576 215576 99039.1 6189.95 0.01 0.00524214 0.00484004 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x6.blif common 0.57 vpr 59.18 MiB -1 -1 -1 -1 5 0.08 -1 -1 32920 -1 -1 5 11 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60600 11 11 61 72 0 49 27 5 5 25 clb auto 19.9 MiB 0.02 227 192 427 90 337 0 59.2 MiB 0.00 0.00 3.28962 3.19291 -21.0185 -3.19291 nan 0.00 0.000130543 0.000119435 0.00245056 0.00228934 -1 -1 -1 -1 -1 193 14 485046 269470 186194. 7447.77 0.01 0.00891919 0.00813612 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_1bit.blif common 0.39 vpr 58.42 MiB -1 -1 -1 -1 1 0.03 -1 -1 31072 -1 -1 1 3 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59824 3 2 5 7 0 5 6 3 3 9 -1 auto 19.7 MiB 0.00 15 15 15 9 5 1 58.4 MiB 0.00 0.00 0.749366 0.67231 -1.34462 -0.67231 nan 0.00 1.1943e-05 8.497e-06 9.9679e-05 7.8348e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.0011809 0.0010594 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_2bit.blif common 0.38 vpr 58.68 MiB -1 -1 -1 -1 1 0.03 -1 -1 32248 -1 -1 1 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60088 5 3 8 11 0 8 9 3 3 9 -1 auto 20.2 MiB 0.00 24 24 27 21 6 0 58.7 MiB 0.00 0.00 0.749366 0.67231 -2.01693 -0.67231 nan 0.00 1.8728e-05 1.3469e-05 0.000148109 0.000124042 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00146367 0.00130165 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_3bit.blif common 0.39 vpr 57.99 MiB -1 -1 -1 -1 2 0.03 -1 -1 32240 -1 -1 1 7 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59380 7 4 12 16 0 11 12 3 3 9 -1 auto 19.5 MiB 0.00 33 33 38 24 11 3 58.0 MiB 0.00 0.00 1.08437 1.08437 -4.00246 -1.08437 nan 0.00 2.2829e-05 1.8391e-05 0.000195041 0.000172271 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00137134 0.00127668 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_4bit.blif common 0.40 vpr 58.73 MiB -1 -1 -1 -1 2 0.03 -1 -1 32252 -1 -1 1 9 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60140 9 5 15 20 0 14 15 3 3 9 -1 auto 19.9 MiB 0.00 42 42 51 29 17 5 58.7 MiB 0.00 0.00 1.08437 1.00731 -4.36655 -1.00731 nan 0.00 3.3127e-05 2.8474e-05 0.000246042 0.000221132 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.00 0.00190242 0.00171776 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_5bit.blif common 0.40 vpr 58.75 MiB -1 -1 -1 -1 3 0.04 -1 -1 32252 -1 -1 1 11 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60164 11 6 19 25 0 17 18 3 3 9 -1 auto 20.2 MiB 0.00 51 51 64 36 21 7 58.8 MiB 0.00 0.00 1.41937 1.34231 -6.71386 -1.34231 nan 0.00 3.464e-05 2.8097e-05 0.000304999 0.000276916 -1 -1 -1 -1 -1 21 11 53894 53894 38783.3 4309.26 0.00 0.00211116 0.00192193 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt index b020b50a0e..2fc8a48a0d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.27 vpr 60.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61896 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.1 MiB 0.00 0 3 0 0 3 60.4 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1967e-05 6.442e-06 7.5021e-05 4.7762e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.0014839 0.00141592 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.27 vpr 60.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.3 MiB 0.00 0 3 0 0 3 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2368e-05 6.553e-06 8.0604e-05 5.2726e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00150763 0.00143643 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.26 vpr 60.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4901e-05 1.736e-05 0.000158286 0.000127589 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00189837 0.00180984 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.27 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.5 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4603e-05 1.7125e-05 0.000156465 0.000123185 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00157342 0.00148859 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.34 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 5 1 6 7 0 6 7 3 3 9 -1 auto 22.3 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.3071e-05 1.7468e-05 0.00015565 0.000122418 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00131998 0.0012364 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.34 vpr 60.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 5 1 6 7 0 6 7 3 3 9 -1 auto 22.0 MiB 0.00 18 18 13 5 0 60.5 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.4504e-05 1.843e-05 0.0003637 0.000327179 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00295184 0.00278863 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.21 vpr 58.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59740 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.7 MiB 0.00 0 0 3 0 0 3 58.3 MiB 0.00 0.00 nan nan 0 0 nan 0.00 6.893e-06 3.141e-06 5.3898e-05 3.4896e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000915795 0.000863453 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.23 vpr 58.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60068 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.9 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.372e-06 3.545e-06 5.351e-05 3.4093e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00083713 0.000785229 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.23 vpr 58.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 6 1 7 8 0 7 8 3 3 9 -1 auto 20.4 MiB 0.00 21 21 21 14 7 0 58.7 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.4276e-05 9.471e-06 0.000108017 8.5148e-05 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00100715 0.000943024 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.23 vpr 58.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59896 6 1 7 8 0 7 8 3 3 9 -1 auto 19.7 MiB 0.00 21 21 21 14 7 0 58.5 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.4296e-05 9.523e-06 0.000102065 8.2015e-05 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00101263 0.00095379 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.23 vpr 58.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59540 5 1 6 7 0 6 7 3 3 9 -1 auto 19.3 MiB 0.00 18 18 18 13 5 0 58.1 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.2432e-05 8.918e-06 0.00010449 8.2153e-05 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00103335 0.000960077 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.26 vpr 58.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60072 5 1 6 7 0 6 7 3 3 9 -1 auto 19.9 MiB 0.00 18 18 18 13 5 0 58.7 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.234e-05 8.789e-06 0.000105391 8.3483e-05 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00100107 0.000937259 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt index 0122eef07c..b4a6cb5e5d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - x_gaussian_y_uniform.xml stereovision3.v common 2.14 vpr 66.94 MiB -1 -1 0.82 26648 5 0.18 -1 -1 36964 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68548 10 2 181 183 1 37 19 6 6 36 clb auto 27.8 MiB 0.08 154 69 23 41 5 66.9 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.00 0.000368162 0.000336195 0.00306832 0.0028942 -1 -1 -1 -1 8 112 5 646728 377258 -1 -1 0.14 0.0630721 0.0541641 1804 2280 -1 112 3 60 81 2140 1007 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0123441 0.0115171 - x_uniform_y_gaussian.xml stereovision3.v common 2.28 vpr 66.56 MiB -1 -1 0.87 27028 5 0.18 -1 -1 36836 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68156 10 2 181 183 1 37 19 6 6 36 clb auto 27.6 MiB 0.06 139 119 44 63 12 66.6 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000434392 0.000379213 0.00478977 0.00443186 -1 -1 -1 -1 8 108 4 646728 377258 -1 -1 0.14 0.0614636 0.053576 1804 2280 -1 92 5 93 129 3144 1427 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0131686 0.0124064 - x_gaussian_y_gaussian.xml stereovision3.v common 1.95 vpr 66.73 MiB -1 -1 0.78 27032 5 0.16 -1 -1 36964 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68336 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.07 141 69 21 42 6 66.7 MiB 0.01 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000231421 0.000200473 0.00279286 0.00262007 -1 -1 -1 -1 6 107 4 646728 377258 -1 -1 0.13 0.0525266 0.046082 1804 2280 -1 105 4 77 102 2777 1152 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.01 -1 -1 0.00 0.0109087 0.0101911 - x_delta_y_uniform.xml stereovision3.v common 2.13 vpr 66.94 MiB -1 -1 0.67 26768 5 0.15 -1 -1 36648 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68548 10 2 181 183 1 37 19 6 6 36 clb auto 27.8 MiB 0.07 154 369 96 253 20 66.9 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000435432 0.00038302 0.00911423 0.00823072 -1 -1 -1 -1 24 117 4 646728 377258 -1 -1 0.31 0.174316 0.150618 1804 2280 -1 116 2 59 79 2150 954 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0153537 0.0147732 - x_delta_y_delta.xml stereovision3.v common 2.28 vpr 66.92 MiB -1 -1 0.81 26892 5 0.18 -1 -1 36968 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68524 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.10 140 544 127 376 41 66.9 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000465798 0.000412818 0.0124105 0.0110487 -1 -1 -1 -1 48 106 2 646728 377258 -1 -1 0.23 0.117282 0.102085 1804 2280 -1 106 2 57 77 1975 772 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00952273 0.00912406 - x_uniform_y_delta.xml stereovision3.v common 2.20 vpr 66.74 MiB -1 -1 0.80 27028 5 0.22 -1 -1 36648 -1 -1 7 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68344 10 2 181 183 1 37 19 6 6 36 clb auto 27.7 MiB 0.07 127 494 89 373 32 66.7 MiB 0.02 0.00 1.78694 -71.1304 -1.78694 1.78694 0.01 0.000426768 0.000373257 0.0117897 0.0105633 -1 -1 -1 -1 14 88 2 646728 377258 -1 -1 0.16 0.10372 0.0914305 1804 2280 -1 88 2 57 77 1819 773 1.78694 1.78694 -71.1304 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00845179 0.00814396 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +x_gaussian_y_uniform.xml stereovision3.v common 1.34 vpr 65.04 MiB -1 -1 0.42 23052 5 0.11 -1 -1 32952 -1 -1 7 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66596 10 2 181 183 1 38 19 6 6 36 clb auto 26.0 MiB 0.03 174 128 319 80 215 24 65.0 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000216857 0.000198279 0.00447385 0.00418212 -1 -1 -1 -1 8 83 5 646728 377258 -1 -1 0.05 0.0290209 0.0255131 1804 2280 -1 86 4 94 125 2948 1117 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00697511 0.0066155 +x_uniform_y_gaussian.xml stereovision3.v common 1.34 vpr 65.04 MiB -1 -1 0.42 23052 5 0.11 -1 -1 33000 -1 -1 7 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66596 10 2 181 183 1 38 19 6 6 36 clb auto 26.0 MiB 0.03 174 125 394 105 261 28 65.0 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000225321 0.000205891 0.00527543 0.00492147 -1 -1 -1 -1 6 93 11 646728 377258 -1 -1 0.07 0.0322663 0.0282449 1804 2280 -1 82 3 62 84 2005 787 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00663346 0.00633137 +x_gaussian_y_gaussian.xml stereovision3.v common 1.34 vpr 64.25 MiB -1 -1 0.41 23820 5 0.11 -1 -1 33004 -1 -1 7 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65796 10 2 181 183 1 38 19 6 6 36 clb auto 25.3 MiB 0.03 174 133 319 65 242 12 64.3 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000218507 0.000199708 0.00455873 0.00427407 -1 -1 -1 -1 6 107 5 646728 377258 -1 -1 0.06 0.0291262 0.0255849 1804 2280 -1 95 6 98 132 3372 1383 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00774239 0.00726615 +x_delta_y_uniform.xml stereovision3.v common 1.32 vpr 64.56 MiB -1 -1 0.42 23436 5 0.11 -1 -1 32944 -1 -1 7 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66108 10 2 181 183 1 38 19 6 6 36 clb auto 25.6 MiB 0.03 174 147 69 22 43 4 64.6 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000229494 0.00020885 0.00234329 0.00225041 -1 -1 -1 -1 14 107 3 646728 377258 -1 -1 0.04 0.0267102 0.0234306 1804 2280 -1 107 3 66 90 2381 972 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00666896 0.00636564 +x_delta_y_delta.xml stereovision3.v common 1.35 vpr 64.31 MiB -1 -1 0.44 23048 5 0.11 -1 -1 33000 -1 -1 7 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65856 10 2 181 183 1 38 19 6 6 36 clb auto 25.3 MiB 0.03 174 131 269 71 179 19 64.3 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000223709 0.000204248 0.00412555 0.00387782 -1 -1 -1 -1 24 87 3 646728 377258 -1 -1 0.04 0.0279184 0.0245799 1804 2280 -1 86 2 58 78 1869 774 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00636272 0.00611727 +x_uniform_y_delta.xml stereovision3.v common 1.30 vpr 64.96 MiB -1 -1 0.41 23048 5 0.11 -1 -1 33216 -1 -1 7 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66520 10 2 181 183 1 38 19 6 6 36 clb auto 26.0 MiB 0.03 174 128 369 99 241 29 65.0 MiB 0.01 0.00 1.78694 1.78694 -71.2229 -1.78694 1.78694 0.00 0.000232074 0.000212992 0.00502949 0.0047012 -1 -1 -1 -1 24 82 2 646728 377258 -1 -1 0.04 0.0287524 0.0253409 1804 2280 -1 82 2 59 79 1850 830 1.78694 1.78694 -71.2229 -1.78694 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00619336 0.00595395 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt index 93fc104644..7f23c6325f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.95 vpr 65.89 MiB -1 -1 0.73 26760 5 0.17 -1 -1 36900 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67476 10 2 181 183 1 35 24 6 6 36 clb auto 26.8 MiB 0.04 153 500 90 382 28 65.9 MiB 0.02 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000660248 0.000574242 0.010203 0.00905969 -1 -1 -1 -1 6 103 13 646728 646728 -1 -1 0.12 0.059948 0.0525698 1456 2040 -1 101 16 136 266 9131 3659 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0191372 0.0164753 - nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.99 vpr 66.10 MiB -1 -1 0.79 27276 5 0.17 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67688 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 148 466 75 365 26 66.1 MiB 0.01 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000394392 0.000346251 0.00742774 0.00666175 -1 -1 -1 -1 8 100 16 646728 646728 -1 -1 0.14 0.0718777 0.0632492 1456 2040 -1 101 19 134 278 9113 3613 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0163481 0.014725 - nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 2.10 vpr 66.14 MiB -1 -1 0.85 26896 5 0.16 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67728 10 2 181 183 1 35 24 6 6 36 clb auto 27.1 MiB 0.05 142 500 108 364 28 66.1 MiB 0.02 0.00 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000538248 0.000486042 0.00902515 0.00805903 -1 -1 -1 -1 4 86 10 646728 646728 -1 -1 0.05 0.0281105 0.0249862 1456 2040 -1 87 9 108 188 5936 2196 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0153203 0.0141626 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.31 vpr 64.42 MiB -1 -1 0.42 23428 5 0.11 -1 -1 32968 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65964 10 2 181 183 1 36 24 6 6 36 clb auto 25.0 MiB 0.02 196 169 92 28 59 5 64.4 MiB 0.01 0.00 1.83894 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000244746 0.000224957 0.00187949 0.00179104 -1 -1 -1 -1 6 131 18 646728 646728 -1 -1 0.07 0.0298655 0.0257115 1456 2040 -1 122 14 118 244 8464 3501 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.00920837 0.00829589 +nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.31 vpr 64.26 MiB -1 -1 0.41 23432 5 0.11 -1 -1 32980 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65804 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 163 296 52 224 20 64.3 MiB 0.01 0.00 1.83894 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000224316 0.000205078 0.00324269 0.00303826 -1 -1 -1 -1 8 116 21 646728 646728 -1 -1 0.07 0.0323754 0.0278875 1456 2040 -1 116 18 143 312 10670 4334 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0105058 0.00938661 +nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.30 vpr 64.06 MiB -1 -1 0.42 23048 5 0.11 -1 -1 33008 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65596 10 2 181 183 1 36 24 6 6 36 clb auto 24.8 MiB 0.02 196 150 398 89 285 24 64.1 MiB 0.01 0.00 1.83894 1.83894 -73.7881 -1.83894 1.83894 0.00 0.000228321 0.000209201 0.00399176 0.00373161 -1 -1 -1 -1 6 101 8 646728 646728 -1 -1 0.05 0.0287724 0.0250888 1456 2040 -1 102 10 126 245 7156 2526 1.83894 1.83894 -73.7881 -1.83894 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00776939 0.00709289 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt index afb5b419a6..3f29073bd0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 5.23 vpr 66.07 MiB -1 -1 0.81 27256 5 0.19 -1 -1 36672 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67656 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 1.88 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000389361 0.000337837 0.00712682 0.00635643 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.83 0.023313 0.0208517 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.40 vpr 63.94 MiB -1 -1 0.41 23432 5 0.11 -1 -1 32960 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65476 10 2 181 183 1 36 24 6 6 36 clb auto 24.4 MiB 0.02 196 160 398 88 284 26 63.9 MiB 1.17 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000228021 0.000207402 0.00403232 0.00374516 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.59 0.0145981 0.0131681 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt index 0cf367e9bd..3b53b7df3d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml stereovision3.v common 1.89 vpr 61.52 MiB -1 -1 0.73 27008 5 0.16 -1 -1 36840 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63000 10 2 181 183 1 37 19 5 5 25 clb auto 22.0 MiB 0.06 123 1025 767 190 68 61.5 MiB 0.03 0.00 2.0306 -84.8829 -2.0306 2.0306 0.02 0.000393487 0.000346106 0.0203419 0.0179997 -1 -1 -1 -1 24 106 9 485046 377258 28445.8 1137.83 0.08 0.0705347 0.0617863 1707 5297 -1 110 10 80 114 1470 618 1.99984 1.99984 -90.3874 -1.99984 0 0 37126.9 1485.07 0.00 0.02 0.01 -1 -1 0.00 0.0158626 0.0146013 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml stereovision3.v common 1.27 vpr 59.04 MiB -1 -1 0.41 23288 5 0.11 -1 -1 33004 -1 -1 7 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60456 10 2 181 183 1 38 19 5 5 25 clb auto 19.2 MiB 0.03 159 125 1025 754 215 56 59.0 MiB 0.02 0.00 2.0306 2.0306 -85.6043 -2.0306 2.0306 0.01 0.000225955 0.000206685 0.0115433 0.0105662 -1 -1 -1 -1 22 124 12 485046 377258 26278.6 1051.14 0.05 0.038911 0.034234 1659 4669 -1 117 9 73 106 1326 594 1.98035 1.98035 -88.0122 -1.98035 0 0 33449.3 1337.97 0.00 0.01 0.00 -1 -1 0.00 0.00865764 0.008017 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt index 891302c2b5..e7e3433b91 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm.xml diffeq.blif common 17.21 vpr 71.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72880 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.3 MiB 0.39 10472 141533 36950 100839 3744 71.2 MiB 1.37 0.02 7.46482 -1369.01 -7.46482 7.46482 0.56 0.00521343 0.00460525 0.3928 0.329697 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.35 2.1497 1.85535 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.84 0.19 -1 -1 0.04 0.261179 0.233132 - k4_N4_90nm.xml ex5p.blif common 19.31 vpr 67.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68632 8 63 1072 1135 0 894 437 22 22 484 clb auto 27.6 MiB 0.35 12004 99857 28319 69545 1993 67.0 MiB 0.94 0.02 6.86459 -313.968 -6.86459 nan 0.53 0.00337095 0.00291084 0.218826 0.187023 -1 -1 -1 -1 32 16530 34 891726 815929 949946. 1962.70 13.54 0.813128 0.698644 43920 162796 -1 14048 22 8455 31174 3329435 847924 6.8764 nan -316.234 -6.8764 0 0 1.22393e+06 2528.78 0.07 1.22 0.29 -1 -1 0.07 0.185657 0.165735 - k4_N4_90nm.xml s298.blif common 16.74 vpr 73.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 75068 4 6 1942 1948 1 1169 590 27 27 729 clb auto 33.1 MiB 0.44 13813 156389 45768 109723 898 73.3 MiB 1.71 0.02 12.2682 -96.384 -12.2682 12.2682 0.97 0.00611806 0.00498358 0.468986 0.387941 -1 -1 -1 -1 26 17490 32 1.39333e+06 1.29301e+06 1.22387e+06 1678.84 9.00 1.38473 1.15574 57250 204657 -1 16420 17 8603 42614 3232268 684840 12.0598 12.0598 -95.4975 -12.0598 0 0 1.55812e+06 2137.34 0.09 1.18 0.31 -1 -1 0.09 0.19019 0.169418 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm.xml diffeq.blif common 5.00 vpr 69.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71420 64 39 1935 1974 1 1075 542 23 23 529 clb auto 30.3 MiB 0.17 24088 10407 135291 36283 95683 3325 69.7 MiB 0.56 0.01 23.0912 7.70338 -1562.28 -7.70338 7.70338 0.21 0.00207796 0.00177949 0.141609 0.122512 -1 -1 -1 -1 24 13067 26 983127 978669 797780. 1508.09 2.51 0.433558 0.377521 39018 137339 -1 11571 16 6466 23559 1530116 397333 7.70338 7.70338 -1636.85 -7.70338 0 0 1.04508e+06 1975.57 0.02 0.32 0.08 -1 -1 0.02 0.0900486 0.0816571 +k4_N4_90nm.xml ex5p.blif common 6.79 vpr 65.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 8 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66596 8 63 1072 1135 0 892 433 22 22 484 clb auto 26.0 MiB 0.14 20089 11891 97016 28068 66779 2169 65.0 MiB 0.42 0.01 11.9965 7.14697 -323.69 -7.14697 nan 0.18 0.00136691 0.00120963 0.0934239 0.083507 -1 -1 -1 -1 32 16897 50 891726 807012 949946. 1962.70 4.46 0.345464 0.301916 43920 162796 -1 13798 21 8357 30046 2938323 715872 6.93884 nan -322.607 -6.93884 0 0 1.22393e+06 2528.78 0.04 0.46 0.10 -1 -1 0.04 0.0720886 0.0650513 +k4_N4_90nm.xml s298.blif common 9.22 vpr 72.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 579 4 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74380 4 6 1942 1948 1 1135 589 27 27 729 clb auto 32.6 MiB 0.19 26761 13173 158541 45950 111660 931 72.6 MiB 0.68 0.01 27.8284 12.5893 -95.8017 -12.5893 12.5893 0.30 0.00235651 0.00199562 0.170033 0.146893 -1 -1 -1 -1 24 18368 39 1.39333e+06 1.29078e+06 1.12265e+06 1539.99 5.78 0.563458 0.485267 54650 192211 -1 15957 20 8308 43971 3554658 708435 12.1943 12.1943 -92.9601 -12.1943 0 0 1.47093e+06 2017.74 0.02 0.65 0.11 -1 -1 0.02 0.12746 0.114832 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt index 639ae9a9ce..ba5bb413a2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.46 vpr 69.17 MiB -1 -1 0.83 26540 4 0.20 -1 -1 36184 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70832 11 2 303 283 2 81 28 7 7 49 clb auto 29.7 MiB 0.25 337 112 35 48 29 69.2 MiB 0.02 0.00 4.0728 0 0 3.92737 0.00 0.00065953 0.000573934 0.00619824 0.00583905 -1 -1 -1 -1 399 5.32000 131 1.74667 151 217 4511 1215 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.15796 4.01977 0 0 -197.842 -1.707 0.05 -1 -1 69.2 MiB 0.12 0.1152 0.11141 69.2 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.31 vpr 66.66 MiB -1 -1 0.41 23076 4 0.10 -1 -1 32976 -1 -1 15 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68260 11 2 303 283 2 82 28 7 7 49 clb auto 27.3 MiB 0.11 424 278 994 204 585 205 66.7 MiB 0.02 0.00 4.1851 4.05951 0 0 3.91314 0.00 0.000355447 0.000324584 0.0115851 0.0107409 -1 -1 -1 -1 318 4.18421 118 1.55263 161 242 4599 1282 1.07788e+06 808410 219490. 4479.39 5 5100 32136 -1 4.18749 3.93845 0 0 -197.86 -1.707 0.02 -1 -1 66.7 MiB 0.07 0.0776518 0.0748363 66.7 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index 7e56604873..d61417eb84 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common_--router_algorithm_parallel_--num_workers_4 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.14847 -1 1.95678 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.38647 -1 -1.28959 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt index 4db4b05c47..0130db9d3c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 3.05 vpr 68.36 MiB -1 -1 0.39 22432 3 0.12 -1 -1 36928 -1 -1 65 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70000 99 130 344 474 1 215 295 12 12 144 clb auto 29.2 MiB 0.19 685 24820 3391 8404 13025 68.4 MiB 0.05 0.00 32 1772 8 5.66058e+06 4.05111e+06 305575. 2122.05 1.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 1.33 vpr 66.32 MiB -1 -1 0.21 19084 3 0.06 -1 -1 33052 -1 -1 65 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67908 99 130 344 474 1 215 295 12 12 144 clb auto 27.1 MiB 0.08 1546 614 23839 3086 6279 14474 66.3 MiB 0.02 0.00 38 1473 8 5.66058e+06 4.05111e+06 345440. 2398.89 0.20 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt index 59b02c3fd0..5c5b099220 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_noc/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links - stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml complex_2_noc_1D_chain.blif complex_2_noc_1D_chain.flows common 104.06 vpr 1.07 GiB -1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1126272 2 32 2204 1661 1 1102 107 36 20 720 -1 EP4SGX110 955.6 MiB 4.04 6649 10733 2374 7396 963 1099.9 MiB 0.85 0.01 7.22684 -4978.81 -7.22684 7.22684 14.03 0.00387297 0.00336653 0.329346 0.282395 154 8599 14 0 0 6.94291e+06 9642.93 42.85 2.6403 2.32523 176404 1494154 -1 8630 10 2443 4554 1083511 308854 7.50808 7.50808 -5329.84 -7.50808 0 0 8.91809e+06 12386.2 1.07 0.65 2.72 -1 -1 1.07 0.27806 0.251316 400000 3e-09 1 4.1359e-25 0 0 0 -1 -1 -1 -1 -1 -1 -1 +arch circuit noc_flow script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time NoC_agg_bandwidth NoC_latency NoC_n_met_latency_constraints NoC_latency_overrun NoC_congested_bw NoC_congestion_ratio NoC_n_congested_links SAT_agg_bandwidth SAT_latency SAT_n_met_latency_constraints SAT_latency_overrun SAT_congested_bw SAT_congestion_ratio SAT_n_congested_links +stratixiv_arch.timing_small_with_a_embedded_mesh_noc_toplogy.xml complex_2_noc_1D_chain.blif complex_2_noc_1D_chain.flows common 41.93 vpr 1.07 GiB -1 2 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1124300 2 32 2204 1661 1 1104 108 36 20 720 -1 EP4SGX110 954.6 MiB 2.08 15097 6710 12958 2982 8805 1171 1097.9 MiB 0.46 0.01 8.01944 7.31997 -4968.85 -7.31997 7.31997 5.67 0.00268965 0.00237612 0.163783 0.144881 154 8889 12 0 0 6.94291e+06 9642.93 8.45 1.0006 0.886884 176404 1494154 -1 8829 14 2492 4758 998347 275320 7.64666 7.64666 -5202.88 -7.64666 0 0 8.91809e+06 12386.2 0.44 0.33 1.40 -1 -1 0.44 0.143978 0.134115 400000 3e-09 1 4.1359e-25 0 0 0 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt index b67a185d18..8c387239fb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.76 vpr 66.03 MiB -1 -1 0.86 26892 5 0.18 -1 -1 37096 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67612 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00186164 0.0017947 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.07 vpr 64.27 MiB -1 -1 0.41 23812 5 0.11 -1 -1 32976 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65812 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00102532 0.000993909 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt index 153be88f8d..49db14efb5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.90 vpr 66.02 MiB -1 -1 0.83 26896 5 0.19 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67604 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 66.0 MiB 0.01 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000402396 0.000353615 0.00726063 0.00647248 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00909673 0.00824277 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.07 vpr 64.27 MiB -1 -1 0.42 23048 5 0.11 -1 -1 33096 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65808 10 2 181 183 1 36 24 6 6 36 clb auto 25.2 MiB 0.02 196 151 500 122 353 25 64.3 MiB 0.01 0.00 2.24217 2.14643 -91.6412 -2.14643 2.14643 0.01 0.000219031 0.000200355 0.00455045 0.00420606 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00559415 0.00521559 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt index 6e6ab2e273..58c7f125c0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml mult_5x6.blif common 0.60 vpr 60.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62244 11 11 59 70 0 48 26 4 4 16 clb auto 22.1 MiB 0.03 179 862 260 602 0 60.8 MiB 0.02 0.00 2.46139 -19.889 -2.46139 nan 0.01 0.000312912 0.000279273 0.00803541 0.00727675 -1 -1 -1 -1 28 244 41 215576 215576 17602.3 1100.14 0.11 0.0569851 0.0502764 984 2821 -1 165 13 220 476 6314 3099 2.61613 nan -21.1174 -2.61613 0 0 21084.5 1317.78 0.00 0.01 0.00 -1 -1 0.00 0.0102047 0.00933765 - k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.06 vpr 23.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 23944 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 22.3 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml mult_5x6.blif common 0.38 vpr 59.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60628 11 11 59 70 0 48 26 4 4 16 clb auto 19.9 MiB 0.02 205 178 672 211 461 0 59.2 MiB 0.01 0.00 2.48509 2.46139 -19.889 -2.46139 nan 0.01 0.00011536 0.000105292 0.00300611 0.0027947 -1 -1 -1 -1 30 215 23 215576 215576 18771.3 1173.21 0.04 0.0198913 0.0171288 1016 3020 -1 186 15 222 505 8959 4790 2.75695 nan -23.0631 -2.75695 0 0 22855.5 1428.47 0.00 0.01 0.00 -1 -1 0.00 0.00605263 0.00548243 +k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.05 vpr 21.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 21860 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 19.5 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt index 12efb65ec8..39dac34ca3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml reg_4x32.blif common 2.54 vpr 77.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 32 33 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78852 33 32 161 193 1 65 97 34 34 1156 -1 32x32 21.4 MiB 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00178122 0.0017245 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml reg_4x32.blif common 1.00 vpr 74.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 32 33 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76772 33 32 161 193 1 65 97 34 34 1156 -1 32x32 19.3 MiB 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00117621 0.00114214 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt index 87ace76c19..40d082a0cd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common 0.20 vpr 64.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66472 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 21 30 9 19 2 64.9 MiB 0.00 0.00 0.646042 -3.51892 -0.646042 0.571 0.01 4.3045e-05 2.9263e-05 0.00159366 0.001524 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00159366 0.001524 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common 0.16 vpr 62.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64020 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 24 21 30 9 19 2 62.5 MiB 0.00 0.00 0.739166 0.646042 -3.51892 -0.646042 0.571 0.00 2.3408e-05 1.6118e-05 0.000972687 0.000932709 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000972687 0.000932709 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt index 8361bf1bfe..013fb5f21d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 38.75 vpr 978.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001760 10 10 168 178 1 68 30 11 8 88 io auto 955.3 MiB 0.46 364 858 131 680 47 978.3 MiB 0.06 0.00 6.37129 -69.6808 -6.37129 6.37129 1.81 0.000551403 0.000481676 0.0153225 0.013705 -1 -1 -1 -1 22 874 22 0 0 110609. 1256.92 1.54 0.247666 0.215864 11258 24748 -1 728 16 428 1746 95453 49745 6.73416 6.73416 -75.7525 -6.73416 0 0 134428. 1527.59 0.01 0.08 0.07 -1 -1 0.01 0.0332471 0.0304495 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 37.57 vpr 978.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001868 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.66 371 950 121 778 51 978.4 MiB 0.07 0.00 6.34606 -69.4373 -6.34606 6.34606 2.32 0.000744808 0.000651566 0.0166971 0.0148799 -1 -1 -1 -1 32 654 12 0 0 153433. 1743.56 0.90 0.149648 0.129506 11830 34246 -1 601 15 249 896 54680 24076 6.61838 6.61838 -74.0379 -6.61838 0 0 205860. 2339.32 0.01 0.07 0.09 -1 -1 0.01 0.0346715 0.0320467 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 34.09 vpr 978.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001652 10 10 168 178 1 68 30 11 8 88 io auto 955.4 MiB 0.44 376 582 74 468 40 978.2 MiB 0.07 0.00 6.26487 -68.7007 -6.26487 6.26487 2.74 0.000593656 0.000520243 0.0126605 0.0115382 -1 -1 -1 -1 28 858 45 0 0 134428. 1527.59 1.21 0.206409 0.180557 11590 29630 -1 614 14 305 1283 69506 33247 6.72367 6.72367 -73.5822 -6.72367 0 0 173354. 1969.93 0.01 0.08 0.06 -1 -1 0.01 0.0327372 0.0302784 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 41.01 vpr 978.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002252 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.60 352 582 88 454 40 978.8 MiB 0.05 0.00 6.37106 -69.2764 -6.37106 6.37106 3.17 0.000446168 0.000388088 0.0115458 0.0104844 -1 -1 -1 -1 22 778 22 0 0 110609. 1256.92 1.84 0.253098 0.220545 11258 24748 -1 690 15 386 1546 88347 46120 6.75259 6.75259 -75.6874 -6.75259 0 0 134428. 1527.59 0.01 0.08 0.06 -1 -1 0.01 0.0310233 0.0286671 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 23.23 vpr 980.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003544 10 10 168 178 1 65 30 11 8 88 io auto 953.5 MiB 0.34 461 363 812 65 683 64 980.0 MiB 0.06 0.00 6.74915 6.53925 -69.3815 -6.53925 6.53925 1.14 0.000300724 0.00027604 0.00848738 0.00790018 -1 -1 -1 -1 18 1016 35 0 0 88979.3 1011.13 0.47 0.0692639 0.0609638 11100 22242 -1 903 21 541 2228 132955 67625 6.88394 6.88394 -78.1788 -6.88394 0 0 114778. 1304.29 0.00 0.06 0.03 -1 -1 0.00 0.0201022 0.0183528 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 24.29 vpr 978.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1002320 10 10 168 178 1 65 30 11 8 88 io auto 952.8 MiB 0.35 461 360 766 54 639 73 978.8 MiB 0.06 0.00 6.74915 6.50519 -69.5865 -6.50519 6.50519 1.16 0.000305512 0.000272989 0.00848076 0.00791167 -1 -1 -1 -1 22 737 19 0 0 110609. 1256.92 0.28 0.0527671 0.0469086 11258 24748 -1 741 17 354 1302 73546 39254 6.97435 6.97435 -75.9089 -6.97435 0 0 134428. 1527.59 0.00 0.05 0.03 -1 -1 0.00 0.0179424 0.0165316 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 23.38 vpr 979.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003420 10 10 168 178 1 65 30 11 8 88 io auto 953.4 MiB 0.33 461 374 858 76 722 60 979.9 MiB 0.05 0.00 6.74915 6.37842 -69.0199 -6.37842 6.37842 1.56 0.000311373 0.000283765 0.00914771 0.00850328 -1 -1 -1 -1 18 1028 44 0 0 88979.3 1011.13 0.40 0.0650195 0.057065 11100 22242 -1 860 17 503 1822 111191 56265 7.04132 7.04132 -78.8721 -7.04132 0 0 114778. 1304.29 0.00 0.06 0.03 -1 -1 0.00 0.0179556 0.0164993 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 25.31 vpr 978.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1002300 10 10 168 178 1 65 30 11 8 88 io auto 952.3 MiB 0.34 461 351 812 66 693 53 978.8 MiB 0.06 0.00 6.74915 6.37842 -69.076 -6.37842 6.37842 1.57 0.00029439 0.0002696 0.00850165 0.00793746 -1 -1 -1 -1 18 886 33 0 0 88979.3 1011.13 0.35 0.0591083 0.0521608 11100 22242 -1 779 16 420 1590 93739 47077 6.94344 6.94344 -77.4262 -6.94344 0 0 114778. 1304.29 0.00 0.05 0.03 -1 -1 0.00 0.0176878 0.0163158 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt index 10a6cf257a..a5d1b89118 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 36.65 vpr 978.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002024 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.61 385 628 76 517 35 978.5 MiB 0.06 0.00 6.37842 -68.9926 -6.37842 6.37842 2.33 0.000579422 0.00050489 0.0121495 0.01103 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.00 0.197686 0.174013 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.07 0.08 -1 -1 0.01 0.0316604 0.0292377 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 28.63 vpr 978.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001964 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.43 356 628 86 501 41 978.5 MiB 0.06 0.00 6.32784 -69.1369 -6.32784 6.32784 1.45 0.000300815 0.000260189 0.00775385 0.00704586 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 0.78 0.12183 0.106239 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.07 0.04 -1 -1 0.01 0.0278034 0.0259211 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 22.85 vpr 979.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003236 10 10 168 178 1 65 30 11 8 88 io auto 953.2 MiB 0.34 530 354 766 109 603 54 979.7 MiB 0.05 0.00 6.8164 6.25965 -69.3407 -6.25965 6.25965 1.14 0.000312618 0.000282739 0.00833341 0.00775628 -1 -1 -1 -1 20 842 24 0 0 100248. 1139.18 0.29 0.0542354 0.0479555 11180 23751 -1 740 16 428 1793 101987 51614 6.72979 6.72979 -75.9114 -6.72979 0 0 125464. 1425.72 0.00 0.06 0.03 -1 -1 0.00 0.0175444 0.0161998 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 22.62 vpr 979.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1002860 10 10 168 178 1 65 30 11 8 88 io auto 953.2 MiB 0.34 530 359 766 97 619 50 979.4 MiB 0.05 0.00 6.8164 6.26487 -69.3105 -6.26487 6.26487 1.15 0.000296285 0.000269899 0.00803609 0.00748514 -1 -1 -1 -1 22 829 20 0 0 110609. 1256.92 0.27 0.0514332 0.0456629 11258 24748 -1 771 17 378 1439 87505 45574 6.83905 6.83905 -76.8941 -6.83905 0 0 134428. 1527.59 0.00 0.05 0.03 -1 -1 0.00 0.017841 0.0164097 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt index bee9bf5e15..0018620007 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml ex5p.blif common_--place_effort_scaling_circuit 3.66 vpr 76.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78656 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.7 MiB 2.32 6246 12245 2336 8854 1055 76.8 MiB 0.39 0.01 4.93521 -218.151 -4.93521 nan 0.22 0.00367856 0.00299064 0.169598 0.144286 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.174334 0.148491 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 3.50 vpr 76.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78400 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.21 6248 12409 2316 9051 1042 76.6 MiB 0.36 0.01 5.00015 -217.921 -5.00015 nan 0.26 0.00350625 0.00296092 0.150187 0.130251 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.154752 0.13448 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 4.86 vpr 76.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78576 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.5 MiB 1.80 6557 16051 3559 11939 553 76.7 MiB 0.46 0.01 5.39652 -231.823 -5.39652 nan 1.19 0.00333577 0.00278218 0.186781 0.161087 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.19137 0.165152 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 7.27 vpr 76.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78592 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.7 MiB 2.48 6642 53385 10847 39555 2983 76.8 MiB 0.94 0.01 5.30857 -236.309 -5.30857 nan 1.66 0.00199214 0.00171649 0.207463 0.177518 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.212761 0.182102 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml ex5p.blif common_--place_effort_scaling_circuit 1.78 vpr 74.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76676 8 63 1072 1135 0 611 133 11 11 121 clb auto 35.3 MiB 1.18 7518 6082 8947 1533 6815 599 74.9 MiB 0.13 0.00 5.94011 5.07653 -213.869 -5.07653 nan 0.08 0.00138772 0.00122352 0.0553416 0.0506401 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0575853 0.0526489 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 1.80 vpr 75.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76868 8 63 1072 1135 0 611 133 11 11 121 clb auto 35.3 MiB 1.19 7518 6142 9355 1631 7067 657 75.1 MiB 0.14 0.00 5.94011 4.97625 -208.188 -4.97625 nan 0.08 0.00139583 0.00122593 0.0595493 0.0543545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0618151 0.0563783 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 3.02 vpr 74.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76460 8 63 1072 1135 0 611 133 27 27 729 -1 auto 35.6 MiB 1.19 17047 6704 22507 6724 13850 1933 74.7 MiB 0.27 0.00 9.03576 5.62812 -248.555 -5.62812 nan 0.62 0.00135806 0.00119759 0.110142 0.0992436 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.112353 0.101219 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 3.28 vpr 74.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76464 8 63 1072 1135 0 611 133 27 27 729 -1 auto 35.3 MiB 1.19 17047 6681 64488 18508 41026 4954 74.7 MiB 0.52 0.01 9.03576 5.51074 -242.103 -5.51074 nan 0.62 0.001337 0.00117799 0.101848 0.0916873 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.104129 0.0937299 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt index 344063856f..8ba15aa9e6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_quench_slack/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.31 vpr 66.14 MiB -1 -1 0.81 26892 5 0.20 -1 -1 36924 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67732 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.05 152 432 67 335 30 66.1 MiB 0.02 0.00 2.14643 -92.8849 -2.14643 2.14643 0.04 0.000410176 0.000357432 0.00947888 0.00721552 -1 -1 -1 -1 12 196 16 646728 646728 19965.4 554.594 0.10 0.0626682 0.052856 1696 3924 -1 174 13 186 392 8874 2604 2.14935 2.14935 -96.0816 -2.14935 0 0 25971.8 721.439 0.00 0.02 0.01 -1 -1 0.00 0.0168161 0.0151469 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.31 vpr 63.81 MiB -1 -1 0.42 23048 5 0.11 -1 -1 32980 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65340 10 2 181 183 1 36 24 6 6 36 clb auto 24.4 MiB 0.02 196 151 500 122 353 25 63.8 MiB 0.01 0.00 2.24217 2.14643 -91.6412 -2.14643 2.14643 0.01 0.000252881 0.000232285 0.00475545 0.00436535 -1 -1 -1 -1 12 169 17 646728 646728 19965.4 554.594 0.05 0.0326769 0.0281977 1696 3924 -1 165 16 218 500 9678 3037 2.12594 2.12594 -92.801 -2.12594 0 0 25971.8 721.439 0.00 0.01 0.00 -1 -1 0.00 0.0097828 0.00873622 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt index a4fadd34b2..f920e62e00 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.35 vpr 62.50 MiB -1 -1 -1 -1 0 0.02 -1 -1 33168 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64000 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.3 MiB 0.00 0 3 0 0 3 62.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2148e-05 6.319e-06 7.9011e-05 5.1305e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00149016 0.00141935 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.45 vpr 62.59 MiB -1 -1 -1 -1 0 0.03 -1 -1 33140 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.3 MiB 0.00 0 3 0 0 3 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2883e-05 7.145e-06 8.5494e-05 5.1608e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00156787 0.00149125 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.37 vpr 62.62 MiB -1 -1 -1 -1 0 0.02 -1 -1 33248 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64128 6 1 1 8 0 1 8 3 3 9 -1 auto 24.3 MiB 0.00 0 21 0 11 10 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.4288e-05 8.001e-06 8.7045e-05 5.7557e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.0015153 0.00144219 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_false.blif common 0.39 vpr 62.59 MiB -1 -1 -1 -1 0 0.02 -1 -1 33208 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64096 6 1 1 8 0 1 8 3 3 9 -1 auto 24.2 MiB 0.00 0 21 0 11 10 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2682e-05 6.827e-06 7.4747e-05 4.546e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00148015 0.0014067 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and.blif common 0.37 vpr 62.59 MiB -1 -1 -1 -1 1 0.02 -1 -1 32904 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 2 1 3 4 0 3 4 3 3 9 -1 auto 24.2 MiB 0.00 9 9 5 0 4 62.6 MiB 0.00 0.00 0.443777 -0.443777 -0.443777 nan 0.00 1.5556e-05 1.071e-05 9.7598e-05 7.1292e-05 -1 -1 -1 -1 -1 6 9 3900 3900 7855.82 872.868 0.00 0.00159844 0.00147185 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.47 vpr 62.71 MiB -1 -1 -1 -1 2 0.05 -1 -1 34804 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64216 5 1 7 8 0 7 7 3 3 9 -1 auto 24.3 MiB 0.00 20 18 12 0 6 62.7 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4161e-05 1.7898e-05 0.000147057 0.000117193 -1 -1 -1 -1 -1 8 6 3900 3900 7855.82 872.868 0.00 0.00183362 0.0017084 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut2.blif common 0.53 vpr 62.71 MiB -1 -1 -1 -1 2 0.06 -1 -1 35320 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64216 5 1 7 8 0 7 7 3 3 9 -1 auto 24.3 MiB 0.00 20 18 13 0 5 62.7 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4929e-05 1.9146e-05 0.000149053 0.000119002 -1 -1 -1 -1 -1 11 12 3900 3900 7855.82 872.868 0.00 0.00207292 0.001883 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.42 vpr 62.59 MiB -1 -1 -1 -1 1 0.03 -1 -1 33204 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 3 1 5 6 1 4 5 3 3 9 -1 auto 24.2 MiB 0.00 9 12 9 0 3 62.6 MiB 0.00 0.00 0.274843 -0.536407 -0.274843 0.274843 0.00 2.0225e-05 1.4435e-05 0.000138329 0.000106209 -1 -1 -1 -1 -1 5 8 3900 3900 7855.82 872.868 0.00 0.00194055 0.00179435 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.55 vpr 62.71 MiB -1 -1 -1 -1 1 0.05 -1 -1 35156 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower 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release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62004 5 1 7 8 0 7 7 3 3 9 -1 auto 22.3 MiB 0.00 20 20 18 13 0 5 60.6 MiB 0.00 0.00 0.70303 0.70303 -0.70303 -0.70303 nan 0.00 1.2408e-05 9.012e-06 9.5712e-05 7.6811e-05 -1 -1 -1 -1 -1 11 12 3900 3900 7855.82 872.868 0.00 0.0011624 0.00104466 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.31 vpr 60.43 MiB -1 -1 -1 -1 1 0.02 -1 -1 29984 -1 -1 1 3 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61880 3 1 5 6 1 4 5 3 3 9 -1 auto 21.8 MiB 0.00 9 9 12 9 0 3 60.4 MiB 0.00 0.00 0.274843 0.274843 -0.536407 -0.274843 0.274843 0.00 1.0871e-05 7.455e-06 7.9775e-05 6.0615e-05 -1 -1 -1 -1 -1 5 8 3900 3900 7855.82 872.868 0.00 0.00105826 0.000963253 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml false_path_mux.blif common 0.41 vpr 60.79 MiB -1 -1 -1 -1 1 0.04 -1 -1 31816 -1 -1 1 3 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62252 4 1 4 6 0 4 6 3 3 9 -1 auto 22.2 MiB 0.00 12 12 15 11 0 4 60.8 MiB 0.00 0.00 0.443777 0.443777 -0.443777 -0.443777 nan 0.00 9.617e-06 6.472e-06 7.4044e-05 5.6429e-05 -1 -1 -1 -1 -1 7 16 3900 3900 7855.82 872.868 0.00 0.00111188 0.000989795 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_2x2.blif common 0.41 vpr 60.80 MiB -1 -1 -1 -1 1 0.03 -1 -1 31872 -1 -1 1 4 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62256 4 4 8 12 0 8 9 3 3 9 -1 auto 22.5 MiB 0.00 25 25 27 23 0 4 60.8 MiB 0.00 0.00 0.443777 0.443777 -1.77511 -0.443777 nan 0.00 1.7789e-05 1.3961e-05 0.000144457 0.000122941 -1 -1 -1 -1 -1 30 13 3900 3900 7855.82 872.868 0.00 0.00142643 0.00127592 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x3.blif common 0.43 vpr 60.83 MiB -1 -1 -1 -1 3 0.04 -1 -1 32352 -1 -1 3 6 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62288 6 6 28 34 0 28 15 5 5 25 clb auto 22.2 MiB 0.00 113 107 51 16 35 0 60.8 MiB 0.00 0.00 1.19848 1.19848 -5.43061 -1.19848 nan 0.00 5.1176e-05 4.5256e-05 0.000389995 0.000359124 -1 -1 -1 -1 -1 190 16 23400 11700 33739.5 1349.58 0.01 0.00307867 0.0027249 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_3x4.blif common 0.45 vpr 60.42 MiB -1 -1 -1 -1 4 0.04 -1 -1 32088 -1 -1 5 7 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61868 7 8 39 47 0 39 20 5 5 25 clb auto 22.2 MiB 0.01 182 166 236 59 163 14 60.4 MiB 0.00 0.00 1.48602 1.46514 -7.47508 -1.46514 nan 0.00 6.6986e-05 5.9065e-05 0.000927094 0.000842763 -1 -1 -1 -1 -1 326 19 23400 19500 33739.5 1349.58 0.02 0.00463562 0.00407194 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_4x4.blif common 0.45 vpr 60.44 MiB -1 -1 -1 -1 8 0.05 -1 -1 32088 -1 -1 6 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61892 8 8 51 59 0 51 22 5 5 25 clb auto 22.2 MiB 0.01 241 211 352 90 254 8 60.4 MiB 0.00 0.00 2.56944 2.55689 -12.2592 -2.55689 nan 0.00 8.6223e-05 7.824e-05 0.00144442 0.00131978 -1 -1 -1 -1 -1 432 21 23400 23400 33739.5 1349.58 0.02 0.00625144 0.0054975 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 0.55 vpr 61.31 MiB -1 -1 -1 -1 7 0.06 -1 -1 32836 -1 -1 11 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62784 10 10 95 105 0 95 31 6 6 36 clb auto 22.2 MiB 0.01 521 440 511 77 404 30 61.3 MiB 0.01 0.00 2.69967 2.57044 -18.1695 -2.57044 nan 0.00 0.000154397 0.000141824 0.00234294 0.00216319 -1 -1 -1 -1 -1 938 24 165600 42900 61410.5 1705.85 0.05 0.0107187 0.00944194 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x6.blif common 0.59 vpr 61.31 MiB -1 -1 -1 -1 8 0.07 -1 -1 32920 -1 -1 11 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62780 11 11 94 105 0 94 33 6 6 36 clb auto 22.2 MiB 0.01 523 447 709 77 581 51 61.3 MiB 0.01 0.00 2.83651 2.78731 -20.9698 -2.78731 nan 0.00 0.000148546 0.000136198 0.00283712 0.00260913 -1 -1 -1 -1 -1 978 22 165600 42900 61410.5 1705.85 0.05 0.0108376 0.00957266 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_1bit.blif common 0.40 vpr 60.80 MiB -1 -1 -1 -1 1 0.03 -1 -1 31080 -1 -1 1 3 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62256 3 2 5 7 0 5 6 3 3 9 -1 auto 22.3 MiB 0.00 15 15 15 11 0 4 60.8 MiB 0.00 0.00 0.443777 0.443777 -0.887553 -0.443777 nan 0.00 1.2549e-05 9.025e-06 9.1394e-05 7.196e-05 -1 -1 -1 -1 -1 12 16 3900 3900 7855.82 872.868 0.00 0.00121131 0.00106409 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.41 vpr 60.79 MiB -1 -1 -1 -1 2 0.03 -1 -1 31868 -1 -1 1 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62252 5 3 9 12 0 9 9 3 3 9 -1 auto 22.2 MiB 0.00 26 26 27 24 0 3 60.8 MiB 0.00 0.00 0.70303 0.70303 -1.84984 -0.70303 nan 0.00 1.6932e-05 1.3142e-05 0.000130104 0.000108733 -1 -1 -1 -1 -1 19 17 3900 3900 7855.82 872.868 0.00 0.00148166 0.00131229 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.41 vpr 60.80 MiB -1 -1 -1 -1 3 0.04 -1 -1 31860 -1 -1 1 7 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62256 7 4 13 17 0 13 12 3 3 9 -1 auto 22.2 MiB 0.00 37 37 38 34 0 4 60.8 MiB 0.00 0.00 0.962283 0.962283 -3.07137 -0.962283 nan 0.00 2.2703e-05 1.8556e-05 0.000180205 0.000158175 -1 -1 -1 -1 -1 39 18 3900 3900 7855.82 872.868 0.00 0.00176237 0.00156212 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.42 vpr 60.81 MiB -1 -1 -1 -1 4 0.04 -1 -1 31868 -1 -1 1 9 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62268 9 5 17 22 0 17 15 3 3 9 -1 auto 22.2 MiB 0.00 48 48 51 43 0 8 60.8 MiB 0.00 0.00 1.22154 1.22154 -4.55216 -1.22154 nan 0.00 2.6578e-05 2.2375e-05 0.000209206 0.000186007 -1 -1 -1 -1 -1 65 18 3900 3900 7855.82 872.868 0.00 0.00197959 0.00175044 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.43 vpr 60.79 MiB -1 -1 -1 -1 4 0.04 -1 -1 31476 -1 -1 2 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62252 11 6 24 30 0 24 19 4 4 16 clb auto 22.1 MiB 0.00 96 81 219 61 139 19 60.8 MiB 0.00 0.00 1.37337 1.3375 -6.59285 -1.3375 nan 0.00 3.6565e-05 3.094e-05 0.000520765 0.000452951 -1 -1 -1 -1 -1 131 14 7800 7800 17482.0 1092.63 0.01 0.00289277 0.0025479 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt index def1a137d2..1283c9a6ab 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.05 vpr 68.39 MiB -1 -1 0.40 21908 3 0.11 -1 -1 37048 -1 54888 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70028 99 130 344 474 1 227 298 12 12 144 clb auto 29.0 MiB 0.23 673 63978 19550 30341 14087 68.4 MiB 0.26 0.00 1.86472 -118.834 -1.86472 1.86472 0.28 0.000886976 0.000801272 0.0813306 0.0745016 -1 -1 -1 -1 38 1393 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.68 0.238994 0.21577 12522 62564 -1 1106 10 397 647 21454 6807 1.90702 1.90702 -131.595 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.03 0.05 0.11 -1 -1 0.03 0.0347348 0.0326652 0.01152 0.2117 0.0667 0.7216 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 11.51 vpr 71.63 MiB -1 -1 0.57 27156 15 0.44 -1 -1 38000 -1 56764 39 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73348 162 96 1009 950 1 701 302 16 16 256 mult_36 auto 32.3 MiB 0.47 5553 86322 27524 51152 7646 71.6 MiB 0.85 0.01 20.9417 -1607.93 -20.9417 20.9417 0.48 0.003704 0.00340296 0.38455 0.354826 -1 -1 -1 -1 50 10993 26 1.21132e+07 4.08187e+06 780512. 3048.87 3.85 1.2672 1.17071 25484 153448 -1 9617 17 3054 6060 825747 253645 22.1678 22.1678 -1734.75 -22.1678 0 0 1.00276e+06 3917.05 0.06 0.43 0.25 -1 -1 0.06 0.181388 0.170418 0.007894 0.3513 0.0164 0.6323 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.14 vpr 66.52 MiB -1 -1 0.22 18444 3 0.06 -1 -1 32164 -1 52608 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68116 99 130 344 474 1 228 298 12 12 144 clb auto 26.8 MiB 0.11 1675 704 66963 20370 32791 13802 66.5 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.00054129 0.000506587 0.0405294 0.0379774 -1 -1 -1 -1 40 1447 16 5.66058e+06 4.21279e+06 333335. 2314.82 0.33 0.156496 0.143421 12666 64609 -1 1220 8 417 630 29292 10027 2.02932 2.02932 -139.109 -2.02932 -0.436676 -0.298787 419432. 2912.72 0.01 0.03 0.05 -1 -1 0.01 0.0205549 0.0191612 0.01097 0.2173 0.06774 0.7149 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 6.66 vpr 70.39 MiB -1 -1 0.32 23820 15 0.29 -1 -1 33804 -1 54336 39 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72084 162 96 1009 950 1 701 302 16 16 256 mult_36 auto 30.9 MiB 0.19 9745 5422 92394 29404 54877 8113 70.4 MiB 0.37 0.01 23.0626 21.1445 -1627.16 -21.1445 21.1445 0.18 0.00159227 0.00147173 0.159711 0.148824 -1 -1 -1 -1 52 12275 40 1.21132e+07 4.08187e+06 805949. 3148.24 2.59 0.660632 0.611952 25992 162577 -1 9489 19 3386 7023 823162 268347 21.9567 21.9567 -1721.84 -21.9567 0 0 1.06067e+06 4143.25 0.03 0.20 0.10 -1 -1 0.03 0.0877284 0.082869 0.008009 0.3554 0.01727 0.6273 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt index 82620e5179..9748a70ef0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.71 vpr 65.87 MiB -1 -1 0.78 26896 5 0.18 -1 -1 36624 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67448 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 65.9 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.00039706 0.000346093 0.00713489 0.00637234 -1 -1 -1 -1 138 4.31250 57 1.78125 181 343 11634 2077 646728 646728 138825. 3856.24 15 3164 19284 -1 2.14648 2.14648 -94.9192 -2.14648 0 0 0.03 -1 -1 65.9 MiB 0.02 0.0245431 0.0219785 65.9 MiB -1 0.00 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.90 vpr 68.91 MiB -1 -1 0.73 26796 4 0.18 -1 -1 36100 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70560 11 2 303 283 2 78 28 7 7 49 clb auto 29.2 MiB 0.18 285 784 175 539 70 68.9 MiB 0.03 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000657098 0.000563918 0.0210266 0.0187872 -1 -1 -1 -1 313 4.34722 112 1.55556 114 177 3842 1019 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.07112 1.86791 -165.31 -2.07112 0 0 0.05 -1 -1 68.9 MiB 0.03 0.0456598 0.0418503 68.9 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml stereovision3.v common 1.14 vpr 64.27 MiB -1 -1 0.42 23428 5 0.11 -1 -1 32708 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65808 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000227241 0.000206544 0.0039717 0.00368594 -1 -1 -1 -1 136 4.12121 61 1.84848 149 320 10235 1961 646728 646728 138825. 3856.24 17 3164 19284 -1 2.10277 2.10277 -91.6521 -2.10277 0 0 0.01 -1 -1 64.3 MiB 0.01 0.0143641 0.0129398 64.3 MiB -1 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.28 vpr 66.73 MiB -1 -1 0.42 23076 4 0.11 -1 -1 32604 -1 -1 15 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68332 11 2 303 283 2 85 28 7 7 49 clb auto 27.0 MiB 0.12 462 289 1204 263 848 93 66.7 MiB 0.02 0.00 2.20327 2.04719 -154.888 -2.04719 1.90466 0.00 0.000399106 0.00035658 0.014814 0.013364 -1 -1 -1 -1 314 3.97468 124 1.56962 130 211 4049 1168 1.07788e+06 808410 219490. 4479.39 6 5100 32136 -1 2.02047 1.86775 -152.224 -2.02047 0 0 0.02 -1 -1 66.7 MiB 0.01 0.0289995 0.0266331 66.7 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt index b3939ae8ba..73c2ffd271 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 40.08 vpr 84.36 MiB -1 -1 7.36 54308 5 2.17 -1 -1 42700 -1 -1 153 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 86380 193 205 2718 2652 1 1312 556 20 20 400 memory auto 43.4 MiB 2.10 10543 233626 82676 126206 24744 84.4 MiB 2.58 0.04 4.85425 -2733.64 -4.85425 4.85425 0.83 0.0094896 0.008538 0.955143 0.814553 -1 -1 -1 -1 76 20844 34 2.07112e+07 1.09858e+07 2.02110e+06 5052.76 19.63 4.86995 4.26704 52074 423490 -1 18742 17 4982 13549 1088379 246430 5.27071 5.27071 -2903.22 -5.27071 -6.49744 -0.292146 2.51807e+06 6295.18 0.11 0.70 0.57 -1 -1 0.11 0.429237 0.387696 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 15.60 vpr 83.65 MiB -1 -1 3.61 52048 5 1.39 -1 -1 38944 -1 -1 152 193 5 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 85656 193 205 2718 2652 1 1315 555 20 20 400 memory auto 43.6 MiB 1.01 22187 10660 223995 81694 118286 24015 83.6 MiB 1.03 0.01 7.82756 5.10197 -2914.56 -5.10197 5.10197 0.32 0.00331777 0.00298858 0.368595 0.329603 -1 -1 -1 -1 76 20582 44 2.07112e+07 1.09319e+07 2.02110e+06 5052.76 5.51 1.30732 1.17135 52074 423490 -1 19292 17 5251 14325 1187541 264668 5.21056 5.21056 -3121.27 -5.21056 -9.98113 -0.359474 2.51807e+06 6295.18 0.07 0.34 0.25 -1 -1 0.07 0.194195 0.181673 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt index b2a77a6f0e..fae098c16b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.71 vpr 71.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73312 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.45 4992 14048 2664 10357 1027 71.6 MiB 0.29 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00333844 0.00278407 0.128199 0.109732 -1 -1 -1 -1 6642 14.5978 1787 3.92747 3214 12750 489499 77791 9.20055e+06 4.79657e+06 867065. 4423.80 16 18088 133656 -1 4.47188 nan -188.808 -4.47188 0 0 0.21 -1 -1 71.6 MiB 0.30 0.276888 0.244984 71.6 MiB -1 0.05 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 1.81 vpr 71.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73256 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.47 4992 14048 2664 10357 1027 71.5 MiB 0.31 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00291779 0.00252096 0.133598 0.1169 -1 -1 -1 -1 6701 14.7275 1794 3.94286 3137 12291 459530 73860 9.20055e+06 4.79657e+06 867065. 4423.80 18 18088 133656 -1 4.41143 nan -186.654 -4.41143 0 0 0.20 -1 -1 71.5 MiB 0.31 0.289515 0.258703 71.5 MiB -1 0.06 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 0.94 vpr 69.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70980 8 63 748 811 0 451 161 14 14 196 clb auto 30.3 MiB 0.24 7035 5048 13708 2494 10216 998 69.3 MiB 0.12 0.00 6.16893 4.25044 -184.802 -4.25044 nan 0.00 0.00122878 0.0010687 0.0494243 0.0443387 -1 -1 -1 -1 6826 15.1353 1836 4.07095 3768 15421 585680 92261 9.20055e+06 4.85046e+06 867065. 4423.80 21 18088 133656 -1 4.17836 nan -185.935 -4.17836 0 0 0.08 -1 -1 69.3 MiB 0.16 0.127168 0.1157 69.3 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 0.95 vpr 69.24 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70900 8 63 748 811 0 451 161 14 14 196 clb auto 30.1 MiB 0.24 7035 5048 13708 2494 10216 998 69.2 MiB 0.12 0.00 6.16893 4.25044 -184.802 -4.25044 nan 0.00 0.00119505 0.00104572 0.0492667 0.0441664 -1 -1 -1 -1 6906 15.3126 1853 4.10865 3897 16323 609528 97595 9.20055e+06 4.85046e+06 867065. 4423.80 21 18088 133656 -1 4.17947 nan -185.454 -4.17947 0 0 0.08 -1 -1 69.2 MiB 0.17 0.12902 0.117178 69.2 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt index f0bed076f0..5c9cf9fe6c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.89 vpr 71.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73344 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.50 4993 17086 3593 12286 1207 71.6 MiB 0.32 0.01 3.65588 -160.421 -3.65588 nan 0.04 0.00302942 0.00252731 0.141328 0.121812 -1 -1 -1 -1 7077 15.5538 1900 4.17582 3821 15130 1125339 197021 9.20055e+06 4.79657e+06 701736. 3580.29 19 16332 105598 -1 4.24547 nan -186.357 -4.24547 0 0 0.15 -1 -1 71.6 MiB 0.43 0.306494 0.271472 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.75 vpr 71.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73176 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.38 4933 15350 2970 11325 1055 71.5 MiB 0.31 0.01 4.27873 -192.837 -4.27873 nan 0.00 0.00317678 0.00277359 0.137596 0.118868 -1 -1 -1 -1 7099 15.6022 1898 4.17143 3600 14045 536072 90036 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.46795 nan -200.148 -4.46795 0 0 0.16 -1 -1 71.5 MiB 0.37 0.319312 0.282053 71.5 MiB -1 0.04 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 3.41 vpr 71.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73128 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.50 5048 17520 3917 12196 1407 71.4 MiB 0.28 0.01 3.77945 -168.167 -3.77945 nan 0.06 0.00517556 0.0043803 0.123856 0.107999 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.14 -1 -1 71.4 MiB 0.56 0.3503 0.312891 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.58 vpr 71.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73184 8 63 748 811 0 455 160 14 14 196 clb auto 31.7 MiB 0.45 5048 17520 3917 12196 1407 71.5 MiB 0.35 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.00283082 0.00243406 0.152931 0.13159 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.10 -1 -1 71.5 MiB 0.60 0.372321 0.328664 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.00 vpr 69.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71212 8 63 748 811 0 451 161 14 14 196 clb auto 30.5 MiB 0.24 7019 5149 19389 4557 13188 1644 69.5 MiB 0.16 0.00 5.27085 3.74489 -168.03 -3.74489 nan 0.02 0.00117698 0.00102561 0.0653639 0.0583698 -1 -1 -1 -1 7151 15.8559 1918 4.25277 4270 17535 1282134 224677 9.20055e+06 4.85046e+06 701736. 3580.29 23 16332 105598 -1 4.37015 nan -196.64 -4.37015 0 0 0.06 -1 -1 69.5 MiB 0.23 0.146259 0.132303 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 0.99 vpr 69.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71208 8 63 748 811 0 451 161 14 14 196 clb auto 30.3 MiB 0.25 7019 5029 15019 2779 11014 1226 69.5 MiB 0.13 0.00 5.64572 4.2713 -188.25 -4.2713 nan 0.00 0.00122201 0.00106187 0.0552723 0.0495083 -1 -1 -1 -1 7035 15.5987 1894 4.19956 3783 16134 598321 102284 9.20055e+06 4.85046e+06 701736. 3580.29 20 16332 105598 -1 4.48059 nan -193.333 -4.48059 0 0 0.07 -1 -1 69.5 MiB 0.19 0.141536 0.128243 69.5 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 1.77 vpr 69.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 70796 8 63 748 811 0 451 161 14 14 196 clb auto 30.1 MiB 0.24 7019 5066 19826 4740 13454 1632 69.1 MiB 0.17 0.00 5.43885 3.72182 -172.204 -3.72182 nan 0.03 0.0011932 0.0010475 0.0674743 0.0603728 -1 -1 -1 -1 7315 16.2195 1982 4.39468 4173 17201 1263136 226328 9.20055e+06 4.85046e+06 701736. 3580.29 22 16332 105598 -1 4.28324 nan -195.438 -4.28324 0 0 0.06 -1 -1 69.1 MiB 0.25 0.152566 0.137971 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.74 vpr 69.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71232 8 63 748 811 0 451 161 14 14 196 clb auto 30.5 MiB 0.24 7019 5066 19826 4740 13454 1632 69.6 MiB 0.17 0.00 5.43885 3.72182 -172.204 -3.72182 nan 0.03 0.00118286 0.00103995 0.0681588 0.0609843 -1 -1 -1 -1 7315 16.2195 1982 4.39468 4173 17201 1263136 226328 9.20055e+06 4.85046e+06 701736. 3580.29 22 16332 105598 -1 4.28324 nan -195.438 -4.28324 0 0 0.06 -1 -1 69.6 MiB 0.24 0.149333 0.134884 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt index 2e38442353..d36b97c30c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 1.81 vpr 71.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72996 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.46 5066 14916 2828 10927 1161 71.3 MiB 0.27 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00329282 0.00274638 0.115858 0.0987687 -1 -1 -1 -1 6988 15.3582 1874 4.11868 3892 16491 596262 97679 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.23403 nan -187.789 -4.23403 0 0 0.17 -1 -1 71.3 MiB 0.40 0.297064 0.262289 71.3 MiB -1 0.03 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 1.90 vpr 71.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72932 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.47 5066 14916 2828 10927 1161 71.2 MiB 0.34 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00295504 0.00249967 0.137157 0.115922 -1 -1 -1 -1 6949 15.2725 1858 4.08352 3794 15906 573229 94207 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.30087 nan -188.544 -4.30087 0 0 0.16 -1 -1 71.2 MiB 0.41 0.334676 0.294068 71.2 MiB -1 0.04 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 0.95 vpr 69.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71204 8 63 748 811 0 451 161 14 14 196 clb auto 30.1 MiB 0.24 7035 5098 13271 2309 10001 961 69.5 MiB 0.12 0.00 6.18121 4.10809 -187.168 -4.10809 nan 0.00 0.00121527 0.00106386 0.0483039 0.043454 -1 -1 -1 -1 7155 15.8647 1916 4.24834 4312 18456 674497 110334 9.20055e+06 4.85046e+06 787177. 4016.21 21 17112 118924 -1 4.03206 nan -187.889 -4.03206 0 0 0.07 -1 -1 69.5 MiB 0.18 0.126771 0.115105 69.5 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 0.92 vpr 69.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71208 8 63 748 811 0 451 161 14 14 196 clb auto 30.5 MiB 0.24 7035 5098 13271 2309 10001 961 69.5 MiB 0.12 0.00 6.18121 4.10809 -187.168 -4.10809 nan 0.00 0.00124748 0.00108677 0.0492662 0.0441845 -1 -1 -1 -1 7141 15.8337 1913 4.24168 4366 18775 685171 111801 9.20055e+06 4.85046e+06 787177. 4016.21 21 17112 118924 -1 4.03206 nan -187.889 -4.03206 0 0 0.07 -1 -1 69.5 MiB 0.18 0.12665 0.114896 69.5 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt index dda3cef9fb..2bbbe91cc9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.94 vpr 67.28 MiB -1 -1 0.14 21160 1 0.06 -1 -1 35568 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68892 6 1 16 17 2 10 9 17 17 289 -1 auto 28.8 MiB 0.03 30 162 45 109 8 67.3 MiB 0.00 0.00 1.4327 -4.13089 -1.4327 0.805 0.60 4.7388e-05 3.614e-05 0.00109694 0.000865862 -1 -1 -1 -1 20 95 2 1.34605e+07 107788 411619. 1424.29 0.37 0.00363015 0.00323679 24098 82050 -1 103 2 14 14 8045 3790 2.67718 0.805 -5.78255 -2.67718 -1.39285 -0.696976 535376. 1852.51 0.04 0.16 0.10 -1 -1 0.04 0.00205247 0.00194107 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.71 vpr 67.09 MiB -1 -1 0.11 20776 1 0.02 -1 -1 33508 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68696 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.1 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.29 2.6273e-05 2.0281e-05 0.000147698 0.000116195 -1 -1 -1 -1 20 62 1 6.63067e+06 53894 227243. 1344.63 0.21 0.00195838 0.00183532 13251 44387 -1 55 1 4 4 2060 1116 1.77078 1.77078 -1.77078 -1.77078 -0.365681 -0.365681 294987. 1745.49 0.02 0.09 0.06 -1 -1 0.02 0.00158307 0.00153637 0 4 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.80 vpr 67.12 MiB -1 -1 0.13 21160 1 0.05 -1 -1 35572 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68728 6 1 16 17 2 10 9 17 17 289 -1 auto 28.7 MiB 0.01 30 162 45 109 8 67.1 MiB 0.00 0.00 1.43377 -4.13192 -1.43377 0.805 0.60 4.8373e-05 3.7154e-05 0.00108209 0.000859607 -1 -1 -1 -1 20 96 2 1.34605e+07 107788 424167. 1467.71 0.36 0.00311589 0.00272737 24098 84646 -1 93 2 14 14 7618 3614 2.36211 0.805 -5.14799 -2.36211 -1.39063 -0.695869 547923. 1895.93 0.04 0.17 0.12 -1 -1 0.04 0.00220953 0.00209751 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.66 vpr 67.09 MiB -1 -1 0.12 20904 1 0.02 -1 -1 33532 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68696 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.1 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.23 2.2312e-05 1.624e-05 0.000140559 0.000108632 -1 -1 -1 -1 20 58 1 6.63067e+06 53894 235789. 1395.20 0.22 0.00172037 0.00159801 13251 46155 -1 59 1 4 4 2248 1144 1.92085 1.92085 -1.92085 -1.92085 -0.365681 -0.365681 303533. 1796.05 0.02 0.10 0.07 -1 -1 0.02 0.00161749 0.00156481 0 4 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 2.79 vpr 67.18 MiB -1 -1 0.14 20780 1 0.06 -1 -1 35568 -1 -1 2 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68788 6 1 16 17 2 10 9 17 17 289 -1 auto 28.9 MiB 0.02 30 162 45 109 8 67.2 MiB 0.00 0.00 1.4327 -4.13089 -1.4327 0.805 0.52 4.3023e-05 3.3348e-05 0.0010817 0.000870707 -1 -1 -1 -1 20 573 2 1.34605e+07 107788 408865. 1414.76 0.27 0.00353152 0.00316566 24098 82150 -1 581 2 13 13 6290 3262 3.57936 0.805 -7.58692 -3.57936 -3.19721 -1.59916 532630. 1843.01 0.04 0.17 0.11 -1 -1 0.04 0.00234323 0.00223031 1 9 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.63 vpr 67.17 MiB -1 -1 0.08 21164 1 0.02 -1 -1 33664 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68780 3 1 5 6 1 4 5 13 13 169 -1 auto 28.7 MiB 0.01 35 12 3 8 1 67.2 MiB 0.00 0.00 1.12186 -1.54831 -1.12186 1.12186 0.27 1.6733e-05 1.1353e-05 0.00024751 0.000102039 -1 -1 -1 -1 20 193 1 6.63067e+06 53894 225153. 1332.26 0.23 0.00204227 0.00181801 13251 44463 -1 186 1 4 4 914 327 2.39001 2.39001 -2.39001 -2.39001 -0.984912 -0.984912 292904. 1733.16 0.02 0.07 0.05 -1 -1 0.02 0.00162703 0.00157897 0 4 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.48 vpr 64.51 MiB -1 -1 0.08 17312 1 0.04 -1 -1 31744 -1 -1 2 6 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66056 6 1 16 17 2 10 9 17 17 289 -1 auto 26.0 MiB 0.01 128 30 162 45 109 8 64.5 MiB 0.00 0.00 2.32203 1.4327 -4.13089 -1.4327 0.805 0.24 2.2875e-05 1.6977e-05 0.000583372 0.000455313 -1 -1 -1 -1 20 95 2 1.34605e+07 107788 411619. 1424.29 0.15 0.00184994 0.00163236 24098 82050 -1 103 2 14 14 8045 3790 2.67718 0.805 -5.78255 -2.67718 -1.39285 -0.696976 535376. 1852.51 0.02 0.07 0.04 -1 -1 0.02 0.00125809 0.00118851 1 9 +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 0.97 vpr 65.00 MiB -1 -1 0.07 17312 1 0.02 -1 -1 30008 -1 -1 1 3 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 3 1 5 6 1 4 5 13 13 169 -1 auto 26.4 MiB 0.00 38 25 12 5 6 1 65.0 MiB 0.00 0.00 1.12186 0.96686 -1.43992 -0.96686 0.96686 0.11 2.7409e-05 7.402e-06 0.00010844 6.9333e-05 -1 -1 -1 -1 20 46 1 6.63067e+06 53894 227243. 1344.63 0.08 0.00102237 0.000928214 13251 44387 -1 49 1 4 4 2037 1117 1.60624 1.60624 -1.60624 -1.60624 -0.386566 -0.386566 294987. 1745.49 0.01 0.04 0.02 -1 -1 0.01 0.000947616 0.000912461 0 4 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.47 vpr 64.77 MiB -1 -1 0.08 17312 1 0.04 -1 -1 31592 -1 -1 2 6 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66328 6 1 16 17 2 10 9 17 17 289 -1 auto 26.5 MiB 0.01 128 30 162 45 109 8 64.8 MiB 0.00 0.00 2.32504 1.43377 -4.13192 -1.43377 0.805 0.22 2.2166e-05 1.6247e-05 0.000563065 0.00043837 -1 -1 -1 -1 20 96 2 1.34605e+07 107788 424167. 1467.71 0.15 0.00183074 0.00161762 24098 84646 -1 93 2 14 14 7618 3614 2.36211 0.805 -5.14799 -2.36211 -1.39063 -0.695869 547923. 1895.93 0.02 0.07 0.05 -1 -1 0.02 0.00125817 0.0011932 1 9 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 0.97 vpr 65.00 MiB -1 -1 0.07 17312 1 0.02 -1 -1 29988 -1 -1 1 3 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 3 1 5 6 1 4 5 13 13 169 -1 auto 26.8 MiB 0.00 38 25 12 5 6 1 65.0 MiB 0.00 0.00 1.12186 0.96686 -1.43992 -0.96686 0.96686 0.12 1.2133e-05 7.609e-06 9.0345e-05 6.733e-05 -1 -1 -1 -1 20 50 1 6.63067e+06 53894 235789. 1395.20 0.08 0.00100567 0.000934072 13251 46155 -1 48 1 4 4 2008 1087 1.59583 1.59583 -1.59583 -1.59583 -0.386566 -0.386566 303533. 1796.05 0.01 0.04 0.02 -1 -1 0.01 0.000946063 0.000910337 0 4 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/multiclock_output_and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 1.45 vpr 64.52 MiB -1 -1 0.08 17312 1 0.04 -1 -1 31588 -1 -1 2 6 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66064 6 1 16 17 2 10 9 17 17 289 -1 auto 26.3 MiB 0.01 128 30 162 45 109 8 64.5 MiB 0.00 0.00 2.32203 1.4327 -4.13089 -1.4327 0.805 0.21 2.2311e-05 1.6391e-05 0.000601358 0.000472892 -1 -1 -1 -1 20 573 2 1.34605e+07 107788 408865. 1414.76 0.15 0.00189602 0.00167591 24098 82150 -1 581 2 13 13 6290 3262 3.57936 0.805 -7.58692 -3.57936 -3.19721 -1.59916 532630. 1843.01 0.02 0.07 0.04 -1 -1 0.02 0.00127677 0.00120874 1 9 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/and_latch.v common_--target_utilization_0.01_--two_stage_clock_routing_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_routing_constraints/multi_clock_routing_constraints.xml_--clock_modeling_dedicated_network 0.98 vpr 65.00 MiB -1 -1 0.07 17312 1 0.02 -1 -1 29984 -1 -1 1 3 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66556 3 1 5 6 1 4 5 13 13 169 -1 auto 26.4 MiB 0.00 38 25 12 5 6 1 65.0 MiB 0.00 0.00 1.12186 0.96686 -1.43992 -0.96686 0.96686 0.11 1.2211e-05 7.607e-06 9.2368e-05 6.8635e-05 -1 -1 -1 -1 20 177 1 6.63067e+06 53894 225153. 1332.26 0.08 0.00101615 0.000943275 13251 44463 -1 180 1 4 4 885 322 2.22548 2.22548 -2.22548 -2.22548 -1.0058 -1.0058 292904. 1733.16 0.01 0.04 0.02 -1 -1 0.01 0.00092857 0.00089531 0 4 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt index 5c6245f2fa..996cb54058 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - slicem.xml carry_chain.blif common 0.74 vpr 59.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61260 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 21.1 MiB 0.24 70 15 4 10 1 59.8 MiB 0.00 0.00 0.532448 -5.19346 -0.532448 0.532448 0.00 0.000194851 0.000170942 0.00110293 0.00100939 -1 -1 -1 -1 27 263 12 133321 74067 -1 -1 0.15 0.0230545 0.019405 1284 5874 -1 260 8 79 79 17257 10064 1.64234 1.64234 -16.7917 -1.64234 0 0 -1 -1 0.00 0.01 0.01 -1 -1 0.00 0.0047943 0.00439499 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +slicem.xml carry_chain.blif common 0.51 vpr 57.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59044 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 18.9 MiB 0.14 70 70 15 4 10 1 57.7 MiB 0.00 0.00 0.552322 0.523836 -5.19346 -0.523836 0.523836 0.00 6.6321e-05 5.9556e-05 0.000539744 0.000502644 -1 -1 -1 -1 27 337 26 133321 74067 -1 -1 0.09 0.0136171 0.0113478 1284 5874 -1 249 10 84 84 16544 9291 1.47622 1.47622 -16.7882 -1.47622 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00280833 0.0025458 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt index bcdd78ccdb..3313254309 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml ndff.blif common 0.33 vpr 58.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60252 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 20.2 MiB 0.00 31 59 13 43 3 58.8 MiB 0.00 0.00 0.247067 -2.25231 -0.247067 0.247067 0.00 3.7056e-05 2.9732e-05 0.000307367 0.000251846 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00402393 0.00331535 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00212051 0.00200433 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml ndff.blif common 0.28 vpr 56.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58040 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 17.8 MiB 0.00 36 31 59 13 43 3 56.7 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8004e-05 1.3978e-05 0.000172543 0.000139622 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00228081 0.00193624 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00106824 0.00100971 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt index 07d413f969..3df7f1c041 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.89 vpr 69.17 MiB -1 -1 0.74 26544 4 0.19 -1 -1 36136 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70832 11 2 303 283 2 81 28 7 7 49 clb auto 29.7 MiB 0.19 337 112 35 48 29 69.2 MiB 0.02 0.00 4.0728 0 0 3.92737 0.00 0.000817884 0.000697618 0.00655739 0.00606976 -1 -1 -1 -1 398 5.30667 131 1.74667 104 164 3400 907 1.07788e+06 808410 219490. 4479.39 3 5100 32136 -1 4.15796 4.01977 0 0 -197.842 -1.707 0.05 -1 -1 69.2 MiB 0.01 0.0209255 0.0197757 69.2 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.30 vpr 66.86 MiB -1 -1 0.40 23076 4 0.10 -1 -1 32584 -1 -1 15 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68464 11 2 303 283 2 82 28 7 7 49 clb auto 27.6 MiB 0.15 424 278 994 204 585 205 66.9 MiB 0.02 0.00 4.1851 4.05951 0 0 3.91314 0.00 0.000343992 0.000313738 0.0113983 0.0105628 -1 -1 -1 -1 320 4.21053 119 1.56579 117 192 3627 1005 1.07788e+06 808410 219490. 4479.39 5 5100 32136 -1 4.18749 3.93845 0 0 -197.86 -1.707 0.02 -1 -1 66.9 MiB 0.01 0.0233894 0.0218837 66.9 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index 4625b2401f..6330616a3f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.45 vpr 65.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66728 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 21 30 5 21 4 65.2 MiB 0.00 0.00 0.814658 -2.77132 -0.814658 0.571 0.03 3.7635e-05 2.9892e-05 0.000225074 0.00018278 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.02 0.00833787 0.0081741 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00218203 0.00181006 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.44 vpr 65.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66812 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 22 30 6 14 10 65.2 MiB 0.00 0.00 0.571 0 0 0.571 0.01 3.1854e-05 2.4534e-05 0.000226572 0.000187065 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.03 0.00709054 0.0068829 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00198245 0.00170015 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.39 vpr 65.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66832 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 21 30 5 22 3 65.3 MiB 0.00 0.00 0.646297 -2.19033 -0.646297 0.571 0.01 3.5201e-05 2.6601e-05 0.00022707 0.000179701 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00304545 0.00286146 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00175316 0.00162725 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.41 vpr 65.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66952 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 21 30 7 16 7 65.4 MiB 0.00 0.00 1.6463 -5.31965 -1.6463 0.571 0.01 4.0901e-05 3.1228e-05 0.000248936 0.000196898 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00216389 0.0019624 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00684314 0.00669963 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.43 vpr 65.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66876 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 22 30 8 15 7 65.3 MiB 0.00 0.00 1.44967 -2.9103 -1.44967 0.571 0.01 3.9504e-05 2.6238e-05 0.000255838 0.000203867 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00256208 0.00226692 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.01 0.00 -1 -1 0.00 0.00410374 0.00385942 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.30 vpr 65.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66632 5 3 11 14 2 9 10 4 4 16 clb auto 26.7 MiB 0.00 21 30 5 23 2 65.1 MiB 0.00 0.00 0.146298 0 0 0.571 0.01 2.4424e-05 1.8925e-05 0.00016567 0.000135551 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.00 0.00149783 0.00138533 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00190216 0.00178073 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.33 vpr 63.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65016 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 22 21 30 5 21 4 63.5 MiB 0.00 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.00 4.1072e-05 3.6465e-05 0.000154946 0.000129413 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.00 0.00123311 0.0011324 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00106889 0.000995206 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.31 vpr 63.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65016 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 22 22 30 6 14 10 63.5 MiB 0.00 0.00 0.571 0.571 0 0 0.571 0.00 1.8581e-05 1.4484e-05 0.000138448 0.000108286 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.00124333 0.00112955 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00107454 0.00100586 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.33 vpr 63.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64632 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 22 21 30 5 22 3 63.1 MiB 0.00 0.00 0.646297 0.646297 -2.19033 -0.646297 0.571 0.00 2.5974e-05 2.1059e-05 0.000150006 0.000122181 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.00 0.00127298 0.00115176 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00110933 0.00102382 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.36 vpr 63.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65020 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 22 21 30 7 16 7 63.5 MiB 0.00 0.00 1.64604 1.6463 -5.31965 -1.6463 0.571 0.01 5.2662e-05 4.285e-05 0.00029313 0.000239707 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00164793 0.00144756 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00111256 0.00103056 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.33 vpr 62.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64412 5 3 11 14 2 9 10 4 4 16 clb auto 24.3 MiB 0.00 22 22 30 8 15 7 62.9 MiB 0.00 0.00 1.44967 1.44967 -2.9103 -1.44967 0.571 0.00 2.6758e-05 1.7748e-05 0.00016326 0.000129028 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00155856 0.00136716 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00115824 0.00106292 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.31 vpr 63.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65016 5 3 11 14 2 9 10 4 4 16 clb auto 24.9 MiB 0.00 22 21 30 5 23 2 63.5 MiB 0.00 0.00 0.146298 0.146298 0 0 0.571 0.00 2.0977e-05 1.6632e-05 0.000148014 0.000122681 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.00 0.0011576 0.00106015 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0011544 0.00107069 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index 3373ba9d87..7f185a2ecb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.57 vpr 66.20 MiB -1 -1 0.12 21572 1 0.03 -1 -1 33720 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67792 9 8 75 70 1 34 20 5 5 25 clb auto 27.2 MiB 0.67 85 398 116 276 6 66.2 MiB 0.01 0.00 2.48207 -27.4234 -2.48207 2.48207 0.03 0.000168115 0.000148552 0.00382732 0.00348451 -1 -1 -1 -1 26 186 18 151211 75605.7 37105.9 1484.24 0.07 0.0274796 0.0239744 1908 5841 -1 144 14 104 128 3783 2136 2.42625 2.42625 -32.7566 -2.42625 0 0 45067.1 1802.68 0.00 0.01 0.01 -1 -1 0.00 0.00858616 0.00782966 13 18 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.85 vpr 66.12 MiB -1 -1 0.12 21064 1 0.03 -1 -1 33420 -1 -1 2 11 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67704 11 10 108 97 1 49 23 4 4 16 clb auto 26.9 MiB 2.02 135 87 35 39 13 66.1 MiB 0.00 0.00 3.45122 -42.4992 -3.45122 3.45122 0.01 0.000185565 0.000169189 0.00161119 0.00153779 -1 -1 -1 -1 34 225 26 50403.8 50403.8 21558.4 1347.40 0.10 0.0502132 0.0405962 1020 3049 -1 158 14 151 165 4063 2532 3.88646 3.88646 -47.5118 -3.88646 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00719488 0.00664889 15 27 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 6.48 vpr 66.58 MiB -1 -1 0.14 21316 1 0.03 -1 -1 33560 -1 -1 7 13 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68180 13 12 149 129 1 68 32 6 6 36 clb auto 27.2 MiB 5.18 196 882 281 588 13 66.6 MiB 0.01 0.00 3.49758 -52.6333 -3.49758 3.49758 0.04 0.000188427 0.000167514 0.00680212 0.00627325 -1 -1 -1 -1 40 395 29 403230 176413 88484.8 2457.91 0.24 0.0901214 0.0785509 3734 16003 -1 328 14 283 356 13658 6213 3.44595 3.44595 -58.2463 -3.44595 0 0 110337. 3064.92 0.00 0.04 0.03 -1 -1 0.00 0.0323499 0.0245182 25 38 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 4.00 vpr 66.86 MiB -1 -1 0.14 21572 1 0.03 -1 -1 33512 -1 -1 7 15 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68460 15 14 196 165 1 92 36 6 6 36 clb auto 27.2 MiB 2.65 304 744 159 567 18 66.9 MiB 0.02 0.00 3.62628 -64.4645 -3.62628 3.62628 0.05 0.000406252 0.000363743 0.00800716 0.00737412 -1 -1 -1 -1 52 651 42 403230 176413 110337. 3064.92 0.29 0.109536 0.0955888 4014 20275 -1 496 16 373 551 19804 8423 3.5903 3.5903 -70.6456 -3.5903 0 0 143382. 3982.83 0.00 0.03 0.03 -1 -1 0.00 0.0200523 0.0184119 37 51 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.34 vpr 67.21 MiB -1 -1 0.16 21320 1 0.03 -1 -1 33716 -1 -1 5 17 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68824 17 16 251 206 1 119 38 5 5 25 clb auto 27.6 MiB 6.96 396 2495 611 1868 16 67.2 MiB 0.04 0.00 3.8369 -73.5721 -3.8369 3.8369 0.03 0.000487285 0.000432143 0.0227482 0.0204679 -1 -1 -1 -1 46 672 23 151211 126010 57775.2 2311.01 0.27 0.134818 0.118379 2220 9391 -1 565 21 712 1067 32893 15487 5.93712 5.93712 -106.904 -5.93712 0 0 73020.3 2920.81 0.00 0.04 0.01 -1 -1 0.00 0.0286301 0.0260985 44 66 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.49 vpr 67.34 MiB -1 -1 0.15 21572 1 0.03 -1 -1 33768 -1 -1 6 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68960 19 18 308 249 1 133 43 5 5 25 clb auto 27.8 MiB 6.09 448 2143 525 1607 11 67.3 MiB 0.04 0.00 4.70186 -94.0493 -4.70186 4.70186 0.03 0.000586405 0.000522924 0.0211391 0.0191781 -1 -1 -1 -1 46 706 50 151211 151211 57775.2 2311.01 0.36 0.18155 0.16007 2220 9391 -1 599 18 697 1112 32896 15750 4.84188 4.84188 -104.71 -4.84188 0 0 73020.3 2920.81 0.00 0.04 0.01 -1 -1 0.00 0.0301574 0.0276463 53 83 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.11 vpr 64.06 MiB -1 -1 0.07 17212 1 0.02 -1 -1 30108 -1 -1 3 9 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65600 9 8 75 70 1 34 20 5 5 25 clb auto 24.9 MiB 0.38 116 87 425 142 281 2 64.1 MiB 0.01 0.00 2.64007 2.48207 -26.067 -2.48207 2.48207 0.01 8.6946e-05 7.8624e-05 0.00221408 0.00205539 -1 -1 -1 -1 26 268 23 151211 75605.7 37105.9 1484.24 0.04 0.0152785 0.0130883 1908 5841 -1 135 7 69 74 2147 1228 2.87707 2.87707 -32.0609 -2.87707 0 0 45067.1 1802.68 0.00 0.01 0.00 -1 -1 0.00 0.00390949 0.00366369 13 18 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 2.37 vpr 64.11 MiB -1 -1 0.08 17592 1 0.02 -1 -1 29744 -1 -1 2 11 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65652 11 10 108 97 1 48 23 4 4 16 clb auto 25.2 MiB 1.61 142 127 279 85 156 38 64.1 MiB 0.01 0.00 3.45122 3.45122 -42.3331 -3.45122 3.45122 0.01 0.000117452 0.000107183 0.00222701 0.00211271 -1 -1 -1 -1 34 218 18 50403.8 50403.8 21558.4 1347.40 0.07 0.0284873 0.0241626 1020 3049 -1 142 9 139 176 4698 2930 3.29429 3.29429 -44.332 -3.29429 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.0055023 0.00511997 14 27 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 3.81 vpr 64.34 MiB -1 -1 0.08 17452 1 0.02 -1 -1 30160 -1 -1 7 13 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65884 13 12 149 129 1 68 32 6 6 36 clb auto 25.1 MiB 2.94 257 197 732 245 474 13 64.3 MiB 0.01 0.00 3.49758 3.49758 -52.6672 -3.49758 3.49758 0.02 0.000153844 0.000140711 0.00384893 0.00362558 -1 -1 -1 -1 48 388 31 403230 176413 104013. 2889.24 0.12 0.0409172 0.0351149 3910 18599 -1 284 17 330 478 14391 6422 3.69853 3.69853 -57.0037 -3.69853 0 0 131137. 3642.71 0.00 0.01 0.01 -1 -1 0.00 0.00942462 0.00855935 25 38 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.32 vpr 64.75 MiB -1 -1 0.08 17596 1 0.02 -1 -1 30132 -1 -1 6 15 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66304 15 14 196 165 1 93 35 5 5 25 clb auto 25.0 MiB 1.43 387 299 1118 289 798 31 64.8 MiB 0.01 0.00 3.70693 3.64998 -62.024 -3.64998 3.64998 0.01 0.000201154 0.000184386 0.00595593 0.00558183 -1 -1 -1 -1 38 642 42 151211 151211 48493.3 1939.73 0.14 0.0565673 0.0486639 2100 8065 -1 443 21 562 836 28073 13943 4.5307 4.5307 -77.3289 -4.5307 0 0 61632.8 2465.31 0.00 0.02 0.00 -1 -1 0.00 0.0127549 0.0115771 36 51 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 4.30 vpr 64.99 MiB -1 -1 0.08 17592 1 0.02 -1 -1 30176 -1 -1 5 17 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66552 17 16 251 206 1 120 38 5 5 25 clb auto 25.5 MiB 3.37 485 430 227 58 164 5 65.0 MiB 0.01 0.00 3.91442 3.88071 -76.4934 -3.88071 3.88071 0.01 0.000251676 0.000231158 0.00337399 0.00325376 -1 -1 -1 -1 46 639 28 151211 126010 57775.2 2311.01 0.15 0.061245 0.0528578 2220 9391 -1 566 15 540 892 27101 12502 4.50773 4.50773 -92.5696 -4.50773 0 0 73020.3 2920.81 0.00 0.02 0.01 -1 -1 0.00 0.0131363 0.0120948 45 66 -1 -1 -1 -1 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 4.69 vpr 64.82 MiB -1 -1 0.09 17976 1 0.03 -1 -1 29800 -1 -1 9 19 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66372 19 18 308 249 1 134 46 6 6 36 clb auto 25.5 MiB 3.66 628 450 3408 877 2509 22 64.8 MiB 0.03 0.00 5.19392 4.85986 -99.9643 -4.85986 4.85986 0.02 0.000290921 0.000263049 0.0149607 0.0139072 -1 -1 -1 -1 56 839 22 403230 226817 117789. 3271.93 0.17 0.0797693 0.0700776 4086 21443 -1 597 17 428 696 24582 10181 4.89622 4.89622 -97.5059 -4.89622 0 0 149557. 4154.36 0.00 0.02 0.01 -1 -1 0.00 0.0163908 0.0151108 54 83 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt index 900ba99d8f..8b30051490 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common 17.03 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60480 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.49 3.9173e-05 3.1698e-05 0.000338068 0.000271828 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00193749 0.00171766 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00201882 0.00189534 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common 4.54 vpr 56.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58132 6 7 19 26 0 19 26 3 3 9 -1 auto 17.9 MiB 0.00 51 51 216 43 63 110 56.8 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.82 2.1706e-05 1.7615e-05 0.000230011 0.000188514 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00154815 0.00141106 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.02 -1 -1 0.00 0.00103655 0.00097557 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt index 160cbfe138..b6eecf207d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles_directs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - heterogeneous_tile.xml sub_tile_directs.blif common 0.33 vpr 59.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60416 2 2 4 5 0 4 5 3 3 9 -1 auto 20.7 MiB 0.00 8 12 0 0 12 59.0 MiB 0.00 0.00 1.899 -3.798 -1.899 nan 0.03 1.7245e-05 1.217e-05 9.686e-05 7.1239e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.01 0.0017081 0.00158045 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00139703 0.00135574 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +heterogeneous_tile.xml sub_tile_directs.blif common 0.26 vpr 56.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 57760 2 2 4 5 0 4 5 3 3 9 -1 auto 18.0 MiB 0.00 8 8 12 0 0 12 56.4 MiB 0.00 0.00 1.899 1.899 -3.798 -1.899 nan 0.01 9.537e-06 6.395e-06 7.1775e-05 4.9083e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.00 0.00127254 0.0011728 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000898456 0.000864679 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt index 6303f27bd5..3607bfdb2a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.72 vpr 66.86 MiB -1 -1 0.36 22284 3 0.10 -1 -1 36712 -1 -1 19 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68460 99 73 292 365 1 173 192 8 8 64 io memory auto 27.1 MiB 0.06 704 10699 1176 8237 1286 66.9 MiB 0.06 0.00 2.09255 -114.438 -2.09255 2.09255 0.09 0.000494971 0.000445037 0.0176268 0.0158319 -1 -1 -1 -1 32 1440 34 2.23746e+06 1.57199e+06 106908. 1670.44 0.32 0.14258 0.127902 4378 18911 -1 1142 12 555 876 46439 15775 1.9226 1.9226 -129.963 -1.9226 -0.449924 -0.248875 130676. 2041.82 0.01 0.04 0.02 -1 -1 0.01 0.0280032 0.0259551 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.15 vpr 64.70 MiB -1 -1 0.21 18676 3 0.06 -1 -1 32736 -1 -1 20 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66248 99 73 292 365 1 172 193 8 8 64 io memory auto 25.0 MiB 0.04 1172 675 12447 1623 9101 1723 64.7 MiB 0.03 0.00 1.95866 1.82604 -115.206 -1.82604 1.82604 0.04 0.000458818 0.000427761 0.0122075 0.0113868 -1 -1 -1 -1 32 1268 15 2.23746e+06 1.62588e+06 106908. 1670.44 0.14 0.0656372 0.0593412 4378 18911 -1 1059 9 499 808 37153 12810 1.99391 1.99391 -128.303 -1.99391 -0.246226 -0.119866 130676. 2041.82 0.00 0.02 0.01 -1 -1 0.00 0.0125287 0.0116228 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt index 9a4d84cf16..9bcd98eb65 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml styr.blif common_--target_ext_pin_util_1 1.36 vpr 68.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70192 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.18 399 703 140 536 27 68.5 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000585274 0.000508741 0.0133922 0.0121686 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.49 0.183472 0.161021 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0299915 0.0274705 - EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.08 vpr 68.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70320 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.19 399 703 140 536 27 68.7 MiB 0.01 0.00 2.34639 -26.9899 -2.34639 2.34639 0.02 0.000329127 0.000280288 0.00811479 0.00735661 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.35 0.13039 0.113608 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0216396 0.0198831 - EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 3.83 vpr 69.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70724 10 10 168 178 1 162 111 14 14 196 clb auto 29.5 MiB 0.87 1467 5165 686 4267 212 69.1 MiB 0.06 0.00 2.95542 -36.8348 -2.95542 2.95542 0.33 0.000607935 0.000523594 0.0180811 0.0161249 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.49 0.224715 0.196946 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.03 0.07 0.10 -1 -1 0.03 0.0292402 0.0269351 - EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.85 vpr 68.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69972 10 10 168 178 1 75 33 7 7 49 clb auto 28.8 MiB 0.15 414 605 98 486 21 68.3 MiB 0.01 0.00 2.40687 -27.3475 -2.40687 2.40687 0.04 0.000340986 0.000290037 0.00724905 0.00664099 -1 -1 -1 -1 26 1062 27 1.07788e+06 700622 75813.7 1547.22 0.16 0.0618811 0.0547109 3816 13734 -1 940 18 540 1691 67850 23781 2.86939 2.86939 -35.5441 -2.86939 0 0 91376.6 1864.83 0.00 0.03 0.01 -1 -1 0.00 0.0207833 0.0191052 - EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.40 vpr 69.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70700 10 10 168 178 1 163 124 14 14 196 clb auto 29.4 MiB 0.95 1526 7540 1144 6026 370 69.0 MiB 0.04 0.00 3.12689 -38.2571 -3.12689 3.12689 0.22 0.000345985 0.000292911 0.012717 0.0113191 -1 -1 -1 -1 20 3129 15 9.20055e+06 5.60498e+06 295730. 1508.82 0.21 0.0326189 0.0295477 18004 60473 -1 3052 13 680 3211 188673 40435 3.88935 3.88935 -46.4141 -3.88935 0 0 387483. 1976.95 0.03 0.08 0.08 -1 -1 0.03 0.0265139 0.024324 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.40 vpr 68.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70232 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.6 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000587109 0.000509454 0.0135198 0.0122638 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.49 0.183086 0.160678 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0347629 0.0319856 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.32 vpr 68.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70240 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.16 399 703 140 536 27 68.6 MiB 0.03 0.00 2.34639 -26.9899 -2.34639 2.34639 0.03 0.000756907 0.000658585 0.016978 0.0153763 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.44 0.169468 0.148387 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.03477 0.0320116 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 3.38 vpr 68.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70504 10 10 168 178 1 162 111 14 14 196 clb auto 29.2 MiB 0.88 1467 5165 686 4267 212 68.9 MiB 0.04 0.00 2.95542 -36.8348 -2.95542 2.95542 0.28 0.000322881 0.000275771 0.0115436 0.0102519 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.09 0.158857 0.137775 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.02 0.05 0.05 -1 -1 0.02 0.0172724 0.0158752 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.48 vpr 68.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70176 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.5 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000502609 0.00043998 0.0125423 0.0114378 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.54 0.190745 0.166737 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.07 0.02 -1 -1 0.00 0.0474457 0.0433946 - EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.10 vpr 30.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30760 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.10 vpr 29.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30632 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.09 vpr 30.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31144 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.09 vpr 30.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31272 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml styr.blif common_--target_ext_pin_util_1 0.72 vpr 66.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67928 10 10 168 178 1 75 32 6 6 36 clb auto 26.4 MiB 0.11 467 424 582 89 470 23 66.3 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.00030999 0.00027877 0.00696272 0.00648816 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.13 0.0551714 0.048526 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0176549 0.0162302 +EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.72 vpr 66.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68432 10 10 168 178 1 75 32 6 6 36 clb auto 27.1 MiB 0.11 467 424 582 89 470 23 66.8 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000315202 0.000283212 0.00698686 0.00652035 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.13 0.0546892 0.0480996 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0177053 0.0162752 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 1.58 vpr 66.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68424 10 10 168 178 1 162 110 14 14 196 clb auto 27.5 MiB 0.46 2218 1472 5633 779 4632 222 66.8 MiB 0.03 0.00 4.05086 3.03976 -37.3505 -3.03976 3.03976 0.14 0.000303933 0.000274123 0.00890676 0.00816451 -1 -1 -1 -1 26 2737 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.28 0.0477367 0.041886 18784 74779 -1 2724 12 481 1718 95989 21869 3.66555 3.66555 -44.1461 -3.66555 0 0 467681. 2386.13 0.01 0.03 0.04 -1 -1 0.01 0.0129063 0.0118832 +EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.80 vpr 66.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68500 10 10 168 178 1 73 34 7 7 49 clb auto 27.1 MiB 0.13 556 403 749 133 594 22 66.9 MiB 0.01 0.00 2.47538 2.3678 -27.2356 -2.3678 2.3678 0.02 0.000305485 0.000280493 0.00719871 0.0067382 -1 -1 -1 -1 28 1121 29 1.07788e+06 754516 79600.7 1624.51 0.14 0.0553626 0.0488108 3864 14328 -1 1032 22 640 2278 94416 33063 2.98849 2.98849 -34.8096 -2.98849 0 0 95067.4 1940.15 0.00 0.04 0.01 -1 -1 0.00 0.0201242 0.0183344 +EArch.xml styr.blif common_--target_ext_pin_util_0.0 1.45 vpr 66.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68472 10 10 168 178 1 163 124 14 14 196 clb auto 27.5 MiB 0.44 2325 1534 6922 992 5667 263 66.9 MiB 0.03 0.00 4.16044 3.06133 -37.5377 -3.06133 3.06133 0.15 0.000313562 0.000277634 0.00955018 0.00873734 -1 -1 -1 -1 20 3156 16 9.20055e+06 5.60498e+06 295730. 1508.82 0.16 0.0255784 0.0232169 18004 60473 -1 3023 14 646 2892 171027 37325 3.649 3.649 -45.9039 -3.649 0 0 387483. 1976.95 0.01 0.04 0.03 -1 -1 0.01 0.0137843 0.0125529 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 0.72 vpr 66.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68172 10 10 168 178 1 75 32 6 6 36 clb auto 26.9 MiB 0.11 467 424 582 89 470 23 66.6 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000309727 0.000278779 0.00689436 0.0064499 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.13 0.0542428 0.0477247 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0175043 0.0160747 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 0.73 vpr 66.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68432 10 10 168 178 1 75 32 6 6 36 clb auto 27.1 MiB 0.11 467 424 582 89 470 23 66.8 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000312024 0.000279782 0.00704641 0.00657383 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.13 0.0544172 0.0478334 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0177462 0.0163156 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 1.66 vpr 66.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68328 10 10 168 178 1 162 110 14 14 196 clb auto 27.0 MiB 0.47 2218 1472 5633 779 4632 222 66.7 MiB 0.03 0.00 4.05086 3.03976 -37.3505 -3.03976 3.03976 0.15 0.000351272 0.0003209 0.00991462 0.00910112 -1 -1 -1 -1 26 2737 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.30 0.054373 0.0480166 18784 74779 -1 2724 12 481 1718 95989 21869 3.66555 3.66555 -44.1461 -3.66555 0 0 467681. 2386.13 0.01 0.03 0.06 -1 -1 0.01 0.0134871 0.0124192 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 0.71 vpr 66.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68432 10 10 168 178 1 75 32 6 6 36 clb auto 27.1 MiB 0.12 467 424 582 89 470 23 66.8 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000325311 0.000293987 0.00698168 0.0065119 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.13 0.0540172 0.0474644 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0179905 0.0165232 +EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.09 vpr 28.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28692 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.5 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.09 vpr 28.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28936 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.8 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.09 vpr 27.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28436 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.3 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.10 vpr 28.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28932 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.8 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt index b99a452bc0..16310b13cc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 8.05 vpr 75.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76868 229 197 2152 2349 1 1013 576 16 16 256 io auto 35.4 MiB 3.87 8858 177806 51921 111135 14750 75.1 MiB 1.04 0.02 2.93018 -671.396 -2.93018 2.93018 0.00 0.00614227 0.00545306 0.382618 0.335662 -1 -1 -1 -1 -1 11350 10 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.30 0.645332 0.579161 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 4.10 vpr 73.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 118 229 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 74808 229 197 2152 2349 1 1012 544 16 16 256 io auto 34.0 MiB 2.07 13816 8635 175845 51740 110676 13429 73.1 MiB 0.62 0.01 3.6187 2.93018 -676.548 -2.93018 2.93018 0.00 0.00283337 0.00251348 0.241581 0.218067 -1 -1 -1 -1 -1 11066 15 1.05632e+07 6.35949e+06 4.24953e+06 16599.7 0.17 0.380716 0.348442 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index b003134057..cd4b9b9db1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.63 vpr 68.02 MiB -1 -1 0.39 22168 3 0.11 -1 -1 36800 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69656 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.0 MiB 0.23 0.00 1.86472 -118.834 -1.86472 1.86472 0.15 0.000594963 0.000540506 0.0732034 0.0668337 -1 -1 -1 -1 38 1389 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.54 0.213559 0.195205 12522 62564 -1 1116 11 409 682 22304 6997 1.90702 1.90702 -133.281 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.08 -1 -1 0.02 0.0300207 0.027912 - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 2.86 vpr 68.12 MiB -1 -1 0.35 22168 3 0.11 -1 -1 36740 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69760 99 130 344 474 1 227 298 12 12 144 clb auto 28.7 MiB 0.20 673 63978 19550 30341 14087 68.1 MiB 0.27 0.00 1.86472 -118.834 -1.86472 1.86472 0.21 0.000644886 0.000574461 0.100184 0.0946805 -1 -1 -1 -1 38 1379 12 5.66058e+06 4.21279e+06 319130. 2216.18 0.64 0.202724 0.187418 12522 62564 -1 1115 10 390 630 21561 6939 1.90702 1.90702 -131.117 -1.90702 -1.20917 -0.320482 406292. 2821.48 0.02 0.04 0.10 -1 -1 0.02 0.021384 0.0193317 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.69 vpr 66.19 MiB -1 -1 0.21 18440 3 0.06 -1 -1 32740 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67776 99 130 344 474 1 228 298 12 12 144 clb auto 26.7 MiB 0.10 1675 704 66963 20370 32791 13802 66.2 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000563911 0.00052899 0.0409924 0.0384805 -1 -1 -1 -1 40 1453 15 5.66058e+06 4.21279e+06 333335. 2314.82 0.33 0.159628 0.146725 12666 64609 -1 1222 11 442 668 30453 10334 2.02932 2.02932 -138.236 -2.02932 -0.424985 -0.298787 419432. 2912.72 0.01 0.02 0.04 -1 -1 0.01 0.0182049 0.0170605 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_--router_algorithm_parallel_--num_workers_4 1.64 vpr 66.09 MiB -1 -1 0.22 18828 3 0.06 -1 -1 32664 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67680 99 130 344 474 1 228 298 12 12 144 clb auto 26.7 MiB 0.11 1675 704 66963 20370 32791 13802 66.1 MiB 0.11 0.00 2.18241 1.84343 -121.838 -1.84343 1.84343 0.09 0.000578968 0.000534423 0.0412337 0.0383096 -1 -1 -1 -1 40 1452 13 5.66058e+06 4.21279e+06 333335. 2314.82 0.30 0.125939 0.112662 12666 64609 -1 1250 11 460 694 31414 10385 2.02932 2.02932 -140.547 -2.02932 -0.436676 -0.298787 419432. 2912.72 0.01 0.02 0.04 -1 -1 0.01 0.0159037 0.0142142 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt index 7b4fc76c6e..54c448ed2b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_fail/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.55 vpr 67.97 MiB -1 -1 0.42 22420 3 0.14 -1 -1 36800 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69600 99 130 344 474 1 225 298 12 12 144 clb auto 28.5 MiB 0.19 695 57013 16754 28454 11805 68.0 MiB 0.25 0.00 1.84453 -73.0907 -1.84453 1.84453 0.29 0.000572985 0.000494317 0.0593261 0.049655 -1 -1 -1 -1 32 1551 10 5.66058e+06 4.21279e+06 281316. 1953.58 1.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 1.27 vpr 65.80 MiB -1 -1 0.22 18440 3 0.06 -1 -1 32700 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67384 99 130 344 474 1 224 298 12 12 144 clb auto 26.0 MiB 0.09 1590 710 59003 16103 31150 11750 65.8 MiB 0.08 0.00 2.39882 1.86362 -71.5534 -1.86362 1.86362 0.09 0.000324437 0.000299051 0.0213263 0.0197158 -1 -1 -1 -1 30 1493 8 5.66058e+06 4.21279e+06 267238. 1855.82 0.25 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt index 50b6703de2..6c8edb7769 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_no_fail/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 3.13 vpr 67.88 MiB -1 -1 0.41 22284 3 0.13 -1 -1 36924 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69508 99 130 344 474 1 218 298 12 12 144 clb auto 28.4 MiB 0.23 632 70943 19608 36161 15174 67.9 MiB 0.23 0.00 2.24009 0 0 2.24009 0.25 0.000717536 0.00062496 0.0508972 0.0435443 -1 -1 -1 -1 32 1480 8 5.66058e+06 4.21279e+06 281316. 1953.58 0.55 0.227253 0.196073 11950 52952 -1 1327 7 304 419 24960 8371 2.42926 2.42926 0 0 0 0 345702. 2400.71 0.03 0.05 0.08 -1 -1 0.03 0.020098 0.0186968 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 1.52 vpr 65.95 MiB -1 -1 0.21 18444 3 0.07 -1 -1 32700 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67528 99 130 344 474 1 220 298 12 12 144 clb auto 26.1 MiB 0.08 1597 670 73928 20988 37298 15642 65.9 MiB 0.10 0.00 2.12094 1.86992 0 0 1.86992 0.09 0.000346553 0.000320307 0.0265137 0.0244879 -1 -1 -1 -1 32 1510 10 5.66058e+06 4.21279e+06 281316. 1953.58 0.24 0.115418 0.0996332 11950 52952 -1 1387 6 289 390 22972 7530 2.02363 2.02363 0 0 0 0 345702. 2400.71 0.01 0.01 0.03 -1 -1 0.01 0.00812432 0.00746999 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index a5bee94784..e0f3adaef2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.50 vpr 67.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68660 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.6443e-05 3.2529e-05 0.000274786 0.000214986 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00211509 0.0019009 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.0017763 0.00169895 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.49 vpr 67.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 5 3 11 14 2 9 10 4 4 16 clb auto 28.8 MiB 0.01 21 30 9 19 2 67.1 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.8016e-05 3.4218e-05 0.000283686 0.000224427 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0022472 0.00206472 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00179634 0.00171755 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.51 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68932 5 3 11 14 2 9 10 4 4 16 clb auto 28.9 MiB 0.01 21 30 9 19 2 67.3 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 6.2523e-05 4.6425e-05 0.000366128 0.000294026 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00236124 0.00216436 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00189537 0.00181322 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.37 vpr 65.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66960 5 3 11 14 2 9 10 4 4 16 clb auto 26.6 MiB 0.00 24 21 30 9 19 2 65.4 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.01 2.8133e-05 1.9232e-05 0.000189523 0.000148581 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0012838 0.00114571 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00106319 0.00101088 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.38 vpr 64.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66332 5 3 11 14 2 9 10 4 4 16 clb auto 26.1 MiB 0.00 24 21 30 9 19 2 64.8 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.3037e-05 1.6002e-05 0.000161301 0.000128215 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00119792 0.00109242 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00104058 0.000989976 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.38 vpr 64.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66400 5 3 11 14 2 9 10 4 4 16 clb auto 26.6 MiB 0.00 24 21 30 9 19 2 64.8 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.3958e-05 1.6675e-05 0.000165922 0.000130845 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00122522 0.0011164 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00108427 0.00103245 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt index db634e1dc0..7ba7023d3b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.81 vpr 69.01 MiB -1 -1 0.66 26668 4 0.21 -1 -1 35972 -1 -1 15 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70664 11 2 303 283 2 78 28 7 7 49 clb auto 29.4 MiB 0.25 285 784 175 539 70 69.0 MiB 0.04 0.00 2.03811 -163.686 -2.03811 1.90043 0.00 0.000759025 0.000652417 0.0254764 0.023241 -1 -1 -1 -1 -1 313 6 1.07788e+06 808410 219490. 4479.39 0.03 0.050656 0.046841 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.83 vpr 66.55 MiB -1 -1 0.41 22688 4 0.10 -1 -1 32604 -1 -1 15 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68148 11 2 303 283 2 85 28 7 7 49 clb auto 26.8 MiB 0.13 462 289 1204 263 848 93 66.6 MiB 0.02 0.00 2.20327 2.04719 -154.888 -2.04719 1.90466 0.00 0.000393487 0.00035083 0.0145974 0.0131537 -1 -1 -1 -1 -1 314 6 1.07788e+06 808410 219490. 4479.39 0.01 0.02878 0.0264373 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt index e65df342f6..28cd1e20a3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.06 vpr 65.94 MiB -1 -1 0.49 27024 5 0.12 -1 -1 36972 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67520 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 152 432 67 335 30 65.9 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000242517 0.000210755 0.00440565 0.00392683 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.0164282 0.0146736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.57 vpr 66.14 MiB -1 -1 0.70 27020 5 0.18 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67732 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.1 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000439525 0.000384869 0.00748551 0.00667971 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.02 0.0256815 0.0230005 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.67 vpr 66.16 MiB -1 -1 0.82 27152 5 0.18 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67748 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.04 152 432 67 335 30 66.2 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 3.5959e-05 2.737e-05 0.00308117 0.00275747 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.0135928 0.0105523 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.25 vpr 66.16 MiB -1 -1 0.65 27036 5 0.12 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67748 10 2 181 183 1 35 24 6 6 36 clb auto 27.0 MiB 0.03 152 432 67 335 30 66.2 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.000221863 9.7941e-05 0.00222519 0.00187901 -1 -1 -1 -1 -1 138 15 646728 646728 138825. 3856.24 0.01 0.00928043 0.00694563 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 1.74 vpr 66.05 MiB -1 -1 0.84 26784 5 0.18 -1 -1 36840 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67632 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.04 152 432 67 335 30 66.0 MiB 0.01 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 5.1198e-05 3.2395e-05 0.002938 0.00248994 -1 -1 -1 -1 -1 137 16 646728 646728 138825. 3856.24 0.02 0.0136494 0.00987341 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 2.01 vpr 66.03 MiB -1 -1 0.85 27040 5 0.19 -1 -1 36968 -1 -1 12 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67616 10 2 181 183 1 35 24 6 6 36 clb auto 26.9 MiB 0.05 152 432 67 335 30 66.0 MiB 0.03 0.00 2.14835 -93.0339 -2.14835 2.14835 0.00 0.00150082 0.00142957 0.0169996 0.0159511 -1 -1 -1 -1 -1 137 16 646728 646728 138825. 3856.24 0.07 0.0553928 0.0438556 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.08 vpr 63.77 MiB -1 -1 0.42 23428 5 0.11 -1 -1 32568 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65300 10 2 181 183 1 36 24 6 6 36 clb auto 24.3 MiB 0.02 196 160 398 88 284 26 63.8 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000227615 0.000207264 0.00397095 0.00368331 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.01 0.0142366 0.0128073 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.10 vpr 64.31 MiB -1 -1 0.42 23432 5 0.11 -1 -1 32820 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65856 10 2 181 183 1 36 24 6 6 36 clb auto 24.7 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000220437 0.000200683 0.00388697 0.00360563 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.01 0.0140084 0.0126067 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.08 vpr 64.30 MiB -1 -1 0.41 23432 5 0.11 -1 -1 32576 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 2.0946e-05 1.5451e-05 0.00144 0.00130782 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.01 0.00714942 0.00533206 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.10 vpr 64.30 MiB -1 -1 0.42 23268 5 0.11 -1 -1 32624 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65840 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 64.3 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000128737 3.4773e-05 0.00157388 0.00135559 -1 -1 -1 -1 -1 136 17 646728 646728 138825. 3856.24 0.01 0.00734362 0.00545723 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--router_algorithm_parallel_--num_workers_4 1.13 vpr 63.82 MiB -1 -1 0.48 23412 5 0.11 -1 -1 32624 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65348 10 2 181 183 1 36 24 6 6 36 clb auto 24.4 MiB 0.02 196 160 398 88 284 26 63.8 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 2.8821e-05 1.6162e-05 0.00152895 0.00131578 -1 -1 -1 -1 -1 146 18 646728 646728 138825. 3856.24 0.01 0.00771689 0.00542962 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full_--router_algorithm_parallel_--num_workers_4 1.08 vpr 63.91 MiB -1 -1 0.41 23412 5 0.11 -1 -1 32592 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65448 10 2 181 183 1 36 24 6 6 36 clb auto 24.9 MiB 0.02 196 160 398 88 284 26 63.9 MiB 0.01 0.00 2.24505 2.14835 -91.9072 -2.14835 2.14835 0.00 0.000391445 0.000369569 0.00604011 0.00564745 -1 -1 -1 -1 -1 146 18 646728 646728 138825. 3856.24 0.02 0.0189758 0.0170555 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt index e84a112970..2f2a8563aa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 66.79 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1215864 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1063.3 MiB 15.63 75097 245792 47628 188491 9673 1158.7 MiB 16.87 0.21 4.99421 -5497.03 -3.99421 2.87584 0.01 0.0552629 0.0482483 4.22516 3.43532 87123 7.00515 21186 1.70347 25964 36365 9630576 1720385 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.30154 2.77187 -5700.98 -4.30154 0 0 5.27 -1 -1 1158.7 MiB 5.35 6.14131 5.12726 1158.7 MiB -1 3.33 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 34.85 vpr 1.16 GiB 42 749 0 0 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1214712 13 29 26295 20086 1 12646 791 39 29 1131 LAB auto 1077.2 MiB 7.88 231619 75107 234775 43541 180854 10380 1154.3 MiB 6.22 0.08 5.55061 5.16398 -5504.03 -4.16398 2.86102 0.01 0.024999 0.0221456 1.93536 1.57413 87307 6.90501 21230 1.67906 25811 34329 9106433 1637889 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.36451 2.98815 -5707.14 -4.36451 0 0 3.45 -1 -1 1154.3 MiB 2.66 3.0208 2.53258 1154.3 MiB -1 1.14 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt index 7d3888ea0e..71dadae60a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan_s10/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratix10_arch.timing.xml murax_stratix10_arch_timing.blif common 19.43 vpr 384.88 MiB 35 93 0 0 8 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 394112 18 17 2338 2195 1 2035 136 17 13 221 io_cell auto 342.6 MiB 9.23 11597 14096 2127 10583 1386 384.9 MiB 0.99 0.03 3.78594 -3334.96 -2.78594 3.78594 0.00 0.0127693 0.0106573 0.428449 0.35312 12754 6.27657 3971 1.95423 6857 16497 4298918 925978 0 0 3.37726e+06 15281.7 12 52540 541133 -1 3.215 3.215 -2910.24 -2.215 0 0 1.33 -1 -1 384.9 MiB 1.91 0.811838 0.706005 384.9 MiB -1 0.27 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_MLAB num_DSP num_M20K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratix10_arch.timing.xml murax_stratix10_arch_timing.blif common 9.53 vpr 382.42 MiB 35 86 0 0 8 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 391600 18 17 2338 2195 1 2026 129 17 13 221 io_cell auto 343.8 MiB 4.50 19688 12064 13129 2012 9707 1410 382.4 MiB 0.43 0.01 4.85192 3.71062 -3391.61 -2.71062 3.71062 0.00 0.0034117 0.00282109 0.180285 0.153335 13833 6.83786 4143 2.04795 6992 16873 4273349 902603 0 0 3.37726e+06 15281.7 13 52540 541133 -1 3.321 3.321 -2993.48 -2.321 0 0 0.58 -1 -1 382.4 MiB 0.89 0.365548 0.32446 382.4 MiB -1 0.14 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt index 6ff0e8d886..9dfb53011a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 22.01 vpr 69.98 MiB -1 -1 0.42 25672 5 0.18 -1 -1 37676 -1 -1 17 66 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 71656 66 96 983 697 1 557 191 16 16 256 mult_27 auto 30.8 MiB 2.52 4520 41915 13784 24449 3682 70.0 MiB 0.47 0.01 16.7771 -983.813 -16.7771 16.7771 0.51 0.00380097 0.00356084 0.223806 0.20783 -1 -1 -1 -1 82 9891 30 4.83877e+06 1.03328e+06 1.63760e+06 6396.87 14.79 1.72784 1.60303 43164 348864 -1 8812 16 2703 5592 1100371 345017 16.7238 16.7238 -1023.47 -16.7238 0 0 2.03272e+06 7940.32 0.12 0.37 0.48 -1 -1 0.12 0.123499 0.117943 138 202 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 6.18 vpr 68.13 MiB -1 -1 0.22 21632 5 0.11 -1 -1 33776 -1 -1 17 66 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69764 66 96 983 697 1 561 191 16 16 256 mult_27 auto 29.3 MiB 0.64 8149 4596 38072 11997 23544 2531 68.1 MiB 0.22 0.00 19.4757 17.0827 -970.661 -17.0827 17.0827 0.23 0.0013349 0.00123315 0.101262 0.0948777 -1 -1 -1 -1 62 12202 30 4.83877e+06 1.03328e+06 1.31386e+06 5132.27 3.21 0.426439 0.394076 39852 267778 -1 9854 19 3552 7322 1583377 471194 17.0705 17.0705 -1067.68 -17.0705 0 0 1.60318e+06 6262.42 0.04 0.26 0.14 -1 -1 0.04 0.0706049 0.0667194 140 202 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt index 8a9769fe6b..ba994c938b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.48 vpr 65.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66896 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.3 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000116029 0.000100823 0.0010942 0.00101432 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.3 MiB 0.01 0.00766251 0.00688033 65.3 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.51 vpr 65.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66796 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000165834 0.000146968 0.00119076 0.00110326 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.2 MiB 0.01 0.00909464 0.00816836 65.2 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.24 vpr 65.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66872 6 8 39 47 1 20 17 5 5 25 clb auto 27.0 MiB 0.02 88 59 31 28 0 65.3 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000113726 9.7512e-05 0.00114825 0.00106423 -1 -1 -1 -1 -1 -1 -1 -1 654 1027 31303 15229 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 65.3 MiB 0.03 -1 -1 65.3 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.24 vpr 65.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66624 6 8 39 47 1 20 17 5 5 25 clb auto 26.8 MiB 0.02 88 59 31 28 0 65.1 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.00013832 0.000115541 0.000955845 0.00087775 -1 -1 -1 -1 142 7.47368 66 3.47368 654 1027 31303 15229 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9824 -1.84852 0 0 0.00 -1 -1 65.1 MiB 0.03 -1 -1 65.1 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.17 vpr 63.55 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65076 6 8 39 47 1 20 17 5 5 25 clb auto 24.9 MiB 0.01 107 88 59 31 28 0 63.6 MiB 0.00 0.00 1.35996 1.35996 -15.7932 -1.35996 1.35996 0.00 8.0158e-05 7.1688e-05 0.000706955 0.000665607 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5199 2021 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 63.6 MiB 0.01 0.00502158 0.00446199 63.6 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.18 vpr 63.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64692 6 8 39 47 1 20 17 5 5 25 clb auto 24.9 MiB 0.01 107 88 59 31 28 0 63.2 MiB 0.00 0.00 1.35996 1.35996 -15.7932 -1.35996 1.35996 0.00 8.5185e-05 7.6654e-05 0.000714704 0.000671672 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5199 2021 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 63.2 MiB 0.01 0.00499041 0.00445636 63.2 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.19 vpr 62.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64488 6 8 39 47 1 20 17 5 5 25 clb auto 24.7 MiB 0.01 107 88 59 31 28 0 63.0 MiB 0.00 0.00 1.36028 1.36028 -15.8 -1.36028 1.36028 0.00 8.0659e-05 7.1984e-05 0.000736297 0.000693377 -1 -1 -1 -1 -1 -1 -1 -1 656 1029 31338 15241 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 63.0 MiB 0.02 -1 -1 63.0 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.19 vpr 63.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64600 6 8 39 47 1 20 17 5 5 25 clb auto 24.3 MiB 0.01 107 88 59 31 28 0 63.1 MiB 0.00 0.00 1.36028 1.36028 -15.8 -1.36028 1.36028 0.00 8.1281e-05 7.241e-05 0.000726072 0.000683087 -1 -1 -1 -1 141 7.42105 65 3.42105 656 1029 31338 15241 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9119 -1.84852 0 0 0.00 -1 -1 63.1 MiB 0.02 -1 -1 63.1 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt index cb597e0042..b2ba415601 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.77 vpr 60.00 MiB -1 -1 0.91 26856 6 0.21 -1 -1 36836 -1 -1 28 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61436 10 2 186 188 1 48 40 8 8 64 clb auto 20.5 MiB 0.04 230 992 145 785 62 60.0 MiB 0.03 0.00 2.71052 -113.21 -2.71052 2.71052 0.00 0.000447321 0.000382714 0.00843147 0.00745792 -1 -1 -1 -1 199 4.42222 199 4.42222 158 387 13661 2934 80255.5 62421 276194. 4315.53 9 9480 40228 -1 2.65254 2.65254 -117.366 -2.65254 -0.0734 -0.0734 0.09 -1 -1 60.0 MiB 0.03 0.0220189 0.0194464 60.0 MiB -1 0.01 - k6_frac_N10_40nm.xml stereovision3.v common 2.04 vpr 61.65 MiB -1 -1 0.81 26884 5 0.16 -1 -1 36968 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63132 10 2 181 183 1 37 19 5 5 25 clb auto 22.0 MiB 0.07 127 144 32 99 13 61.7 MiB 0.01 0.00 2.03188 -84.9427 -2.03188 2.03188 0.00 0.000403252 0.000354056 0.00494195 0.00440924 -1 -1 -1 -1 107 3.14706 52 1.52941 43 59 1032 320 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97747 1.97747 -86.276 -1.97747 0 0 0.03 -1 -1 61.7 MiB 0.01 0.0168116 0.0156639 61.7 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_90nm.xml stereovision3.v common 1.38 vpr 57.91 MiB -1 -1 0.41 23268 6 0.10 -1 -1 32560 -1 -1 28 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59296 10 2 186 188 1 46 40 8 8 64 clb auto 18.0 MiB 0.02 370 219 1196 185 951 60 57.9 MiB 0.01 0.00 3.46426 2.64808 -111.051 -2.64808 2.64808 0.00 0.00022725 0.000207091 0.00499837 0.00456403 -1 -1 -1 -1 190 4.41860 190 4.41860 181 461 16985 3541 80255.5 62421 276194. 4315.53 13 9480 40228 -1 2.65254 2.65254 -110.961 -2.65254 -0.0734 -0.0734 0.03 -1 -1 57.9 MiB 0.01 0.0132785 0.0119286 57.9 MiB -1 0.00 +k6_frac_N10_40nm.xml stereovision3.v common 1.33 vpr 59.37 MiB -1 -1 0.40 23292 5 0.11 -1 -1 32592 -1 -1 7 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60792 10 2 181 183 1 38 19 5 5 25 clb auto 19.9 MiB 0.04 159 121 469 107 323 39 59.4 MiB 0.01 0.00 2.03188 2.03188 -84.6958 -2.03188 2.03188 0.00 0.000224585 0.000205104 0.00727533 0.00683626 -1 -1 -1 -1 105 3.00000 54 1.54286 61 90 1611 507 485046 377258 99699.4 3987.98 6 2523 14238 -1 2.07226 2.07226 -86.1872 -2.07226 0 0 0.01 -1 -1 59.4 MiB 0.01 0.0155457 0.0145868 59.4 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt index 0fde75bd1e..eb1b56df78 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.09 vpr 60.07 MiB -1 -1 0.81 26980 6 0.15 -1 -1 36756 -1 -1 28 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61512 10 2 186 188 1 48 40 8 8 64 clb auto 20.6 MiB 0.03 230 992 145 785 62 60.1 MiB 0.02 0.00 2.71052 -113.21 -2.71052 2.71052 0.00 0.000430706 0.00037483 0.00785446 0.00688801 -1 -1 -1 -1 199 4.42222 199 4.42222 158 387 13661 2934 80255.5 62421 276194. 4315.53 9 9480 40228 -1 2.65254 2.65254 -117.366 -2.65254 -0.0734 -0.0734 0.08 -1 -1 60.1 MiB 0.02 0.0211284 0.0188358 60.1 MiB -1 0.01 - k6_frac_N10_40nm.xml stereovision3.v common 1.94 vpr 61.65 MiB -1 -1 0.77 26880 5 0.18 -1 -1 36968 -1 -1 7 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63132 10 2 181 183 1 37 19 5 5 25 clb auto 22.1 MiB 0.06 127 144 32 99 13 61.7 MiB 0.01 0.00 2.03188 -84.9427 -2.03188 2.03188 0.00 0.000420371 0.000366917 0.00494209 0.00453968 -1 -1 -1 -1 107 3.14706 52 1.52941 43 59 1032 320 485046 377258 99699.4 3987.98 3 2523 14238 -1 1.97747 1.97747 -86.276 -1.97747 0 0 0.02 -1 -1 61.7 MiB 0.01 0.0164382 0.0153894 61.7 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_90nm.xml stereovision3.v common 1.27 vpr 57.61 MiB -1 -1 0.40 23264 6 0.10 -1 -1 32568 -1 -1 28 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58996 10 2 186 188 1 46 40 8 8 64 clb auto 18.0 MiB 0.01 370 219 1196 185 951 60 57.6 MiB 0.01 0.00 3.46426 2.64808 -111.051 -2.64808 2.64808 0.00 0.000222621 0.000202989 0.0049341 0.00450901 -1 -1 -1 -1 190 4.41860 190 4.41860 181 461 16985 3541 80255.5 62421 276194. 4315.53 13 9480 40228 -1 2.65254 2.65254 -110.961 -2.65254 -0.0734 -0.0734 0.03 -1 -1 57.6 MiB 0.01 0.0129377 0.0116096 57.6 MiB -1 0.00 +k6_frac_N10_40nm.xml stereovision3.v common 1.26 vpr 59.36 MiB -1 -1 0.40 23292 5 0.11 -1 -1 32584 -1 -1 7 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60788 10 2 181 183 1 38 19 5 5 25 clb auto 19.5 MiB 0.03 159 121 469 107 323 39 59.4 MiB 0.01 0.00 2.03188 2.03188 -84.6958 -2.03188 2.03188 0.00 0.000224474 0.000205035 0.00586463 0.00545401 -1 -1 -1 -1 105 3.00000 54 1.54286 61 90 1611 507 485046 377258 99699.4 3987.98 6 2523 14238 -1 2.07226 2.07226 -86.1872 -2.07226 0 0 0.01 -1 -1 59.4 MiB 0.01 0.0136329 0.0127204 59.4 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt index 9a8744d436..d2d1f8f443 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml styr.blif common 32.55 vpr 978.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001924 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.50 371 490 69 397 24 978.4 MiB 0.08 0.00 6.66046 -72.2933 -6.66046 6.66046 0.00 0.000745164 0.00064564 0.0121362 0.0109717 -1 -1 -1 -1 549 8.19403 169 2.52239 264 964 62268 28521 0 0 194014. 2204.70 13 11730 32605 -1 6.70864 6.70864 -73.3171 -6.70864 0 0 0.08 -1 -1 978.4 MiB 0.14 0.0524157 0.0489871 978.4 MiB -1 0.02 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml styr.blif common 21.89 vpr 979.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1002988 10 10 168 178 1 65 30 11 8 88 io auto 953.4 MiB 0.34 530 402 720 97 571 52 979.5 MiB 0.06 0.00 6.8225 6.61671 -72.4654 -6.61671 6.61671 0.00 0.000317958 0.000284786 0.00836011 0.00777644 -1 -1 -1 -1 669 10.4531 198 3.09375 255 965 67200 31259 0 0 194014. 2204.70 14 11730 32605 -1 6.73871 6.73871 -74.3689 -6.73871 0 0 0.04 -1 -1 979.5 MiB 0.05 0.0253452 0.0235373 979.5 MiB -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt index 7b5437463d..f221a6579e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 5.51 vpr 77.59 MiB 0.04 8576 -1 -1 1 0.07 -1 -1 35240 -1 -1 12 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79456 130 40 596 562 1 356 185 14 14 196 dsp_top auto 38.5 MiB 0.13 1890 35427 11493 18934 5000 77.6 MiB 0.27 0.00 5.12303 -647.058 -5.12303 5.12303 0.48 0.00206617 0.00189672 0.14394 0.133207 -1 -1 -1 -1 64 3873 16 4.93594e+06 1.0962e+06 976140. 4980.31 2.20 0.636996 0.595296 31408 195022 -1 3500 9 851 887 209984 82943 4.57723 4.57723 -694.457 -4.57723 0 0 1.23909e+06 6321.90 0.09 0.15 0.39 -1 -1 0.09 0.0903946 0.0866517 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 7.78 odin 122.62 MiB 4.61 125568 -1 -1 1 0.05 -1 -1 31928 -1 -1 12 130 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77960 130 40 596 562 1 355 185 14 14 196 dsp_top auto 37.4 MiB 0.09 3418 1865 39635 13944 21044 4647 76.1 MiB 0.12 0.00 5.12303 5.12303 -651.76 -5.12303 5.12303 0.26 0.000839334 0.000783096 0.0678992 0.0634122 -1 -1 -1 -1 82 3469 9 4.93594e+06 1.0962e+06 1.23902e+06 6321.54 1.21 0.310392 0.286691 33448 250998 -1 3353 9 741 768 180939 69062 4.57723 4.57723 -669.54 -4.57723 0 0 1.53308e+06 7821.82 0.04 0.05 0.19 -1 -1 0.04 0.0252324 0.0238661 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt index 23cf7b0b85..2f01890b2c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 14.85 vpr 81.40 MiB 0.10 11392 -1 -1 1 0.12 -1 -1 37676 -1 -1 23 130 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 83352 130 40 1203 1030 1 586 196 14 14 196 dsp_top auto 41.3 MiB 0.63 2691 46285 14724 25599 5962 81.4 MiB 0.45 0.01 6.58999 -703.566 -6.58999 6.58999 0.48 0.00220042 0.00200207 0.214554 0.193316 -1 -1 -1 -1 108 5210 35 4.93594e+06 1.40315e+06 1.55765e+06 7947.21 10.07 1.93637 1.74105 36552 325092 -1 4641 23 2669 2746 326887 113256 6.77766 6.77766 -770.287 -6.77766 0 0 1.93951e+06 9895.46 0.12 0.27 0.65 -1 -1 0.12 0.138318 0.125698 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml test.v common 10.83 odin 217.88 MiB 6.37 223104 -1 -1 1 0.07 -1 -1 33996 -1 -1 23 130 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 81872 130 40 1203 1030 1 587 196 14 14 196 dsp_top auto 40.4 MiB 0.31 5039 2615 41733 12907 23223 5603 80.0 MiB 0.16 0.00 7.16349 6.55057 -693.511 -6.55057 6.55057 0.19 0.000991493 0.00090394 0.082402 0.0754617 -1 -1 -1 -1 120 4838 28 4.93594e+06 1.40315e+06 1.69991e+06 8673.00 1.92 0.399102 0.358269 38028 369366 -1 4452 23 2538 2614 296097 92461 6.77726 6.77726 -734.869 -6.77726 0 0 2.14988e+06 10968.8 0.04 0.10 0.28 -1 -1 0.04 0.0610235 0.0563769 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt index 235e1da010..0d6f5758ca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.88 vpr 72.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74068 130 150 1169 1319 1 886 363 12 12 144 clb auto 32.4 MiB 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00708147 0.00640458 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 2.22 vpr 72.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 130 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73804 130 150 1216 1366 1 933 370 12 12 144 clb auto 32.3 MiB 1.54 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00920908 0.00830291 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.00 vpr 71.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 130 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72864 130 150 1169 1319 1 885 365 12 12 144 clb auto 31.3 MiB 0.63 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00292909 0.00271156 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 0.99 vpr 70.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 94 130 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71752 130 150 1216 1366 1 925 374 12 12 144 clb auto 30.4 MiB 0.64 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00290828 0.00268481 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt index d3c7d61af8..76c0f05c90 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.36 vpr 66.46 MiB 0.08 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68060 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.08 425 2283 406 1804 73 66.5 MiB 0.05 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000768694 0.000638603 0.0252644 0.022728 -1 -1 -1 -1 414 4.35789 166 1.74737 630 1427 58282 13907 1.07788e+06 1.02399e+06 207176. 4228.08 20 4440 29880 -1 2.3823 2.2863 -180.577 -2.3823 0 0 0.05 -1 -1 66.5 MiB 0.08 0.0775573 0.0705898 66.5 MiB -1 0.01 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.76 vpr 69.14 MiB 0.09 10368 -1 -1 5 0.19 -1 -1 36576 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70804 11 30 313 321 2 115 55 7 7 49 clb auto 29.7 MiB 0.40 448 1927 352 1502 73 69.1 MiB 0.07 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.000863635 0.000740182 0.0221309 0.0195205 -1 -1 -1 -1 595 5.45872 228 2.09174 234 449 14202 4622 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 2.70461 2.28805 -176.84 -2.70461 0 0 0.05 -1 -1 69.1 MiB 0.06 0.0568064 0.051944 69.1 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml stereovision3.v common 4.23 odin 167.25 MiB 3.26 171264 -1 -1 4 0.13 -1 -1 33232 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66852 11 30 262 292 2 99 61 7 7 49 clb auto 25.1 MiB 0.04 688 437 2341 384 1888 69 65.3 MiB 0.02 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000415356 0.000361815 0.0107384 0.00950622 -1 -1 -1 -1 434 4.56842 177 1.86316 730 1655 64750 15779 1.07788e+06 1.07788e+06 207176. 4228.08 23 4440 29880 -1 2.44651 2.32748 -175.142 -2.44651 0 0 0.02 -1 -1 65.3 MiB 0.03 0.0334807 0.0293173 65.3 MiB -1 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.68 odin 156.75 MiB 2.59 160512 -1 -1 5 0.11 -1 -1 33280 -1 -1 14 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69556 11 30 313 321 2 114 55 7 7 49 clb auto 28.3 MiB 0.18 671 455 1719 301 1356 62 67.9 MiB 0.02 0.00 2.73611 2.6413 -165.526 -2.6413 2.31106 0.00 0.000448919 0.000388835 0.0114299 0.0103066 -1 -1 -1 -1 571 5.28704 218 2.01852 192 380 9910 2908 1.07788e+06 754516 219490. 4479.39 12 5100 32136 -1 2.66069 2.29553 -166.559 -2.66069 0 0 0.02 -1 -1 67.9 MiB 0.02 0.0319073 0.029025 67.9 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt index df63a32e43..85c5267f8c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_analytic_placer/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.27 vpr 67.81 MiB 0.06 9984 -1 -1 3 0.40 -1 -1 39908 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69436 99 130 363 493 1 251 298 12 12 144 clb auto 28.8 MiB 0.14 1080 1293 313 846 134 67.8 MiB 0.06 0.00 2.45187 -223.196 -2.45187 2.45187 0.31 0.000607122 0.000549979 0.00491114 0.00472929 -1 -1 -1 -1 34 2076 26 5.66058e+06 4.21279e+06 293002. 2034.74 1.92 0.386002 0.351306 12094 55633 -1 1662 10 540 720 43948 13958 2.71514 2.71514 -233.572 -2.71514 0 0 360780. 2505.42 0.02 0.06 0.08 -1 -1 0.02 0.0335019 0.0302667 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.89 odin 99.75 MiB 2.21 102144 -1 -1 3 0.20 -1 -1 34100 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67576 99 130 363 493 1 252 298 12 12 144 clb auto 27.1 MiB 0.07 1168 1026 1293 339 819 135 66.0 MiB 0.05 0.00 2.24785 2.1902 -216.85 -2.1902 2.1902 0.09 0.00056326 0.000525731 0.00350551 0.00338302 -1 -1 -1 -1 38 1909 17 5.66058e+06 4.21279e+06 319130. 2216.18 0.38 0.117941 0.107068 12522 62564 -1 1585 12 545 712 54323 17831 2.61371 2.61371 -231.046 -2.61371 0 0 406292. 2821.48 0.01 0.03 0.04 -1 -1 0.01 0.0185355 0.017307 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt index c57ad9bdb4..5e82650715 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_n4_v7_bidir.xml styr.blif common 1.89 vpr 61.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62636 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.06 1288 4445 682 3619 144 61.2 MiB 0.05 0.00 5.46014 -72.9505 -5.46014 5.46014 0.09 0.000707997 0.000614185 0.0204147 0.0180597 -1 -1 -1 -1 14 2036 29 2.43e+06 2.07e+06 -1 -1 0.97 0.236366 0.209157 3402 27531 -1 1911 15 1185 4098 215222 27160 6.9309 6.9309 -92.2142 -6.9309 0 0 -1 -1 0.01 0.10 0.02 -1 -1 0.01 0.0335803 0.0304927 - k4_n4_v7_longline_bidir.xml styr.blif common 1.77 vpr 60.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61816 10 10 253 263 1 165 89 11 11 121 clb auto 21.3 MiB 0.05 1219 4247 600 3483 164 60.4 MiB 0.05 0.00 4.42494 -53.3169 -4.42494 4.42494 0.10 0.000681666 0.000592315 0.0189188 0.016758 -1 -1 -1 -1 18 2215 40 2.43e+06 2.07e+06 -1 -1 0.80 0.256847 0.227018 3282 34431 -1 2139 18 1151 3756 254207 31830 9.07319 9.07319 -108.035 -9.07319 0 0 -1 -1 0.02 0.10 0.03 -1 -1 0.02 0.0370258 0.033411 - k4_n4_v7_l1_bidir.xml styr.blif common 2.35 vpr 61.16 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62632 10 10 253 263 1 165 89 11 11 121 clb auto 21.5 MiB 0.05 1285 7613 1616 5547 450 61.2 MiB 0.12 0.00 6.9252 -85.9419 -6.9252 6.9252 0.14 0.000675324 0.000585254 0.0347554 0.0308708 -1 -1 -1 -1 10 1481 31 2.43e+06 2.07e+06 -1 -1 1.17 0.183607 0.16336 4482 22551 -1 1268 22 1168 4312 263452 47622 7.30329 7.30329 -93.8299 -7.30329 0 0 -1 -1 0.01 0.13 0.02 -1 -1 0.01 0.0396264 0.0357171 - k4_n4_v7_bidir_pass_gate.xml styr.blif common 3.49 vpr 60.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 69 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61772 10 10 253 263 1 165 89 11 11 121 clb auto 21.2 MiB 0.05 1234 4643 666 3821 156 60.3 MiB 0.09 0.01 3.51175 -43.7413 -3.51175 3.51175 0.09 0.000766831 0.000671887 0.0247522 0.0222268 -1 -1 -1 -1 14 2053 42 2.43e+06 2.07e+06 -1 -1 2.23 0.282741 0.249953 3402 27531 -1 1991 28 1438 5059 778762 132220 26.9853 26.9853 -248.248 -26.9853 0 0 -1 -1 0.01 0.37 0.03 -1 -1 0.01 0.0480187 0.0429407 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_n4_v7_bidir.xml styr.blif common 1.00 vpr 59.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61128 10 10 253 263 1 171 92 11 11 121 clb auto 19.6 MiB 0.03 1829 1341 4439 719 3525 195 59.7 MiB 0.03 0.00 8.75156 5.95188 -76.2362 -5.95188 5.95188 0.03 0.000372798 0.000336358 0.0101275 0.00926594 -1 -1 -1 -1 14 2179 38 2.43e+06 2.16e+06 -1 -1 0.47 0.0972455 0.0836955 3402 27531 -1 1923 17 1033 3494 176707 22465 7.58177 7.58177 -95.383 -7.58177 0 0 -1 -1 0.00 0.04 0.01 -1 -1 0.00 0.0163727 0.0146544 +k4_n4_v7_longline_bidir.xml styr.blif common 0.93 vpr 59.69 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61124 10 10 253 263 1 171 92 11 11 121 clb auto 20.2 MiB 0.03 1829 1318 3611 426 3020 165 59.7 MiB 0.02 0.00 5.19817 4.47516 -54.2373 -4.47516 4.47516 0.04 0.000357194 0.000327491 0.00872522 0.00800938 -1 -1 -1 -1 17 2528 41 2.43e+06 2.16e+06 -1 -1 0.37 0.0881091 0.0761338 3202 31699 -1 2252 25 1472 4968 313575 40767 9.40236 9.40236 -107.704 -9.40236 0 0 -1 -1 0.01 0.06 0.01 -1 -1 0.01 0.0205934 0.018225 +k4_n4_v7_l1_bidir.xml styr.blif common 1.05 vpr 59.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61052 10 10 253 263 1 171 92 11 11 121 clb auto 19.6 MiB 0.03 1829 1340 8579 1857 6361 361 59.6 MiB 0.04 0.00 11.3865 6.30908 -81.1511 -6.30908 6.30908 0.04 0.000378171 0.000340838 0.0176138 0.016088 -1 -1 -1 -1 11 1565 28 2.43e+06 2.16e+06 -1 -1 0.46 0.0837494 0.072839 4842 26035 -1 1365 23 1309 5061 314893 55846 8.55913 8.55913 -101.511 -8.55913 0 0 -1 -1 0.00 0.07 0.01 -1 -1 0.00 0.0195915 0.0173663 +k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.29 vpr 59.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61132 10 10 253 263 1 171 92 11 11 121 clb auto 19.8 MiB 0.03 1829 1326 4025 528 3322 175 59.7 MiB 0.02 0.00 4.50889 3.47884 -44.786 -3.47884 3.47884 0.03 0.000370889 0.000332628 0.00920041 0.00841326 -1 -1 -1 -1 16 2193 28 2.43e+06 2.16e+06 -1 -1 0.69 0.0908466 0.0783035 3522 30407 -1 2061 19 1236 4213 766518 139225 14.4125 14.4125 -146.898 -14.4125 0 0 -1 -1 0.00 0.12 0.01 -1 -1 0.00 0.01733 0.0154935 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt index 0bd2ba5a63..bf8f4235b9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.92 vpr 66.34 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36540 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67936 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 427 1815 293 1474 48 66.3 MiB 0.03 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.000749649 0.00064239 0.0161237 0.0140852 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.28 0.147245 0.127953 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.08 0.01 -1 -1 0.00 0.047308 0.0404063 - k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 2.40 vpr 66.13 MiB 0.07 10368 -1 -1 4 0.23 -1 -1 36792 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67716 11 30 262 292 2 99 60 7 7 49 clb auto 27.2 MiB 0.08 427 1815 293 1474 48 66.1 MiB 0.04 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.000744837 0.000636456 0.0185703 0.0149662 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.64 0.298818 0.25277 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.10 0.01 -1 -1 0.00 0.0500747 0.044978 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 4.11 odin 167.25 MiB 2.75 171264 -1 -1 4 0.12 -1 -1 33096 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66760 11 30 262 292 2 99 61 7 7 49 clb auto 25.1 MiB 0.04 688 430 2821 451 2299 71 65.2 MiB 0.02 0.00 2.92675 2.74423 -180.089 -2.74423 2.44742 0.02 0.000405254 0.000351084 0.0121422 0.0106998 -1 -1 -1 -1 18 673 35 1.07788e+06 1.07788e+06 45686.6 932.380 0.18 0.0749113 0.0629661 2616 8308 -1 591 24 845 2121 68310 27246 2.65985 2.3922 -190.754 -2.65985 0 0 59124.6 1206.62 0.00 0.04 0.00 -1 -1 0.00 0.0225961 0.019569 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 4.49 odin 167.25 MiB 2.84 171264 -1 -1 4 0.12 -1 -1 33076 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.8 MiB 0.05 688 430 2821 451 2299 71 65.7 MiB 0.03 0.00 2.92675 2.74423 -180.089 -2.74423 2.44742 0.02 0.000444492 0.000390671 0.0153437 0.0137473 -1 -1 -1 -1 18 673 35 1.07788e+06 1.07788e+06 45686.6 932.380 0.47 0.165439 0.138844 2616 8308 -1 591 24 845 2121 68310 27246 2.65985 2.3922 -190.754 -2.65985 0 0 59124.6 1206.62 0.00 0.04 0.00 -1 -1 0.00 0.0226738 0.0196115 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt index 7d75ebf7e2..f9b5fe2689 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.32 vpr 67.44 MiB 0.07 9856 -1 -1 3 0.36 -1 -1 39552 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69060 99 130 363 493 1 255 305 13 13 169 clb auto 27.9 MiB 0.11 817 73151 23083 37131 12937 67.4 MiB 0.30 0.01 2.36834 -235.63 -2.36834 2.36834 0.29 0.00233393 0.00223993 0.0738859 0.066584 -1 -1 -1 -1 32 1352 17 6.63067e+06 4.59005e+06 323148. 1912.12 0.52 0.196726 0.178694 11612 59521 -1 1138 16 719 1086 65347 22389 2.48507 2.48507 -238.178 -2.48507 0 0 396943. 2348.77 0.02 0.13 0.12 -1 -1 0.02 0.0517727 0.0472555 - k6_N10_mem32K_40nm.xml diffeq1.v common 10.12 vpr 70.60 MiB 0.03 9856 -1 -1 15 0.44 -1 -1 38380 -1 -1 60 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72292 162 96 999 932 1 661 323 16 16 256 mult_36 auto 31.3 MiB 0.38 5531 95525 26953 60139 8433 70.6 MiB 0.91 0.01 21.9361 -1891.35 -21.9361 21.9361 0.47 0.00396915 0.00366377 0.403824 0.374905 -1 -1 -1 -1 44 11294 43 1.21132e+07 5.21364e+06 665287. 2598.78 5.71 1.78116 1.66467 20656 131250 -1 8771 24 4066 8799 1047369 299882 22.5944 22.5944 -1935.68 -22.5944 0 0 864808. 3378.16 0.04 0.50 0.16 -1 -1 0.04 0.234899 0.221057 - k6_N10_mem32K_40nm.xml single_wire.v common 0.56 vpr 65.29 MiB 0.01 6912 -1 -1 1 0.02 -1 -1 32916 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66852 1 1 1 2 0 1 2 3 3 9 -1 auto 27.0 MiB 0.00 2 3 0 3 0 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.0231e-05 6.013e-06 7.2755e-05 4.8573e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.00153872 0.00147005 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00109157 0.00106485 - k6_N10_mem32K_40nm.xml single_ff.v common 0.49 vpr 65.16 MiB 0.01 7040 -1 -1 1 0.02 -1 -1 33280 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66728 2 1 3 4 1 3 4 3 3 9 -1 auto 26.9 MiB 0.00 6 9 5 1 3 65.2 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5008e-05 1.0331e-05 0.000105161 7.8059e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.0016194 0.0015365 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.00112886 0.00109032 - k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 5.85 vpr 67.48 MiB 0.06 9856 -1 -1 3 0.36 -1 -1 39692 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69100 99 130 363 493 1 255 305 19 19 361 o auto 27.9 MiB 0.10 1043 75203 18688 40447 16068 67.5 MiB 0.27 0.00 2.5827 -243.865 -2.5827 2.5827 1.92 0.000939884 0.00084584 0.0725048 0.0652395 -1 -1 -1 -1 36 1432 20 1.79173e+07 4.59005e+06 833707. 2309.44 1.36 0.302543 0.27272 24998 161561 -1 1342 23 802 1298 88966 26229 2.93129 2.93129 -249.701 -2.93129 0 0 1.02328e+06 2834.56 0.07 0.10 0.15 -1 -1 0.07 0.0554021 0.0511266 - k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 12.40 vpr 79.29 MiB 0.04 9856 -1 -1 15 0.45 -1 -1 38032 -1 -1 60 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 81188 162 96 999 932 1 661 323 24 24 576 i auto 31.0 MiB 0.28 7114 95525 25526 57948 12051 79.3 MiB 0.94 0.01 21.4854 -1914.4 -21.4854 21.4854 3.35 0.00392701 0.00363416 0.415599 0.386608 -1 -1 -1 -1 32 12804 30 3.08128e+07 5.21364e+06 1.24505e+06 2161.54 3.94 1.18592 1.11276 39974 242477 -1 10817 26 4455 9936 1378660 349639 22.5193 22.5193 -2054.22 -22.5193 0 0 1.54255e+06 2678.04 0.12 0.65 0.37 -1 -1 0.12 0.246186 0.231211 - k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 0.47 vpr 65.28 MiB 0.02 6784 -1 -1 1 0.02 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66848 1 1 1 2 0 1 2 4 4 16 i auto 26.9 MiB 0.00 3 3 0 0 3 65.3 MiB 0.00 0.00 0.18684 -0.18684 -0.18684 nan 0.00 1.1306e-05 5.604e-06 7.2139e-05 4.6493e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.00155951 0.00148904 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.0014785 0.00144447 - k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 0.49 vpr 65.16 MiB 0.02 7040 -1 -1 1 0.02 -1 -1 33288 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66724 2 1 3 4 1 3 4 4 4 16 i auto 26.9 MiB 0.00 7 9 0 2 7 65.2 MiB 0.00 0.00 0.55247 -0.955943 -0.55247 0.55247 0.00 1.6222e-05 1.0832e-05 0.00010458 7.8535e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.01 0.00166008 0.00157112 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.00159511 0.00154443 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.80 odin 99.75 MiB 2.20 102144 -1 -1 3 0.20 -1 -1 34096 -1 -1 75 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67832 99 130 363 493 1 253 305 13 13 169 clb auto 26.7 MiB 0.04 2273 844 74177 21541 39695 12941 66.2 MiB 0.12 0.00 2.6333 2.22949 -229.909 -2.22949 2.22949 0.11 0.000542243 0.000508101 0.0415956 0.0389332 -1 -1 -1 -1 32 1393 19 6.63067e+06 4.59005e+06 323148. 1912.12 0.22 0.111211 0.102107 11612 59521 -1 1193 22 721 1096 62496 20405 2.52707 2.52707 -230.152 -2.52707 0 0 396943. 2348.77 0.01 0.04 0.03 -1 -1 0.01 0.0269632 0.0248202 +k6_N10_mem32K_40nm.xml diffeq1.v common 6.53 odin 87.38 MiB 2.18 89472 -1 -1 15 0.29 -1 -1 34632 -1 -1 62 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71132 162 96 999 932 1 663 325 16 16 256 mult_36 auto 29.8 MiB 0.15 9594 5574 90802 23938 58756 8108 69.5 MiB 0.35 0.01 24.8422 21.1611 -1910.27 -21.1611 21.1611 0.17 0.00167942 0.00157719 0.149739 0.14046 -1 -1 -1 -1 40 11068 31 1.21132e+07 5.32143e+06 612675. 2393.26 1.95 0.624335 0.581811 19892 118481 -1 8993 24 3753 8101 1142271 339586 22.091 22.091 -1952.75 -22.091 0 0 771607. 3014.09 0.02 0.26 0.07 -1 -1 0.02 0.109107 0.10319 +k6_N10_mem32K_40nm.xml single_wire.v common 1.74 vpr 63.87 MiB 1.20 62208 -1 -1 1 0.02 -1 -1 29676 -1 -1 0 1 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 1 1 1 2 0 1 2 3 3 9 -1 auto 25.2 MiB 0.00 2 2 3 0 3 0 63.9 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.952e-06 3.841e-06 5.3762e-05 3.5945e-05 -1 -1 -1 -1 2 1 1 53894 0 1165.58 129.509 0.00 0.000937013 0.000882922 254 297 -1 1 1 1 1 19 15 0.211201 nan -0.211201 -0.211201 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000864715 0.000839404 +k6_N10_mem32K_40nm.xml single_ff.v common 1.73 vpr 63.87 MiB 1.18 62208 -1 -1 1 0.02 -1 -1 30008 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65400 2 1 3 4 1 3 4 3 3 9 -1 auto 25.6 MiB 0.00 6 6 9 5 1 3 63.9 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 1.4427e-05 9.795e-06 9.0773e-05 6.8612e-05 -1 -1 -1 -1 2 2 2 53894 53894 1165.58 129.509 0.00 0.0010051 0.00092554 254 297 -1 2 2 3 3 56 18 0.577715 0.577715 -0.9588 -0.577715 0 0 1165.58 129.509 0.00 0.00 0.00 -1 -1 0.00 0.000925874 0.000886196 +k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 4.95 odin 99.75 MiB 2.18 102144 -1 -1 3 0.21 -1 -1 34096 -1 -1 75 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67616 99 130 363 493 1 253 305 19 19 361 o auto 26.4 MiB 0.04 3198 975 75203 18286 41793 15124 66.0 MiB 0.13 0.00 3.0814 2.23502 -240.202 -2.23502 2.23502 0.67 0.000564829 0.000532266 0.0443077 0.0417084 -1 -1 -1 -1 36 1305 22 1.79173e+07 4.59005e+06 833707. 2309.44 0.56 0.166596 0.152961 24998 161561 -1 1270 26 731 1078 66382 19258 2.55328 2.55328 -255.132 -2.55328 0 0 1.02328e+06 2834.56 0.03 0.05 0.09 -1 -1 0.03 0.0307218 0.0281825 +k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 7.43 odin 87.00 MiB 1.98 89088 -1 -1 15 0.29 -1 -1 34620 -1 -1 62 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78504 162 96 999 932 1 663 325 24 24 576 i auto 30.1 MiB 0.15 13908 6960 97504 27766 60997 8741 76.7 MiB 0.38 0.01 27.051 21.3253 -1909.99 -21.3253 21.3253 1.14 0.00168296 0.00157156 0.160765 0.15046 -1 -1 -1 -1 44 10768 25 3.08128e+07 5.32143e+06 1.60659e+06 2789.21 1.67 0.561172 0.522326 44574 325925 -1 10016 19 3329 7120 1011052 264242 21.9724 21.9724 -1931.12 -21.9724 0 0 2.07854e+06 3608.58 0.06 0.21 0.18 -1 -1 0.06 0.082648 0.0779565 +k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 1.66 vpr 63.86 MiB 1.17 61824 -1 -1 1 0.02 -1 -1 29676 -1 -1 0 1 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65392 1 1 1 2 0 1 2 4 4 16 i auto 25.2 MiB 0.00 3 3 3 0 0 3 63.9 MiB 0.00 0.00 0.18684 0.18684 -0.18684 -0.18684 nan 0.00 6.623e-06 3.608e-06 5.0071e-05 3.3373e-05 -1 -1 -1 -1 4 2 1 215576 0 2092.17 130.760 0.00 0.000884175 0.000822836 324 600 -1 2 1 1 1 17 7 0.229376 nan -0.229376 -0.229376 0 0 3281.68 205.105 0.00 0.00 0.00 -1 -1 0.00 0.000865836 0.000836718 +k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 1.81 vpr 63.48 MiB 1.29 62208 -1 -1 1 0.02 -1 -1 29956 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65008 2 1 3 4 1 3 4 4 4 16 i auto 25.2 MiB 0.00 7 7 9 0 2 7 63.5 MiB 0.00 0.00 0.55247 0.55247 -0.955943 -0.55247 0.55247 0.00 9.495e-06 6.13e-06 7.3063e-05 5.3359e-05 -1 -1 -1 -1 6 3 2 215576 53894 3281.68 205.105 0.00 0.000961518 0.000885564 340 760 -1 3 2 3 3 59 19 0.569757 0.569757 -0.969092 -0.569757 0 0 4601.64 287.602 0.00 0.00 0.00 -1 -1 0.00 0.000926462 0.000881683 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt index a4f4578b4e..2334d259eb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.22 vpr 66.21 MiB 0.06 10368 -1 -1 4 0.23 -1 -1 36792 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67796 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 485 3687 781 2795 111 66.2 MiB 0.01 0.00 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 18 734 39 1.07788e+06 1.02399e+06 45686.6 932.380 0.65 0.239065 0.204044 2616 8308 -1 583 23 761 1801 50764 16568 2.52485 2.36559 -186.102 -2.52485 0 0 59124.6 1206.62 0.00 0.07 0.01 -1 -1 0.00 0.0486043 0.0430292 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.87 odin 167.25 MiB 2.60 171264 -1 -1 4 0.12 -1 -1 33100 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67032 11 30 262 292 2 99 61 7 7 49 clb auto 25.4 MiB 0.04 688 466 3421 681 2621 119 65.5 MiB 0.00 0.00 -1 -1 -1 -1 -1 -1 0 0 0 0 -1 -1 -1 -1 18 697 29 1.07788e+06 1.07788e+06 45686.6 932.380 0.16 0.0589119 0.0493105 2616 8308 -1 557 36 1075 2921 72281 22541 2.63547 2.45943 -188.872 -2.63547 0 0 59124.6 1206.62 0.00 0.05 0.00 -1 -1 0.00 0.0299743 0.0256686 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt index d3b62c629a..abbecd671c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_check_route_options/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common_--check_route_full 14.36 vpr 58.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60212 6 7 19 26 0 19 26 3 3 9 -1 auto 20.5 MiB 0.00 51 216 43 63 110 58.8 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 13.10 4.6187e-05 3.8396e-05 0.000395937 0.000323618 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00202221 0.00179313 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00173217 0.0016394 - sub_tiles.xml sub_tiles.blif common_--check_route_quick 16.94 vpr 58.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60340 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 58.9 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.28 4.6086e-05 3.7994e-05 0.000373556 0.000302701 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.13 0.00235088 0.00212378 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.06 -1 -1 0.00 0.00221042 0.00197359 - sub_tiles.xml sub_tiles.blif common_--check_route_off 16.20 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60476 6 7 19 26 0 19 26 3 3 9 -1 auto 20.7 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 14.72 4.2295e-05 3.5105e-05 0.000363474 0.000296118 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.12 0.00229484 0.00207762 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00174454 0.00165562 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common_--check_route_full 4.60 vpr 57.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58896 6 7 19 26 0 19 26 3 3 9 -1 auto 19.1 MiB 0.00 51 51 216 43 63 110 57.5 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.88 2.1915e-05 1.7842e-05 0.000207274 0.000166571 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00147367 0.0013425 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00105837 0.000997571 +sub_tiles.xml sub_tiles.blif common_--check_route_quick 4.57 vpr 57.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58392 6 7 19 26 0 19 26 3 3 9 -1 auto 18.6 MiB 0.00 51 51 216 43 63 110 57.0 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.84 2.2325e-05 1.8099e-05 0.000210674 0.000169565 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00142374 0.0012953 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.00105498 0.000994675 +sub_tiles.xml sub_tiles.blif common_--check_route_off 4.56 vpr 57.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58896 6 7 19 26 0 19 26 3 3 9 -1 auto 19.1 MiB 0.00 51 51 216 43 63 110 57.5 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.83 2.1907e-05 1.772e-05 0.000206458 0.000166686 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00148503 0.00135441 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.03 -1 -1 0.00 0.0010293 0.000968816 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt index 7b6b29fbf3..23f873bdf6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.50 vpr 66.18 MiB 0.01 6912 -1 -1 1 0.03 -1 -1 33524 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67768 9 8 71 66 1 35 20 5 5 25 clb auto 27.2 MiB 0.61 102 641 211 420 10 66.2 MiB 0.01 0.00 2.52843 -27.3721 -2.52843 2.52843 0.02 0.000162932 0.000142933 0.00487777 0.00439017 -1 -1 -1 -1 32 152 12 151211 75605.7 43252.0 1730.08 0.15 0.05219 0.0443549 2004 6761 -1 170 13 131 173 5906 3259 2.68643 2.68643 -34.5837 -2.68643 0 0 52324.5 2092.98 0.00 0.01 0.01 -1 -1 0.00 0.00766663 0.00704697 14 17 16 6 0 0 - k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 6.42 vpr 67.07 MiB 0.01 6912 -1 -1 1 0.04 -1 -1 33628 -1 -1 8 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68680 19 18 299 240 1 146 45 6 6 36 clb auto 27.6 MiB 4.94 477 2365 468 1860 37 67.1 MiB 0.04 0.00 4.92757 -99.6523 -4.92757 4.92757 0.05 0.000316619 0.0002807 0.0196432 0.0179661 -1 -1 -1 -1 54 1052 25 403230 201615 113905. 3164.04 0.53 0.17427 0.152991 4050 20995 -1 792 24 850 1349 48852 19559 4.89358 4.89358 -108.576 -4.89358 0 0 146644. 4073.44 0.00 0.05 0.03 -1 -1 0.00 0.0285954 0.0259387 62 82 85 13 0 0 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 2.19 vpr 64.45 MiB 1.10 63744 -1 -1 1 0.02 -1 -1 30520 -1 -1 3 9 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66000 9 8 71 66 1 36 20 5 5 25 clb auto 25.7 MiB 0.34 137 104 641 234 396 11 64.5 MiB 0.01 0.00 2.52843 2.52843 -27.3563 -2.52843 2.52843 0.01 8.6511e-05 7.8365e-05 0.00289488 0.00267695 -1 -1 -1 -1 36 198 14 151211 75605.7 46719.2 1868.77 0.06 0.0213537 0.018032 2052 7582 -1 134 10 105 135 3075 1640 2.65565 2.65565 -30.2407 -2.65565 0 0 57775.2 2311.01 0.00 0.01 0.00 -1 -1 0.00 0.00417193 0.00385609 14 17 16 6 0 0 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 4.82 vpr 66.02 MiB 1.13 65664 -1 -1 1 0.03 -1 -1 30676 -1 -1 8 19 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67604 19 18 299 240 1 146 45 6 6 36 clb auto 26.2 MiB 2.65 653 478 2685 571 2068 46 66.0 MiB 0.02 0.00 4.89372 4.92757 -99.729 -4.92757 4.92757 0.02 0.000296226 0.000272813 0.0128327 0.011962 -1 -1 -1 -1 54 1009 23 403230 201615 113905. 3164.04 0.19 0.079399 0.06938 4050 20995 -1 757 20 679 1069 35690 14737 4.92407 4.92407 -104.302 -4.92407 0 0 146644. 4073.44 0.00 0.03 0.01 -1 -1 0.00 0.0178827 0.0163921 62 82 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt index 82e16e68c5..fb934275ef 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.35 vpr 59.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61244 1 4 28 32 2 10 9 4 4 16 clb auto 21.2 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.9876e-05 6.8917e-05 0.000564474 0.000511898 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00933145 0.00790294 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.0020437 0.00190467 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.33 vpr 60.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61444 1 4 28 32 2 10 9 4 4 16 clb auto 21.5 MiB 0.01 21 27 10 10 7 60.0 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 9.3379e-05 8.2596e-05 0.000566541 0.000512464 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00867291 0.00731794 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00253268 0.00233063 - timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.35 vpr 59.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61264 1 4 28 32 2 10 9 4 4 16 clb auto 21.4 MiB 0.01 21 27 10 10 7 59.8 MiB 0.00 0.00 2.44626 0 0 2.44626 0.01 7.8562e-05 6.7163e-05 0.000561289 0.000507136 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00963983 0.0081025 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00296634 0.00273132 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.30 vpr 58.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59864 1 4 28 32 2 10 9 4 4 16 clb auto 19.5 MiB 0.00 22 21 27 10 10 7 58.5 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.01 4.1348e-05 3.6073e-05 0.00034488 0.000317087 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00504245 0.00426562 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00176246 0.0016367 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.30 vpr 58.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59476 1 4 28 32 2 10 9 4 4 16 clb auto 19.5 MiB 0.00 22 21 27 10 10 7 58.1 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 4.1185e-05 3.5891e-05 0.000352653 0.000324622 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00514641 0.00434508 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00178216 0.00165267 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.31 vpr 58.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59392 1 4 28 32 2 10 9 4 4 16 clb auto 19.0 MiB 0.00 22 21 27 10 10 7 58.0 MiB 0.00 0.00 2.44626 2.44626 0 0 2.44626 0.00 4.1401e-05 3.6001e-05 0.000345345 0.000317533 -1 -1 -1 -1 8 11 5 72000 72000 5593.62 349.601 0.02 0.00507361 0.00430143 672 1128 -1 21 6 21 21 561 284 2.37141 2.37141 0 0 0 0 6492.02 405.751 0.00 0.00 0.00 -1 -1 0.00 0.00175666 0.00163105 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt index 17671e26cf..018bbc29e2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.35 vpr 59.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61088 2 2 22 24 2 4 6 4 4 16 clb auto 21.2 MiB 0.01 8 15 5 7 3 59.7 MiB 0.00 0.00 1.297 0 0 1.297 0.01 6.7393e-05 5.6956e-05 0.000402551 0.000351966 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.01 0.00291274 0.00268287 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00264613 0.00228889 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.29 vpr 58.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59792 2 2 22 24 2 4 6 4 4 16 clb auto 19.6 MiB 0.00 8 8 15 5 7 3 58.4 MiB 0.00 0.00 1.297 1.297 0 0 1.297 0.00 3.2816e-05 2.7598e-05 0.000245535 0.000217945 -1 -1 -1 -1 6 12 3 72000 36000 4025.56 251.598 0.00 0.00184439 0.00170877 660 1032 -1 15 4 8 8 644 530 1.297 1.297 0 0 0 0 5593.62 349.601 0.00 0.00 0.00 -1 -1 0.00 0.00136872 0.00127721 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt index 55f3e1dd3b..b7e6584d84 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.69449 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt index c54c9279c5..6f4716f18d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.26 vpr 59.67 MiB 0.00 6912 -1 -1 1 0.02 -1 -1 33484 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61100 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 6 9 3 5 1 59.7 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.4271e-05 9.019e-06 0.000105429 7.7044e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00167801 0.00157995 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.26 vpr 59.67 MiB 0.00 6912 -1 -1 1 0.02 -1 -1 33216 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61100 2 1 3 4 1 3 4 3 3 9 -1 auto 21.4 MiB 0.00 9 9 3 3 3 59.7 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.5585e-05 1.0104e-05 0.000105029 7.6023e-05 -1 -1 -1 -1 -1 4 3 18000 18000 15707.9 1745.32 0.00 0.00153942 0.00144868 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 4.33 abc 63.01 MiB 0.24 59520 -1 -1 2 1.56 -1 -1 64520 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63024 5 156 191 347 1 163 316 15 15 225 clb auto 22.0 MiB 0.04 29 82016 58904 3157 19955 61.5 MiB 0.15 0.00 1.49664 -15.1312 -1.49664 1.49664 0.00 0.000408132 0.000370067 0.0341355 0.031078 -1 -1 -1 -1 -1 32 6 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0428942 0.0391583 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 - timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 4.51 abc 63.14 MiB 0.34 59776 -1 -1 2 1.51 -1 -1 64652 -1 -1 155 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63260 5 156 191 347 1 163 316 15 15 225 clb auto 22.2 MiB 0.02 41 76641 54775 3226 18640 61.8 MiB 0.14 0.00 1.49775 -14.6172 -1.49775 1.49775 0.00 0.000395712 0.000358237 0.0299271 0.0269791 -1 -1 -1 -1 -1 63 5 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0377601 0.0341837 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.33 vpr 65.29 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33412 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 2 1 3 4 1 3 4 3 3 9 -1 auto 26.8 MiB 0.00 6 9 3 5 1 65.3 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.5615e-05 1.0606e-05 0.000109326 8.0241e-05 -1 -1 -1 -1 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.00165784 0.00156601 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 - timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.25 vpr 65.38 MiB 0.01 7040 -1 -1 1 0.02 -1 -1 33208 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66952 2 1 3 4 1 3 4 3 3 9 -1 auto 27.1 MiB 0.00 9 9 3 3 3 65.4 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.6671e-05 1.1297e-05 0.000111494 8.1284e-05 -1 -1 -1 -1 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.00178932 0.0017001 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 4.46 vpr 71.98 MiB 0.15 16896 -1 -1 2 0.16 -1 -1 37600 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73704 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.58 8394 210108 78030 120895 11183 72.0 MiB 1.33 0.02 3.90475 -4339.03 -3.90475 3.90475 0.00 0.00537924 0.00456001 0.565099 0.476317 -1 -1 -1 -1 -1 12247 12 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.38 0.731735 0.628685 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 - timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 4.57 vpr 72.21 MiB 0.16 17152 -1 -1 2 0.16 -1 -1 37596 -1 -1 43 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73948 311 156 972 1128 1 953 525 28 28 784 memory auto 32.4 MiB 0.52 9639 203757 70988 121974 10795 72.2 MiB 1.36 0.02 4.05379 -3834.49 -4.05379 4.05379 0.00 0.00624609 0.00547423 0.627089 0.535493 -1 -1 -1 -1 -1 13797 11 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.48 0.824983 0.713955 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 0.42 vpr 57.73 MiB 0.10 45312 -1 -1 1 0.02 -1 -1 29984 -1 -1 1 2 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59112 2 1 3 4 1 3 4 3 3 9 -1 auto 19.3 MiB 0.00 6 6 9 3 5 1 57.7 MiB 0.00 0.00 0.55447 0.55447 -0.91031 -0.55447 0.55447 0.00 9.671e-06 6.4e-06 7.3634e-05 5.5037e-05 -1 -1 -1 -1 -1 2 4 18000 18000 14049.7 1561.07 0.00 0.00102008 0.000946752 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 0.40 vpr 57.87 MiB 0.08 45312 -1 -1 1 0.02 -1 -1 29960 -1 -1 1 2 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59260 2 1 3 4 1 3 4 3 3 9 -1 auto 19.4 MiB 0.00 9 9 9 3 3 3 57.9 MiB 0.00 0.00 0.56425 0.48631 -0.91031 -0.48631 0.48631 0.00 1.0128e-05 6.088e-06 7.4758e-05 5.4181e-05 -1 -1 -1 -1 -1 4 3 18000 18000 15707.9 1745.32 0.00 0.00115418 0.00108395 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 11.11 odin 789.42 MiB 8.39 808368 -1 -1 2 0.91 -1 -1 50632 -1 -1 155 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61456 5 156 191 347 1 163 316 15 15 225 clb auto 20.6 MiB 0.02 118 29 82016 59012 3139 19865 60.0 MiB 0.07 0.00 1.99335 1.49664 -15.1312 -1.49664 1.49664 0.00 0.000218587 0.000205009 0.0179129 0.0168205 -1 -1 -1 -1 -1 32 6 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0227624 0.0213101 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 11.00 odin 789.65 MiB 8.22 808604 -1 -1 2 0.90 -1 -1 50628 -1 -1 155 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61840 5 156 191 347 1 163 316 15 15 225 clb auto 20.9 MiB 0.02 126 33 76641 54911 3193 18537 60.4 MiB 0.06 0.00 1.66097 1.47673 -14.6018 -1.47673 1.47673 0.00 0.000215293 0.000202099 0.0163557 0.015299 -1 -1 -1 -1 -1 47 5 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0208267 0.0194471 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 1.71 vpr 63.62 MiB 1.37 62208 -1 -1 1 0.02 -1 -1 29984 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65148 2 1 3 4 1 3 4 3 3 9 -1 auto 25.3 MiB 0.00 6 6 9 3 5 1 63.6 MiB 0.00 0.00 0.55247 0.55247 -0.90831 -0.55247 0.55247 0.00 9.495e-06 6.161e-06 7.7539e-05 5.8162e-05 -1 -1 -1 -1 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.000963467 0.000895961 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 1.56 vpr 63.87 MiB 1.20 62208 -1 -1 1 0.02 -1 -1 29976 -1 -1 1 2 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 2 1 3 4 1 3 4 3 3 9 -1 auto 25.2 MiB 0.00 9 9 9 3 3 3 63.9 MiB 0.00 0.00 0.56425 0.48631 -0.90831 -0.48631 0.48631 0.00 9.378e-06 5.802e-06 7.5374e-05 5.4709e-05 -1 -1 -1 -1 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.000951563 0.000888171 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_ideal_--route_chan_width_60 7.62 odin 618.93 MiB 5.31 633780 -1 -1 2 0.09 -1 -1 35196 -1 -1 43 311 15 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72812 311 156 972 1128 1 953 525 28 28 784 memory auto 32.0 MiB 0.28 18730 8256 201640 71067 119264 11309 71.1 MiB 0.57 0.01 4.8206 3.69209 -4283.73 -3.69209 3.69209 0.00 0.00251436 0.00222708 0.254259 0.224622 -1 -1 -1 -1 -1 12173 14 4.25198e+07 1.05374e+07 2.96205e+06 3778.13 0.20 0.35721 0.319406 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_route_--route_chan_width_60 7.58 odin 619.79 MiB 5.21 634660 -1 -1 2 0.09 -1 -1 35196 -1 -1 43 311 15 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72796 311 156 972 1128 1 953 525 28 28 784 memory auto 32.0 MiB 0.28 19537 8661 201640 66024 123894 11722 71.1 MiB 0.57 0.01 4.71974 3.76482 -3710.64 -3.76482 3.76482 0.00 0.00251751 0.00222729 0.255304 0.224377 -1 -1 -1 -1 -1 12504 13 4.25198e+07 1.05374e+07 3.02951e+06 3864.17 0.21 0.353969 0.31532 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt index 270c7d97d8..82215e0db5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_pll/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.68 vpr 66.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67792 8 4 25 28 5 19 19 6 6 36 clb auto 27.9 MiB 0.43 51 194 39 119 36 66.2 MiB 0.00 0.00 1.41795 -5.85435 -1.41795 0.545 0.00 6.5511e-05 4.9348e-05 0.000956967 0.000802791 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 675 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.01 -1 -1 66.2 MiB 0.00 0.00312006 0.00280809 66.2 MiB -1 0.01 - k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 vpr 20.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 21424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.35 vpr 64.65 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66204 8 4 25 28 5 19 19 6 6 36 clb auto 26.4 MiB 0.18 73 51 194 39 119 36 64.7 MiB 0.00 0.00 1.51369 1.41795 -5.85435 -1.41795 0.545 0.00 3.4655e-05 2.6815e-05 0.000451283 0.000368188 -1 -1 -1 -1 86 6.14286 35 2.50000 16 16 673 275 431152 215576 56755.0 1576.53 2 2184 7490 -1 1.6578 0.545 -6.7903 -1.6578 -0.42675 -0.369747 0.00 -1 -1 64.7 MiB 0.00 0.00174473 0.00156693 64.7 MiB -1 0.00 +k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 vpr 18.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 18664 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt index a8229d3cc5..9fc4513c22 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.39 vpr 65.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66856 -1 2 2 4 0 2 4 4 4 16 clb auto 27.0 MiB 0.00 0 9 0 2 7 65.3 MiB 0.00 0.00 nan 0 0 nan 0.01 1.324e-05 7.342e-06 8.3458e-05 5.501e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.00154065 0.00146112 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.00148898 0.00145049 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.32 vpr 63.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64848 -1 2 2 4 0 2 4 4 4 16 clb auto 24.7 MiB 0.00 0 0 9 0 2 7 63.3 MiB 0.00 0.00 nan nan 0 0 nan 0.00 8.32e-06 4.382e-06 6.2042e-05 4.1566e-05 -1 -1 -1 -1 2 0 1 107788 107788 1342.00 83.8749 0.00 0.000911021 0.000854588 504 462 -1 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.00 0.00 -1 -1 0.00 0.000865229 0.000834416 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt index dedf8b436a..37122255ff 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_grid.xml raygentop.v common 22.04 vpr 87.12 MiB 0.37 32000 -1 -1 3 1.37 -1 -1 43832 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89216 214 305 2963 2869 1 1444 650 25 25 625 -1 25x25 45.9 MiB 3.49 12196 290492 92452 176193 21847 87.1 MiB 1.73 0.04 4.70145 -2687.49 -4.70145 4.70145 0.77 0.009062 0.00821446 0.664489 0.598586 -1 -1 -1 -1 50 24072 42 3.19446e+07 9.79696e+06 2.03477e+06 3255.63 9.38 3.04543 2.74886 65619 409230 -1 20090 15 5518 12429 1427524 369655 4.84691 4.84691 -2936.69 -4.84691 0 0 2.61863e+06 4189.80 0.13 0.72 0.40 -1 -1 0.13 0.405468 0.382168 - column_io.xml raygentop.v common 30.34 vpr 87.28 MiB 0.43 32000 -1 -1 3 1.83 -1 -1 43888 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89376 214 305 2963 2869 1 1444 650 25 25 625 io auto 46.2 MiB 3.96 11325 239840 77339 132443 30058 87.3 MiB 2.09 0.03 4.40936 -2625.55 -4.40936 4.40936 1.20 0.0090281 0.0081843 0.836879 0.749323 -1 -1 -1 -1 48 24462 25 2.82259e+07 9.79696e+06 1.82181e+06 2914.90 14.53 3.9566 3.54503 57888 355703 -1 20518 17 5996 13599 1716937 426068 4.7409 4.7409 -2939.5 -4.7409 0 0 2.33544e+06 3736.71 0.17 0.92 0.52 -1 -1 0.17 0.442866 0.410518 - multiwidth_blocks.xml raygentop.v common 23.34 vpr 87.11 MiB 0.46 32000 -1 -1 3 1.66 -1 -1 43932 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89196 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.9 MiB 4.70 10825 234212 78128 135288 20796 87.1 MiB 2.20 0.03 4.45499 -2656.92 -4.45499 4.45499 0.58 0.00914429 0.00826611 0.84541 0.761865 -1 -1 -1 -1 60 22314 37 1.65001e+07 9.79696e+06 1.13508e+06 3144.28 8.15 3.5171 3.1499 34801 210837 -1 18718 16 6372 15066 2125910 636768 4.83864 4.83864 -2933.88 -4.83864 0 0 1.43369e+06 3971.44 0.09 1.02 0.34 -1 -1 0.09 0.423489 0.392785 - non_column.xml raygentop.v common 50.57 vpr 101.43 MiB 0.57 32128 -1 -1 3 1.64 -1 -1 43688 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103864 214 305 2963 2869 1 1444 650 33 33 1089 io auto 47.6 MiB 3.38 13852 267980 91761 149229 26990 98.5 MiB 2.25 0.03 4.81737 -2748.68 -4.81737 4.81737 2.25 0.00871345 0.00790536 0.883704 0.789723 -1 -1 -1 -1 46 27889 41 5.44432e+07 9.79696e+06 2.87196e+06 2637.24 31.91 4.82411 4.34906 94862 558952 -1 23226 19 7179 17098 2136481 565014 5.00295 5.00295 -3094.61 -5.00295 0 0 3.68462e+06 3383.49 0.29 1.11 0.95 -1 -1 0.29 0.492691 0.457205 - non_column_tall_aspect_ratio.xml raygentop.v common 41.13 vpr 107.46 MiB 0.65 32128 -1 -1 3 2.07 -1 -1 43888 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 110040 214 305 2963 2869 1 1444 650 23 46 1058 io auto 47.5 MiB 4.75 12924 225770 77986 115287 32497 98.0 MiB 1.99 0.02 4.68258 -2746.61 -4.68258 4.68258 2.17 0.00617553 0.00548634 0.751525 0.668955 -1 -1 -1 -1 50 24702 35 5.05849e+07 9.79696e+06 3.07243e+06 2904.00 20.48 4.80846 4.28853 95149 595581 -1 21346 17 5714 12751 1591343 424414 4.99583 4.99583 -3024.29 -4.99583 0 0 3.91054e+06 3696.17 0.39 1.00 1.06 -1 -1 0.39 0.462953 0.424532 - non_column_wide_aspect_ratio.xml raygentop.v common 40.58 vpr 101.39 MiB 0.68 32000 -1 -1 3 1.80 -1 -1 43696 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 103820 214 305 2963 2869 1 1444 650 43 22 946 io auto 47.4 MiB 4.77 13982 276422 90498 164087 21837 95.1 MiB 2.48 0.03 4.68152 -2857.71 -4.68152 4.68152 2.06 0.0081203 0.0072676 0.94579 0.847056 -1 -1 -1 -1 50 26296 34 4.55909e+07 9.79696e+06 2.70028e+06 2854.41 19.21 5.11489 4.60481 84704 520009 -1 22872 18 6244 14195 1614167 427447 4.86473 4.86473 -3155.96 -4.86473 0 0 3.44953e+06 3646.44 0.30 1.16 1.00 -1 -1 0.30 0.501153 0.460019 - custom_sbloc.xml raygentop.v common 25.95 vpr 86.98 MiB 0.39 32000 -1 -1 3 1.58 -1 -1 43804 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89072 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.8 MiB 4.86 11696 245468 82823 140883 21762 87.0 MiB 2.50 0.04 4.53013 -2681.39 -4.53013 4.53013 0.61 0.00909806 0.00824441 0.931511 0.836258 -1 -1 -1 -1 62 22622 49 1.65001e+07 9.79696e+06 1.15634e+06 3203.15 10.71 4.10582 3.71488 35161 219597 -1 19429 17 6137 14618 1898349 506769 4.83748 4.83748 -2977.52 -4.83748 0 0 1.43990e+06 3988.64 0.05 0.92 0.41 -1 -1 0.05 0.399467 0.368878 - multiple_io_types.xml raygentop.v common 148.40 vpr 474.05 MiB 0.38 31872 -1 -1 3 1.46 -1 -1 43604 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 485424 214 305 2963 2869 1 1444 650 67 67 4489 io_left auto 46.2 MiB 5.36 26050 90698 4115 22648 63935 474.0 MiB 0.95 0.03 4.73667 -3563.79 -4.73667 4.73667 26.71 0.00792183 0.00702959 0.36772 0.321766 -1 -1 -1 -1 52 41451 45 2.48753e+08 9.79696e+06 1.27607e+07 2842.65 95.91 4.21007 3.80326 406473 2447650 -1 35770 21 7664 17455 3505363 891802 5.27395 5.27395 -3927.86 -5.27395 0 0 1.67786e+07 3737.72 0.99 1.06 2.69 -1 -1 0.99 0.318577 0.29589 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_grid.xml raygentop.v common 24.21 odin 1.55 GiB 11.38 1620756 -1 -1 3 0.86 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88312 214 305 2963 2869 1 1441 650 25 25 625 -1 25x25 46.6 MiB 2.34 25402 12254 282050 88602 172367 21081 86.2 MiB 1.20 0.02 5.35403 4.41932 -2744.04 -4.41932 4.41932 0.51 0.00456697 0.00427604 0.484622 0.447341 -1 -1 -1 -1 48 24508 46 3.19446e+07 9.79696e+06 1.97188e+06 3155.02 4.31 1.58927 1.46697 64995 397836 -1 20934 15 5849 13951 1555077 389423 4.73647 4.73647 -2992.8 -4.73647 0 0 2.52596e+06 4041.53 0.08 0.43 0.24 -1 -1 0.08 0.215542 0.203428 +column_io.xml raygentop.v common 31.04 odin 1.54 GiB 10.96 1616220 -1 -1 3 0.85 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88288 214 305 2963 2869 1 1441 650 25 25 625 io auto 46.3 MiB 2.32 25737 12044 245468 82104 140823 22541 86.2 MiB 0.94 0.01 5.96169 4.61982 -2725.2 -4.61982 4.61982 0.45 0.00379513 0.00350345 0.360774 0.331583 -1 -1 -1 -1 50 25560 24 2.82259e+07 9.79696e+06 1.88190e+06 3011.03 12.10 1.66226 1.52766 58512 365993 -1 21648 16 6081 14502 1687459 402383 4.72983 4.72983 -3044.61 -4.72983 0 0 2.41964e+06 3871.43 0.07 0.39 0.23 -1 -1 0.07 0.194588 0.184524 +multiwidth_blocks.xml raygentop.v common 22.28 odin 1.45 GiB 11.36 1523644 -1 -1 3 0.86 -1 -1 40384 -1 -1 123 214 0 8 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88696 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.6 MiB 2.30 24028 11655 245468 82518 140645 22305 86.6 MiB 0.94 0.01 5.44642 4.52802 -2634.46 -4.52802 4.52802 0.22 0.00375748 0.00346104 0.356187 0.32727 -1 -1 -1 -1 60 24300 34 1.65001e+07 9.79696e+06 1.13508e+06 3144.28 3.45 1.18621 1.09239 34801 210837 -1 20057 19 6400 15852 2295662 663397 4.80907 4.80907 -2946.21 -4.80907 0 0 1.43369e+06 3971.44 0.04 0.50 0.13 -1 -1 0.04 0.215008 0.202964 +non_column.xml raygentop.v common 53.13 odin 1.93 GiB 39.11 2024016 -1 -1 3 0.86 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 102924 214 305 2963 2869 1 1441 650 33 33 1089 io auto 47.2 MiB 2.31 35936 13660 262352 89101 152531 20720 99.0 MiB 0.96 0.01 6.8947 4.81737 -2806.8 -4.81737 4.81737 0.85 0.00374869 0.00345753 0.379444 0.34828 -1 -1 -1 -1 44 28243 27 5.44432e+07 9.79696e+06 2.74036e+06 2516.40 4.46 1.32728 1.22173 93774 543488 -1 22727 18 6328 15147 1605451 431979 4.86083 4.86083 -3079.84 -4.86083 0 0 3.56397e+06 3272.70 0.13 0.41 0.38 -1 -1 0.13 0.207923 0.196656 +non_column_tall_aspect_ratio.xml raygentop.v common 52.95 odin 1.93 GiB 39.83 2023144 -1 -1 3 0.85 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 101720 214 305 2963 2869 1 1441 650 23 46 1058 io auto 47.8 MiB 2.34 34433 12310 253910 86017 138818 29075 98.2 MiB 0.91 0.01 6.20818 4.74318 -2736.15 -4.74318 4.74318 0.82 0.00366742 0.00337302 0.362804 0.332949 -1 -1 -1 -1 52 22487 30 5.05849e+07 9.79696e+06 3.17293e+06 2998.99 3.63 1.31183 1.20953 97261 632982 -1 20510 16 5114 12053 1254371 346946 4.98587 4.98587 -2932.2 -4.98587 0 0 4.15960e+06 3931.57 0.13 0.37 0.43 -1 -1 0.13 0.211188 0.200475 +non_column_wide_aspect_ratio.xml raygentop.v common 51.96 odin 1.93 GiB 39.01 2023148 -1 -1 3 0.85 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 97796 214 305 2963 2869 1 1441 650 43 22 946 io auto 47.7 MiB 2.33 32195 14077 256724 83624 150449 22651 94.0 MiB 0.93 0.01 6.20333 4.54267 -2819.04 -4.54267 4.54267 0.73 0.0036836 0.00338589 0.367728 0.337572 -1 -1 -1 -1 42 27740 26 4.55909e+07 9.79696e+06 2.29725e+06 2428.38 3.73 1.29545 1.19324 79978 445530 -1 23661 21 6769 17034 1969793 532017 5.2623 5.2623 -3159.48 -5.2623 0 0 2.89121e+06 3056.25 0.09 0.47 0.30 -1 -1 0.09 0.224632 0.211588 +custom_sbloc.xml raygentop.v common 23.30 odin 1.50 GiB 11.66 1574844 -1 -1 3 0.88 -1 -1 40248 -1 -1 123 214 0 8 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88296 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.2 MiB 2.37 24028 12399 225770 74858 132033 18879 86.2 MiB 0.88 0.01 5.49355 4.39465 -2699.44 -4.39465 4.39465 0.23 0.00384826 0.00355486 0.341246 0.313852 -1 -1 -1 -1 60 25212 46 1.65001e+07 9.79696e+06 1.11685e+06 3093.75 3.98 1.18851 1.09389 34801 214773 -1 20923 16 6158 14594 1766703 471535 4.72432 4.72432 -3000.62 -4.72432 0 0 1.41014e+06 3906.19 0.03 0.46 0.14 -1 -1 0.03 0.216305 0.205082 +multiple_io_types.xml raygentop.v common 100.46 odin 1.54 GiB 10.89 1613936 -1 -1 3 0.89 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 484240 214 305 2963 2869 1 1441 650 67 67 4489 io_left auto 46.3 MiB 2.79 60956 25475 99140 5163 24781 69196 472.9 MiB 0.47 0.01 9.23589 4.60777 -3590.83 -4.60777 4.60777 12.16 0.00424816 0.00393296 0.187025 0.172866 -1 -1 -1 -1 38 47769 50 2.48753e+08 9.79696e+06 9.69761e+06 2160.30 63.90 1.65141 1.51652 366081 1845534 -1 38574 21 9565 21545 4981287 1328871 5.11017 5.11017 -4030.7 -5.11017 0 0 1.23326e+07 2747.29 0.53 1.14 1.24 -1 -1 0.53 0.264959 0.248163 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt index 032d95a320..fcc259605f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 3.10 vpr 67.66 MiB 0.06 9856 -1 -1 3 0.38 -1 -1 39496 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69284 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.15 804 66963 21682 33533 11748 67.7 MiB 0.23 0.00 2.23767 -220.613 -2.23767 2.23767 0.25 0.00122229 0.00116469 0.0742124 0.0677305 -1 -1 -1 -1 38 1639 12 5.66058e+06 4.21279e+06 328943. 2284.32 0.72 0.298961 0.271262 12522 66188 -1 1359 8 559 726 39339 13482 2.60043 2.60043 -237.265 -2.60043 0 0 418267. 2904.63 0.03 0.05 0.11 -1 -1 0.03 0.0322868 0.0303399 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 4.22 odin 99.38 MiB 2.31 101760 -1 -1 3 0.22 -1 -1 34100 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68336 99 130 363 493 1 252 298 12 12 144 clb auto 27.5 MiB 0.07 2018 885 69948 23010 34855 12083 66.7 MiB 0.13 0.00 2.57832 2.17528 -217.156 -2.17528 2.17528 0.11 0.000768195 0.000732652 0.0469629 0.0440995 -1 -1 -1 -1 40 1651 16 5.66058e+06 4.21279e+06 343462. 2385.15 0.42 0.200686 0.184847 12666 68385 -1 1603 9 533 666 46991 15253 2.5852 2.5852 -243.226 -2.5852 0 0 431791. 2998.55 0.01 0.03 0.04 -1 -1 0.01 0.0172091 0.0161769 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt index a65248b7f3..d179e3150f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.43 vpr 64.82 MiB 0.05 9728 -1 -1 4 0.35 -1 -1 39692 -1 -1 75 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66380 99 130 378 508 1 307 305 15 15 225 memory auto 25.3 MiB 0.06 1083 69047 24301 32567 12179 64.8 MiB 0.22 0.01 1.63577 -172.755 -1.63577 1.63577 0.00 0.00106212 0.000958102 0.0684136 0.0626923 -1 -1 -1 -1 1479 6.03673 767 3.13061 797 1865 235419 59319 1.16234e+06 375248 2.18283e+06 9701.45 16 48952 428016 -1 1.89463 1.89463 -188.601 -1.89463 -0.194976 -0.108352 0.68 -1 -1 64.8 MiB 0.11 0.107667 0.0986163 64.8 MiB -1 0.37 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 3.69 odin 94.12 MiB 2.29 96384 -1 -1 4 0.21 -1 -1 34100 -1 -1 80 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64988 99 130 378 508 1 307 310 15 15 225 memory auto 23.6 MiB 0.03 2811 1131 73670 26591 35126 11953 63.5 MiB 0.14 0.00 1.90937 1.69007 -171.787 -1.69007 1.69007 0.00 0.000572698 0.000535082 0.0430164 0.0402085 -1 -1 -1 -1 1607 6.55918 824 3.36327 788 1831 251903 61748 1.16234e+06 394748 2.18283e+06 9701.45 13 48952 428016 -1 1.87081 1.87081 -179.525 -1.87081 0 0 0.29 -1 -1 63.5 MiB 0.05 0.0620738 0.0577834 63.5 MiB -1 0.14 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt index c044fb3663..dad7de4c97 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets - timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 16.11 vpr 77.95 MiB 0.11 17024 -1 -1 2 0.10 -1 -1 37392 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 79820 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.7 MiB 0.63 9390 201609 69489 120331 11789 76.8 MiB 1.40 0.02 4.09817 -3462.19 -4.09817 4.09817 1.75 0.00638402 0.00561878 0.639416 0.550497 -1 -1 -1 -1 36 15662 18 4.25198e+07 9.89071e+06 1.97160e+06 2514.80 6.39 2.29245 2.04057 76483 392267 -1 14444 15 3124 3650 1031496 356426 4.24327 4.24327 -4339.34 -4.24327 -405.202 -1.29702 2.42825e+06 3097.26 0.20 1.56 0.59 -1 -1 0.20 0.278119 0.255639 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 12.94 vpr 83.35 MiB 0.18 17024 -1 -1 2 0.12 -1 -1 37644 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 85352 311 156 1019 1160 1 965 513 28 28 784 memory auto 35.0 MiB 0.95 9390 201609 69489 120331 11789 83.4 MiB 0.81 0.01 4.09817 -3462.19 -4.09817 4.09817 1.06 0.00320533 0.00273182 0.351431 0.298654 -1 -1 -1 -1 36 15777 15 4.25198e+07 9.89071e+06 2.00618e+06 2558.90 4.74 1.57738 1.39763 76483 403003 -1 14373 10 2886 3379 762706 219312 4.3954 4.3954 -4595.94 -4.3954 -153.524 -1.32288 2.47848e+06 3161.33 0.22 1.20 0.50 -1 -1 0.22 0.199455 0.182428 15 950 - timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 20.64 vpr 78.23 MiB 0.14 17152 -1 -1 2 0.19 -1 -1 37392 -1 -1 31 311 15 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 80112 311 156 1019 1160 1 965 513 28 28 784 memory auto 35.0 MiB 0.82 8956 201609 71778 118284 11547 78.2 MiB 1.41 0.02 3.73942 -3418.22 -3.73942 3.73942 1.71 0.00607733 0.00531502 0.647808 0.554869 -1 -1 -1 -1 36 16279 32 4.25198e+07 9.89071e+06 1.96702e+06 2508.96 9.86 2.33237 2.04039 76483 392433 -1 15198 14 2704 3167 1739681 1219090 5.58949 5.58949 -4496.49 -5.58949 -1697.62 -3.42836 2.42368e+06 3091.42 0.20 2.25 0.55 -1 -1 0.20 0.242641 0.222883 15 950 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 12.73 odin 619.11 MiB 5.32 633968 -1 -1 2 0.10 -1 -1 33924 -1 -1 31 311 15 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78076 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.3 MiB 0.49 18226 8928 193401 64117 117643 11641 74.7 MiB 0.59 0.01 4.81013 3.67388 -3454.23 -3.67388 3.67388 0.69 0.00277864 0.00248689 0.278952 0.248388 -1 -1 -1 -1 40 14778 13 4.25198e+07 9.89071e+06 2.15543e+06 2749.27 2.56 0.936301 0.844347 78831 435646 -1 13800 11 2663 3052 814928 278609 4.53842 4.53842 -4454.28 -4.53842 -315.655 -1.23838 2.69266e+06 3434.52 0.09 0.60 0.25 -1 -1 0.09 0.0997977 0.0925211 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 12.74 odin 619.74 MiB 5.39 634616 -1 -1 2 0.10 -1 -1 33768 -1 -1 31 311 15 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 84996 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.3 MiB 0.49 18226 8928 193401 64117 117643 11641 78.9 MiB 0.58 0.01 4.81013 3.67388 -3454.23 -3.67388 3.67388 0.70 0.00261194 0.00231486 0.266487 0.235485 -1 -1 -1 -1 40 14952 13 4.25198e+07 9.89071e+06 2.19000e+06 2793.37 2.36 0.8856 0.792301 78831 446382 -1 13786 11 2650 3108 720747 217033 4.26762 4.26762 -4440.59 -4.26762 -135.258 -1.2599 2.74289e+06 3498.59 0.10 0.65 0.27 -1 -1 0.10 0.127014 0.117431 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_-start_odin_--clock_modeling_dedicated_network 14.12 odin 619.45 MiB 5.30 634312 -1 -1 2 0.10 -1 -1 33568 -1 -1 31 311 15 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 78824 311 156 1019 1160 1 965 513 28 28 784 memory auto 34.9 MiB 0.49 18226 9203 197505 67339 118442 11724 77.0 MiB 0.61 0.01 4.81013 3.956 -3512.79 -3.956 3.956 0.68 0.00273897 0.00243918 0.283578 0.250267 -1 -1 -1 -1 36 16669 23 4.25198e+07 9.89071e+06 1.96702e+06 2508.96 3.59 0.985182 0.87909 76483 392433 -1 15397 11 2678 3089 1644949 1134599 5.57406 5.57406 -4431.03 -5.57406 -1496.8 -3.14941 2.42368e+06 3091.42 0.09 1.00 0.22 -1 -1 0.09 0.104605 0.0976902 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt index 3e3e8b64dd..0c42c605c4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 16.94 vpr 71.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73360 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.5 MiB 0.26 10472 141533 36950 100839 3744 71.6 MiB 1.41 0.02 7.46482 -1369.01 -7.46482 7.46482 0.60 0.00534435 0.00471558 0.398834 0.330633 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.25 2.1497 1.834 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.04 0.76 0.21 -1 -1 0.04 0.209487 0.18755 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 6.27 vpr 69.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71428 64 39 1935 1974 1 1075 542 23 23 529 clb auto 30.7 MiB 0.19 24088 10407 135291 36283 95683 3325 69.8 MiB 0.70 0.01 23.0912 7.70338 -1562.28 -7.70338 7.70338 0.23 0.00335052 0.00288586 0.212378 0.185612 -1 -1 -1 -1 24 13067 26 983127 978669 797780. 1508.09 3.33 0.623267 0.54809 39018 137339 -1 11571 16 6466 23559 1530116 397333 7.70338 7.70338 -1636.85 -7.70338 0 0 1.04508e+06 1975.57 0.02 0.41 0.08 -1 -1 0.02 0.11517 0.10445 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt index 57a8e16dad..09ff7799b6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 26.42 vpr 86.55 MiB 0.39 29568 -1 -1 4 2.92 -1 -1 43300 -1 -1 169 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88632 193 205 2863 2789 1 1374 572 20 20 400 memory auto 45.3 MiB 1.96 10985 240245 81936 130873 27436 86.6 MiB 2.98 0.04 4.42447 -2617.73 -4.42447 4.42447 0.87 0.010731 0.00973575 1.17585 1.01795 -1 -1 -1 -1 78 21148 32 2.07112e+07 1.18481e+07 2.06176e+06 5154.39 12.21 3.92596 3.45972 52874 439520 -1 19015 16 5137 14374 1050969 231484 5.06231 5.06231 -2806.44 -5.06231 -11.1461 -0.341744 2.60035e+06 6500.87 0.19 0.81 0.45 -1 -1 0.19 0.495649 0.459932 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 25.04 odin 1.02 GiB 11.98 1071200 -1 -1 4 1.58 -1 -1 39396 -1 -1 165 193 5 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87476 193 205 2863 2789 1 1378 568 20 20 400 memory auto 45.1 MiB 1.16 22943 10817 247423 86121 133897 27405 85.4 MiB 1.40 0.02 6.47551 5.02579 -2678.97 -5.02579 5.02579 0.34 0.00434509 0.00394969 0.565479 0.512407 -1 -1 -1 -1 76 21112 33 2.07112e+07 1.16325e+07 2.02110e+06 5052.76 5.23 1.83755 1.67494 52074 423490 -1 19105 16 5044 13854 1088699 242536 5.48145 5.48145 -2895.27 -5.48145 -14.3689 -0.360359 2.51807e+06 6295.18 0.07 0.42 0.26 -1 -1 0.07 0.252321 0.236983 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt index 7d3c0c996a..30ff2d9d2e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.83 vpr 67.63 MiB 0.09 9984 -1 -1 3 0.34 -1 -1 39772 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69252 99 130 363 493 1 251 298 12 12 144 clb auto 28.5 MiB 0.20 804 66963 21682 33533 11748 67.6 MiB 0.34 0.01 2.23767 -220.613 -2.23767 2.23767 0.27 0.000902266 0.000807045 0.0650955 0.0583605 -1 -1 -1 -1 38 1665 16 5.66058e+06 4.21279e+06 319130. 2216.18 1.19 0.319458 0.291293 12522 62564 -1 1367 8 564 725 39208 13509 2.60043 2.60043 -237.701 -2.60043 0 0 406292. 2821.48 0.03 0.06 0.09 -1 -1 0.03 0.0273369 0.0256329 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.06 odin 100.12 MiB 2.24 102528 -1 -1 3 0.21 -1 -1 34096 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67488 99 130 363 493 1 252 298 12 12 144 clb auto 26.7 MiB 0.07 2018 885 69948 23010 34855 12083 65.9 MiB 0.12 0.00 2.57832 2.17528 -217.156 -2.17528 2.17528 0.10 0.000579426 0.000543768 0.0424701 0.039797 -1 -1 -1 -1 40 1646 17 5.66058e+06 4.21279e+06 333335. 2314.82 0.35 0.159844 0.146344 12666 64609 -1 1625 10 525 650 46110 15051 2.57635 2.57635 -244.199 -2.57635 0 0 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.0175606 0.0164624 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt index ceb027e03e..643bd38a29 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_40nm.xml stereovision0.v common 198.12 vpr 257.14 MiB 2.00 126464 -1 -1 5 139.65 -1 -1 78708 -1 -1 1337 157 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 263312 157 197 21024 21221 1 6369 1691 39 39 1521 clb auto 124.7 MiB 6.38 48812 948271 327778 599083 21410 257.1 MiB 9.39 0.13 3.8487 -15314.7 -3.8487 3.8487 8.33 0.0426525 0.0388129 3.00817 2.44576 -1 -1 -1 -1 38 60857 30 2.4642e+07 2.4066e+07 4.29790e+06 2825.71 13.17 9.3436 7.78726 119030 883757 -1 57009 24 29792 62484 2448958 439074 3.78459 3.78459 -15886.2 -3.78459 0 0 5.41627e+06 3561.00 0.27 2.25 0.65 -1 -1 0.27 1.68943 1.4738 - k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 201.99 vpr 255.40 MiB 2.14 126336 -1 -1 5 142.90 -1 -1 78972 -1 -1 1356 157 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 261528 157 197 21024 21221 1 6467 1710 39 39 1521 clb auto 124.6 MiB 7.21 49809 962484 334554 607807 20123 255.4 MiB 9.87 0.12 3.26114 -15027.4 -3.26114 3.26114 7.20 0.0351221 0.0281327 3.06287 2.48936 -1 -1 -1 -1 38 63075 34 7.37824e+07 7.30817e+07 4.16760e+06 2740.04 13.41 9.93144 8.27431 119030 845795 -1 59104 24 31762 70331 2621462 488165 3.1068 3.1068 -15929.2 -3.1068 0 0 5.22668e+06 3436.35 0.24 2.20 0.62 -1 -1 0.24 1.62443 1.4202 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_40nm.xml stereovision0.v common 192.79 odin 1.78 GiB 72.45 1866192 -1 -1 5 79.95 -1 -1 74308 -1 -1 1333 157 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 257100 157 197 21024 21221 1 6351 1687 39 39 1521 clb auto 136.4 MiB 3.13 183607 48717 965335 340609 600791 23935 251.1 MiB 7.13 0.07 8.3236 3.67149 -15448.9 -3.67149 3.67149 3.59 0.0208449 0.0183946 2.33967 1.95367 -1 -1 -1 -1 38 62381 33 2.4642e+07 2.3994e+07 4.29790e+06 2825.71 13.59 7.86508 6.6353 119030 883757 -1 57672 22 29914 63381 2482926 444293 3.4728 3.4728 -15928.1 -3.4728 0 0 5.41627e+06 3561.00 0.21 2.09 0.47 -1 -1 0.21 1.49835 1.34294 +k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 188.45 odin 1.78 GiB 67.67 1867908 -1 -1 5 80.91 -1 -1 74696 -1 -1 1329 157 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 259028 157 197 21024 21221 1 6395 1683 39 39 1521 clb auto 136.5 MiB 3.18 182137 48305 952348 332116 600539 19693 253.0 MiB 7.10 0.07 7.71591 3.21097 -14756.9 -3.21097 3.21097 3.62 0.0211325 0.0185694 2.328 1.93583 -1 -1 -1 -1 38 61719 36 7.37824e+07 7.16265e+07 4.16760e+06 2740.04 13.17 8.33502 7.01334 119030 845795 -1 58052 25 31719 70350 2555452 477654 3.64157 3.64157 -15795.2 -3.64157 0 0 5.22668e+06 3436.35 0.21 2.09 0.46 -1 -1 0.21 1.4967 1.31815 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt index 53aa221bde..7474f87790 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml test_eblif.eblif common 0.35 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 3 1 5 6 1 4 5 3 3 9 -1 auto 22.0 MiB 0.00 9 12 4 4 4 60.6 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 6.5921e-05 4.9487e-05 0.000173999 0.000134314 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.01 0.00172845 0.00161091 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.0015722 0.00153245 - k6_frac_N10_40nm.xml conn_order.eblif common 0.43 vpr 60.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61580 2 1 4 5 1 3 4 3 3 9 -1 auto 21.9 MiB 0.01 6 9 4 1 4 60.1 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.01 1.6713e-05 1.1905e-05 0.000118437 9.2123e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.01 0.00165899 0.00156225 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00153235 0.00149153 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml test_eblif.eblif common 0.29 vpr 58.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59568 3 1 5 6 1 4 5 3 3 9 -1 auto 19.7 MiB 0.00 9 9 12 4 4 4 58.2 MiB 0.00 0.00 0.52647 0.52647 -0.88231 -0.52647 0.52647 0.00 1.1014e-05 7.547e-06 8.7571e-05 6.8587e-05 -1 -1 -1 -1 20 9 2 53894 53894 4880.82 542.314 0.00 0.000972767 0.0009026 379 725 -1 5 1 3 3 29 19 0.545526 0.545526 -1.07365 -0.545526 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000931566 0.000898402 +k6_frac_N10_40nm.xml conn_order.eblif common 0.28 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60456 2 1 4 5 1 3 4 3 3 9 -1 auto 20.6 MiB 0.00 6 6 9 4 1 4 59.0 MiB 0.00 0.00 0.69084 0.69084 -1.21731 -0.69084 0.69084 0.00 1.0565e-05 7.12e-06 8.3404e-05 6.4898e-05 -1 -1 -1 -1 20 7 2 53894 53894 4880.82 542.314 0.00 0.00101172 0.000942555 379 725 -1 15 1 2 2 51 45 1.70808 1.70808 -2.25272 -1.70808 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.000925877 0.000893589 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt index c0c64f8d2c..07dab32856 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml eblif_write.eblif common 0.32 vpr 58.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60388 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 20.5 MiB 0.00 14 18 7 10 1 59.0 MiB 0.00 0.00 0.198536 -0.769354 -0.198536 0.198536 0.00 2.3959e-05 1.5869e-05 0.000131827 9.7152e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00165685 0.00154691 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00177312 0.00171917 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml eblif_write.eblif common 0.27 vpr 57.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58724 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 18.6 MiB 0.00 16 14 18 7 10 1 57.3 MiB 0.00 0.00 0.247067 0.198536 -0.769354 -0.198536 0.198536 0.00 1.3819e-05 8.442e-06 8.8035e-05 6.4514e-05 -1 -1 -1 -1 1 8 1 59253.6 29626.8 -1 -1 0.00 0.00122037 0.00113413 136 248 -1 8 1 4 4 68 40 0.189392 0.189392 -0.755508 -0.189392 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000897553 0.000861759 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt index c750dd5202..c272c7dff2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.53 vpr 66.67 MiB 0.08 10368 -1 -1 4 0.21 -1 -1 36920 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68272 11 30 262 292 2 99 60 7 7 49 clb auto 27.0 MiB 0.11 431 1932 256 1610 66 66.7 MiB 0.10 0.00 2.45279 -183.914 -2.45279 2.30526 0.00 0.000756181 0.000646522 0.0198618 0.0177275 -1 -1 -1 -1 -1 458 24 1.07788e+06 1.02399e+06 90369.8 1844.28 0.07 0.0693622 0.0613246 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.92 odin 166.88 MiB 2.86 170880 -1 -1 4 0.12 -1 -1 33232 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.07 688 427 2461 355 2028 78 65.7 MiB 0.07 0.00 2.92195 2.72416 -177.287 -2.72416 2.43773 0.00 0.0003934 0.000342762 0.0107271 0.00943758 -1 -1 -1 -1 -1 457 20 1.07788e+06 1.07788e+06 90369.8 1844.28 0.03 0.0311773 0.0272889 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt index 41d36d5dda..3e176724b2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - equivalent.xml equivalent.blif common 0.40 vpr 58.74 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60148 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 20.5 MiB 0.00 9 9 3 6 0 58.7 MiB 0.00 0.00 3.8649 -3.8649 -3.8649 nan 0.00 2.1313e-05 1.5936e-05 0.000108787 8.0593e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00168168 0.00158747 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00146867 0.00143048 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +equivalent.xml equivalent.blif common 0.28 vpr 57.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58424 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 18.7 MiB 0.00 11 9 9 3 6 0 57.1 MiB 0.00 0.00 3.98683 3.8649 -3.8649 -3.8649 nan 0.00 8.933e-06 5.625e-06 6.4132e-05 4.5255e-05 -1 -1 -1 -1 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00119903 0.00112309 72 304 -1 3 1 3 3 37 15 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000871788 0.000838483 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt index 41bceae31d..9548fe0472 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 2.46 vpr 66.34 MiB 0.09 10240 -1 -1 4 0.25 -1 -1 36836 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67932 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.10 417 1932 303 1579 50 66.3 MiB 0.03 0.00 2.45862 -181.765 -2.45862 2.33618 0.06 0.000452546 0.000389719 0.0170733 0.0149049 -1 -1 -1 -1 14 566 30 1.07788e+06 1.02399e+06 81563.3 1664.56 0.67 0.279658 0.24196 2472 22196 -1 446 21 890 1897 62387 19776 2.78119 2.51931 -191.416 -2.78119 0 0 98201.7 2004.12 0.00 0.07 0.02 -1 -1 0.00 0.0396875 0.0352228 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 4.78 odin 167.25 MiB 3.44 171264 -1 -1 4 0.13 -1 -1 33076 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67264 11 30 262 292 2 99 61 7 7 49 clb auto 25.7 MiB 0.04 688 429 2941 457 2408 76 65.7 MiB 0.02 0.00 2.93468 2.74942 -180.398 -2.74942 2.45106 0.02 0.000399659 0.000346833 0.0122033 0.0107426 -1 -1 -1 -1 16 538 33 1.07788e+06 1.07788e+06 88828.2 1812.82 0.14 0.0728439 0.0614584 2520 24504 -1 531 31 912 2238 78937 24519 2.94529 2.53849 -196.108 -2.94529 0 0 104221. 2126.97 0.00 0.04 0.01 -1 -1 0.00 0.0270377 0.0232596 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/apex2_block_locations.place b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/apex2_block_locations.place index 9813ce389c..84ede063b4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/apex2_block_locations.place +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/apex2_block_locations.place @@ -1,175 +1,181 @@ #block name x y subblk layer block number #---------- -- -- ------ ----- ------------ -o_1_ 4 3 2 0 #0 -o_2_ 1 1 2 0 #1 -o_0_ 1 4 4 0 #2 -n_n1827 2 2 3 0 #3 -n_n1829 1 2 5 0 #4 -n_n1812 1 1 3 0 #5 -n_n1866 1 3 4 0 #6 -n_n1865 1 2 4 0 #7 -[493] 4 5 2 0 #8 -n_n544 5 4 5 0 #9 -n_n416 4 1 4 0 #10 -n_n394 2 1 2 0 #11 -n_n391 2 1 3 0 #12 -n_n300 3 1 0 0 #13 -[260] 3 5 3 0 #14 -n_n437 3 3 3 0 #15 -[223] 5 4 1 0 #16 -[79] 3 5 0 0 #17 -[410] 2 4 1 0 #18 -[516] 4 5 4 0 #19 -[245] 3 4 2 0 #20 -[340] 2 5 5 0 #21 -[432] 2 4 5 0 #22 -[80] 3 4 1 0 #23 -[541] 5 3 5 0 #24 -n_n309 2 1 5 0 #25 -[8] 4 5 5 0 #26 -[546] 3 4 5 0 #27 -n_n706 1 2 3 0 #28 -[261] 2 2 1 0 #29 -[463] 4 4 3 0 #30 -n_n1575 3 5 4 0 #31 -n_n1571 2 4 3 0 #32 -[132] 1 5 3 0 #33 -[355] 2 4 2 0 #34 -[214] 4 4 5 0 #35 -[267] 5 4 4 0 #36 -n_n329 3 2 0 0 #37 -[420] 5 2 2 0 #38 -n_n849 2 2 5 0 #39 -[478] 5 4 0 0 #40 -[578] 4 1 3 0 #41 -[253] 4 2 0 0 #42 -[4] 4 1 5 0 #43 -[56] 1 1 4 0 #44 -[226] 3 1 2 0 #45 -[282] 1 3 3 0 #46 -[377] 1 2 1 0 #47 -[71] 1 1 1 0 #48 -[319] 5 2 5 0 #49 -[233] 4 3 1 0 #50 -[246] 3 4 4 0 #51 -[301] 3 5 1 0 #52 -[441] 5 5 0 0 #53 -[608] 5 4 3 0 #54 -[21] 2 1 4 0 #55 -[311] 4 4 1 0 #56 -[344] 3 2 2 0 #57 -[310] 2 2 2 0 #58 -[315] 1 3 2 0 #59 -[29] 1 4 0 0 #60 -[273] 2 4 4 0 #61 -n_n1690 3 4 0 0 #62 -[383] 5 3 1 0 #63 -[390] 2 2 4 0 #64 -[705] 4 4 4 0 #65 -[41] 4 3 5 0 #66 -[351] 4 1 1 0 #67 -[484] 4 2 1 0 #68 -[437] 5 3 4 0 #69 -[349] 3 2 4 0 #70 -[65] 3 5 5 0 #71 -[221] 4 5 1 0 #72 -[402] 2 4 0 0 #73 -[521] 4 1 0 0 #74 -[767] 4 1 2 0 #75 -[133] 2 5 0 0 #76 -[234] 4 3 4 0 #77 -[868] 1 4 3 0 #78 -[904] 4 4 2 0 #79 -[906] 4 2 4 0 #80 -[919] 2 3 3 0 #81 -[1253] 1 3 0 0 #82 -[1283] 3 1 3 0 #83 -[1340] 3 2 3 0 #84 -[1382] 1 1 0 0 #85 -[1404] 3 2 1 0 #86 -[1417] 3 1 1 0 #87 -[1534] 4 3 3 0 #88 -[1615] 3 5 2 0 #89 -[6947] 2 3 2 0 #90 -[7082] 4 3 0 0 #91 -[7159] 4 2 5 0 #92 -[7165] 5 3 2 0 #93 -[7191] 5 3 3 0 #94 -[7319] 3 3 0 0 #95 -[7321] 5 2 0 0 #96 -[7351] 2 3 4 0 #97 -[7388] 1 2 0 0 #98 -[7423] 2 1 0 0 #99 -[7466] 3 2 5 0 #100 -[7782] 4 4 0 0 #101 -[7822] 2 5 4 0 #102 -[7885] 2 5 3 0 #103 -[7888] 2 3 1 0 #104 -[7997] 5 5 2 0 #105 -[8027] 5 2 4 0 #106 -[50] 2 3 0 0 #107 -[288] 3 3 2 0 #108 -[539] 5 2 1 0 #109 -[372] 4 2 3 0 #110 -n_n1584 2 5 1 0 #111 -[196] 2 2 0 0 #112 -[585] 3 3 5 0 #113 -[365] 4 5 3 0 #114 -[492] 1 4 5 0 #115 -[616] 3 3 1 0 #116 -[430] 2 1 1 0 #117 -[663] 1 2 2 0 #118 -[700] 4 2 2 0 #119 -[322] 1 3 5 0 #120 -[739] 3 3 4 0 #121 -[745] 5 3 0 0 #122 -[771] 3 4 3 0 #123 -[95] 4 5 0 0 #124 -[345] 3 1 4 0 #125 -[759] 3 1 5 0 #126 -[1066] 1 3 1 0 #127 -[7199] 5 1 5 0 #128 -[7969] 5 5 3 0 #129 -[7328] 1 4 1 0 #130 -[7559] 5 2 3 0 #131 -out:o_1_ 3 6 1 0 #132 -out:o_2_ 1 0 5 0 #133 -out:o_0_ 1 6 2 0 #134 -i_30_ 3 6 3 0 #135 -i_20_ 4 0 6 0 #136 -i_9_ 3 0 5 0 #137 -i_10_ 0 1 4 0 #138 -i_7_ 2 6 7 0 #139 -i_8_ 3 0 7 0 #140 -i_5_ 2 0 1 0 #141 -i_6_ 3 0 0 0 #142 -i_27_ 4 6 4 0 #143 -i_14_ 2 6 5 0 #144 -i_3_ 3 0 2 0 #145 -i_28_ 2 0 3 0 #146 -i_13_ 2 0 2 0 #147 -i_4_ 3 0 6 0 #148 -i_25_ 1 0 0 0 #149 -i_12_ 2 0 0 0 #150 -i_1_ 4 0 3 0 #151 -i_26_ 1 0 7 0 #152 -i_11_ 4 0 5 0 #153 -i_2_ 3 0 3 0 #154 -i_23_ 4 6 7 0 #155 -i_18_ 4 0 1 0 #156 -i_24_ 2 0 7 0 #157 -i_17_ 4 0 2 0 #158 -i_0_ 2 6 3 0 #159 -i_21_ 5 6 5 0 #160 -i_16_ 4 6 2 0 #161 -i_22_ 1 0 4 0 #162 -i_32_ 4 0 4 0 #163 -i_31_ 2 0 5 0 #164 -i_34_ 3 6 5 0 #165 -i_33_ 1 0 3 0 #166 -i_19_ 6 1 1 0 #167 -i_36_ 3 6 7 0 #168 -i_35_ 2 0 6 0 #169 -i_38_ 3 0 4 0 #170 -i_29_ 2 6 4 0 #171 -i_37_ 4 6 1 0 #172 +o_1_ 4 1 4 0 #0 +o_2_ 4 3 4 0 #1 +o_0_ 2 2 0 0 #2 +n_n1829 3 5 4 0 #3 +n_n1812 5 3 5 0 #4 +n_n1866 4 5 1 0 #5 +n_n1865 4 5 3 0 #6 +[493] 2 1 2 0 #7 +n_n544 3 1 0 0 #8 +n_n416 4 4 0 0 #9 +n_n394 5 4 5 0 #10 +n_n391 5 3 4 0 #11 +n_n300 4 5 5 0 #12 +[260] 3 2 4 0 #13 +[223] 3 1 4 0 #14 +[79] 2 2 4 0 #15 +[410] 1 3 1 0 #16 +[516] 1 3 2 0 #17 +[530] 1 1 1 0 #18 +[245] 1 2 0 0 #19 +[340] 1 4 4 0 #20 +[432] 3 1 2 0 #21 +[533] 2 3 3 0 #22 +[80] 2 2 5 0 #23 +[535] 1 2 1 0 #24 +n_n316 4 2 4 0 #25 +[541] 1 2 5 0 #26 +n_n1563 2 2 1 0 #27 +n_n1585 2 3 4 0 #28 +[38] 2 3 2 0 #29 +n_n706 4 2 3 0 #30 +n_n608 2 1 1 0 #31 +[261] 4 1 0 0 #32 +[463] 5 1 3 0 #33 +n_n1578 1 2 3 0 #34 +[124] 2 3 1 0 #35 +[132] 3 3 2 0 #36 +[227] 1 1 3 0 #37 +[267] 2 2 2 0 #38 +n_n329 2 2 3 0 #39 +n_n849 4 5 0 0 #40 +[478] 2 3 0 0 #41 +[578] 5 5 0 0 #42 +[253] 5 3 2 0 #43 +[4] 5 4 3 0 #44 +[56] 4 4 3 0 #45 +[226] 4 2 5 0 #46 +[282] 5 4 2 0 #47 +[377] 5 5 4 0 #48 +[71] 5 3 3 0 #49 +[246] 3 2 1 0 #50 +[301] 3 1 1 0 #51 +[311] 4 4 4 0 #52 +[344] 4 4 1 0 #53 +[310] 4 2 2 0 #54 +[315] 4 3 0 0 #55 +[78] 3 5 5 0 #56 +[656] 5 3 0 0 #57 +[29] 2 4 1 0 #58 +[273] 3 1 3 0 #59 +[668] 1 2 4 0 #60 +[674] 5 3 1 0 #61 +[74] 1 2 2 0 #62 +n_n1704 4 1 3 0 #63 +[327] 4 5 2 0 #64 +[305] 1 4 3 0 #65 +n_n1702 4 1 5 0 #66 +[351] 5 2 3 0 #67 +[437] 3 3 3 0 #68 +[349] 5 1 5 0 #69 +[65] 1 1 0 0 #70 +[221] 2 1 5 0 #71 +[343] 3 4 5 0 #72 +[406] 5 2 5 0 #73 +[521] 5 4 0 0 #74 +[161] 3 1 5 0 #75 +[189] 2 4 2 0 #76 +[906] 2 4 3 0 #77 +[977] 4 3 5 0 #78 +[1340] 4 4 5 0 #79 +[1426] 5 2 1 0 #80 +[1435] 5 4 1 0 #81 +[1542] 4 3 3 0 #82 +[1615] 3 4 3 0 #83 +[1619] 4 1 2 0 #84 +[6958] 1 4 2 0 #85 +[7025] 5 2 4 0 #86 +[7082] 1 1 5 0 #87 +[7160] 3 2 2 0 #88 +[7319] 3 4 0 0 #89 +[7321] 4 5 4 0 #90 +[7388] 3 3 0 0 #91 +[7390] 3 5 2 0 #92 +[7787] 1 3 3 0 #93 +[7791] 2 3 5 0 #94 +[7811] 2 1 3 0 #95 +[7822] 4 2 0 0 #96 +[7829] 2 1 4 0 #97 +[7885] 3 4 4 0 #98 +[7899] 1 3 5 0 #99 +[7901] 1 1 4 0 #100 +[7997] 1 3 4 0 #101 +[8027] 2 1 0 0 #102 +[8042] 1 4 1 0 #103 +[50] 3 5 3 0 #104 +[307] 3 2 5 0 #105 +[275] 3 2 3 0 #106 +[372] 3 4 1 0 #107 +[503] 3 5 0 0 #108 +[585] 2 4 4 0 #109 +[63] 2 5 3 0 #110 +[431] 5 2 2 0 #111 +[447] 3 3 1 0 #112 +[615] 2 4 5 0 #113 +n_n1716 1 3 0 0 #114 +[254] 4 3 2 0 #115 +[381] 5 4 4 0 #116 +[430] 4 3 1 0 #117 +[276] 4 4 2 0 #118 +[760] 3 4 2 0 #119 +[768] 4 1 1 0 #120 +[792] 2 5 2 0 #121 +[721] 5 2 0 0 #122 +[877] 3 2 0 0 #123 +[884] 4 2 1 0 #124 +[1021] 3 3 5 0 #125 +[1077] 3 3 4 0 #126 +[1700] 1 4 0 0 #127 +[7108] 2 4 0 0 #128 +[7211] 5 1 1 0 #129 +[7516] 2 5 0 0 #130 +[7531] 2 5 4 0 #131 +[7820] 1 4 5 0 #132 +[7917] 2 5 5 0 #133 +[7028] 2 5 1 0 #134 +[7774] 1 5 5 0 #135 +[7778] 1 5 2 0 #136 +[177] 1 1 2 0 #137 +out:o_1_ 4 0 0 0 #138 +out:o_2_ 4 6 1 0 #139 +out:o_0_ 2 0 4 0 #140 +i_30_ 2 6 7 0 #141 +i_20_ 2 0 3 0 #142 +i_9_ 5 6 5 0 #143 +i_10_ 3 6 6 0 #144 +i_7_ 2 0 5 0 #145 +i_8_ 4 6 4 0 #146 +i_5_ 5 6 6 0 #147 +i_6_ 3 0 3 0 #148 +i_27_ 3 0 1 0 #149 +i_14_ 2 0 1 0 #150 +i_3_ 6 4 5 0 #151 +i_28_ 3 0 7 0 #152 +i_13_ 2 0 2 0 #153 +i_4_ 6 2 7 0 #154 +i_25_ 4 6 0 0 #155 +i_12_ 1 0 4 0 #156 +i_1_ 6 2 2 0 #157 +i_26_ 3 6 2 0 #158 +i_11_ 4 0 1 0 #159 +i_2_ 4 6 7 0 #160 +i_23_ 2 0 7 0 #161 +i_18_ 5 6 4 0 #162 +i_24_ 2 0 6 0 #163 +i_17_ 3 0 0 0 #164 +i_0_ 4 0 5 0 #165 +i_21_ 2 6 1 0 #166 +i_16_ 0 3 0 0 #167 +i_22_ 3 6 0 0 #168 +i_32_ 3 6 7 0 #169 +i_31_ 2 6 5 0 #170 +i_34_ 1 0 6 0 #171 +i_33_ 4 0 7 0 #172 +i_19_ 6 4 6 0 #173 +i_36_ 1 0 1 0 #174 +i_35_ 1 0 7 0 #175 +i_38_ 4 6 3 0 #176 +i_29_ 3 6 1 0 #177 +i_37_ 3 0 6 0 #178 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt index 76744275cd..4311d6f440 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_clusters/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fix_clusters_test_arch.xml apex2.blif common 15.55 vpr 74.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 132 38 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76704 38 3 1916 1919 0 1054 173 7 7 49 clb auto 34.1 MiB 5.08 5783 1135 0 0 1135 74.9 MiB 0.08 0.01 5.08129 -15.1527 -5.08129 nan 0.20 0.00521387 0.00456397 0.054855 0.0516446 -1 -1 -1 -1 164 7880 41 1.34735e+06 7.11401e+06 957298. 19536.7 8.09 2.3336 2.00198 18546 296938 -1 7311 19 6308 26453 1146687 361661 5.58525 nan -16.6102 -5.58525 0 0 1.19720e+06 24432.6 0.03 0.49 0.23 -1 -1 0.03 0.228213 0.208678 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fix_clusters_test_arch.xml apex2.blif common 8.49 vpr 71.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 138 38 -1 -1 success v8.0.0-12603-g0e7af78bf-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-02T15:24:02 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73684 38 3 1916 1919 0 1057 179 7 7 49 clb auto 32.6 MiB 2.55 5571 5572 1187 0 0 1187 72.0 MiB 0.04 0.00 4.76188 4.76188 -14.2451 -4.76188 nan 0.08 0.00205618 0.00185269 0.030602 0.0295235 -1 -1 -1 -1 158 7466 37 1.34735e+06 7.43737e+06 924312. 18863.5 4.39 1.09074 0.93946 18354 286522 -1 7089 17 5844 24589 1071101 337183 5.3663 nan -15.678 -5.3663 0 0 1.15416e+06 23554.3 0.02 0.28 0.14 -1 -1 0.02 0.138896 0.12896 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt index 2735c09358..8093e29b7f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 2.00 vpr 66.73 MiB 0.06 10368 -1 -1 4 0.21 -1 -1 36456 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68336 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.07 499 1698 69 1565 64 66.7 MiB 0.04 0.00 2.45489 -182.908 -2.45489 2.31533 0.06 0.000803566 0.000668095 0.0165762 0.0143795 -1 -1 -1 -1 18 719 39 1.07788e+06 1.02399e+06 45686.6 932.380 0.43 0.155736 0.134195 2616 8308 -1 605 32 901 2129 57619 17801 2.65666 2.40393 -192.483 -2.65666 0 0 59124.6 1206.62 0.00 0.09 0.01 -1 -1 0.00 0.062047 0.0552258 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.95 odin 167.62 MiB 2.55 171648 -1 -1 4 0.14 -1 -1 33080 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66548 11 30 262 292 2 99 61 7 7 49 clb auto 25.3 MiB 0.04 688 531 1981 91 1813 77 65.0 MiB 0.02 0.00 2.92675 2.71243 -182.607 -2.71243 2.42504 0.02 0.000416471 0.000357687 0.00968716 0.00854183 -1 -1 -1 -1 18 741 35 1.07788e+06 1.07788e+06 45686.6 932.380 0.18 0.0721732 0.060501 2616 8308 -1 669 22 765 1836 62890 21794 2.72374 2.48096 -195.552 -2.72374 0 0 59124.6 1206.62 0.00 0.04 0.00 -1 -1 0.00 0.0212961 0.0185098 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt index 03193b4299..65a8edefc2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - shorted_flyover_wires.xml raygentop.v common 26.23 vpr 87.18 MiB 0.37 31744 -1 -1 3 1.50 -1 -1 43564 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89276 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 46.2 MiB 4.36 11021 242654 80011 140532 22111 87.2 MiB 2.29 0.03 4.72515 -2651.47 -4.72515 4.72515 0.68 0.00870927 0.00789125 0.867466 0.775905 -1 -1 -1 -1 58 24978 46 1.65001e+07 9.79696e+06 1.00638e+06 2787.76 11.26 3.56546 3.21933 34441 208101 -1 21032 16 5966 14058 1826516 536884 5.22938 5.22938 -3010.82 -5.22938 0 0 1.28387e+06 3556.43 0.10 1.10 0.34 -1 -1 0.10 0.47794 0.447984 - buffered_flyover_wires.xml raygentop.v common 23.64 vpr 87.26 MiB 0.39 31872 -1 -1 3 1.51 -1 -1 43828 -1 -1 123 214 0 8 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 89352 214 305 2963 2869 1 1444 650 19 19 361 io clb auto 45.9 MiB 4.72 11369 231398 74152 135293 21953 87.3 MiB 2.16 0.03 4.81413 -2746.12 -4.81413 4.81413 0.60 0.00796315 0.00714187 0.791566 0.711054 -1 -1 -1 -1 64 23029 28 1.65001e+07 9.79696e+06 1.15406e+06 3196.84 8.51 3.3002 2.94744 35881 226057 -1 19740 15 5519 12704 1627954 469106 4.80072 4.80072 -2914.34 -4.80072 0 0 1.44847e+06 4012.38 0.10 0.92 0.36 -1 -1 0.10 0.422967 0.392398 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +shorted_flyover_wires.xml raygentop.v common 22.87 odin 1.54 GiB 11.39 1614048 -1 -1 3 0.85 -1 -1 40256 -1 -1 123 214 0 8 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88144 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.1 MiB 2.33 24028 11417 245468 84522 140289 20657 86.1 MiB 0.95 0.01 5.44161 4.44985 -2711.83 -4.44985 4.44985 0.23 0.00365636 0.00337393 0.360318 0.330434 -1 -1 -1 -1 62 24833 45 1.65001e+07 9.79696e+06 1.07728e+06 2984.15 3.96 1.42118 1.30957 35161 217957 -1 21028 18 6730 15878 2433481 654279 5.215 5.215 -3026.13 -5.215 0 0 1.33769e+06 3705.50 0.04 0.50 0.14 -1 -1 0.04 0.208236 0.196927 +buffered_flyover_wires.xml raygentop.v common 22.36 odin 1.54 GiB 10.71 1614412 -1 -1 3 0.86 -1 -1 40260 -1 -1 123 214 0 8 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 88688 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 46.6 MiB 2.30 24520 12150 245468 84299 140070 21099 86.6 MiB 0.93 0.02 5.76052 4.50441 -2846.22 -4.50441 4.50441 0.22 0.00376258 0.00341339 0.358441 0.328763 -1 -1 -1 -1 64 25856 29 1.65001e+07 9.79696e+06 1.15406e+06 3196.84 4.15 1.38176 1.27052 35881 226057 -1 21156 15 6633 15933 2219536 617587 4.97633 4.97633 -3163.74 -4.97633 0 0 1.44847e+06 4012.38 0.04 0.51 0.14 -1 -1 0.04 0.197935 0.186867 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt index b90ac6049e..66ecb88632 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - hard_fpu_arch_timing.xml mm3.v common 3.31 vpr 64.39 MiB 0.03 7296 -1 -1 1 0.04 -1 -1 34228 -1 -1 0 193 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 65940 193 32 545 422 1 289 227 21 21 441 io auto 25.0 MiB 1.91 3735 46591 19762 26388 441 64.4 MiB 0.33 0.00 2.985 -824.634 -2.985 2.985 0.00 0.00288823 0.00269357 0.190083 0.178688 -1 -1 -1 -1 4590 15.9375 1212 4.20833 431 431 162323 43530 809148 68766.3 979092. 2220.16 5 24050 197379 -1 2.985 2.985 -813.802 -2.985 -21.7856 -0.0851 0.43 -1 -1 64.4 MiB 0.09 0.239729 0.22641 64.4 MiB -1 0.09 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +hard_fpu_arch_timing.xml mm3.v common 3.37 odin 76.88 MiB 2.13 78720 -1 -1 1 0.03 -1 -1 30252 -1 -1 0 193 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64072 193 32 545 422 1 289 227 21 21 441 io auto 23.0 MiB 0.41 5010 3747 45899 19410 26043 446 62.6 MiB 0.14 0.00 2.985 2.985 -824.872 -2.985 2.985 0.00 0.00104171 0.000984304 0.0749863 0.0708592 -1 -1 -1 -1 4610 16.0069 1211 4.20486 431 431 145305 38673 809148 68766.3 979092. 2220.16 6 24050 197379 -1 2.985 2.985 -813.692 -2.985 -21.8252 -0.0851 0.14 -1 -1 62.6 MiB 0.04 0.0964117 0.091324 62.6 MiB -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt index 356e91ccb3..d3d7298256 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 3.01 vpr 67.75 MiB 0.06 9728 -1 -1 3 0.26 -1 -1 39908 -1 -1 69 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69380 99 130 363 493 1 251 299 13 13 169 clb auto 28.2 MiB 0.66 756 79220 19640 31087 28493 67.8 MiB 0.16 0.00 36 1238 7 0 0 481804. 2850.91 0.62 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 4.22 odin 102.38 MiB 2.40 104832 -1 -1 3 0.20 -1 -1 34100 -1 -1 71 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68284 99 130 363 493 1 251 301 13 13 169 clb auto 26.6 MiB 0.42 2129 766 78925 23058 31147 24720 66.7 MiB 0.06 0.00 34 1460 7 0 0 460544. 2725.11 0.25 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt index a8ea974737..755c112c6c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.21 vpr 66.19 MiB 0.08 10368 -1 -1 4 0.19 -1 -1 36516 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67780 11 30 262 292 2 99 60 7 7 49 clb auto 27.2 MiB 0.09 431 1932 256 1610 66 66.2 MiB 0.04 0.00 2.45279 -183.914 -2.45279 2.30526 0.00 0.000582727 0.000489391 0.0185537 0.0162573 -1 -1 -1 -1 -1 458 24 1.07788e+06 1.02399e+06 90369.8 1844.28 0.07 0.0660847 0.0581726 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.52 odin 167.25 MiB 2.57 171264 -1 -1 4 0.13 -1 -1 33120 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67264 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 427 2461 355 2028 78 65.7 MiB 0.02 0.00 2.92195 2.72416 -177.287 -2.72416 2.43773 0.00 0.000406539 0.000354742 0.0109243 0.00961111 -1 -1 -1 -1 -1 457 20 1.07788e+06 1.07788e+06 90369.8 1844.28 0.03 0.0315309 0.0275957 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt index 265af1c4b6..985d6e2f7a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.39 vpr 60.20 MiB -1 -1 -1 -1 0 0.02 -1 -1 33040 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61648 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.9 MiB 0.00 0 3 0 0 3 60.2 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1661e-05 6.33e-06 7.7033e-05 5.0742e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00147387 0.00140823 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.38 vpr 60.24 MiB -1 -1 -1 -1 0 0.02 -1 -1 32912 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61684 -1 1 1 2 0 1 2 3 3 9 -1 auto 21.9 MiB 0.00 0 3 0 0 3 60.2 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1339e-05 5.859e-06 8.8591e-05 5.8829e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00162493 0.00154875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.37 vpr 60.46 MiB -1 -1 -1 -1 0 0.02 -1 -1 32868 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 6 1 1 8 0 1 8 3 3 9 -1 auto 22.1 MiB 0.00 0 21 0 10 11 60.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3541e-05 7.635e-06 8.6471e-05 5.7499e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00150205 0.00143129 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.38 vpr 60.58 MiB -1 -1 -1 -1 0 0.02 -1 -1 32612 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 6 1 1 8 0 1 8 3 3 9 -1 auto 22.3 MiB 0.00 0 21 0 10 11 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.7003e-05 9.772e-06 9.7802e-05 6.5568e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.00166482 0.00158779 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and.blif common 0.39 vpr 60.29 MiB -1 -1 -1 -1 1 0.03 -1 -1 33040 -1 -1 1 2 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61732 2 1 3 4 0 3 4 3 3 9 -1 auto 21.9 MiB 0.00 9 9 3 3 3 60.3 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 1.5758e-05 1.1048e-05 0.000114967 8.6726e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00169019 0.00161423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.50 vpr 60.59 MiB -1 -1 -1 -1 1 0.05 -1 -1 34804 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.5271e-05 1.9684e-05 0.000266101 0.000119821 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00203214 0.00174712 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.51 vpr 60.46 MiB -1 -1 -1 -1 1 0.05 -1 -1 35364 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61908 5 1 6 7 0 6 7 3 3 9 -1 auto 22.0 MiB 0.00 18 18 13 5 0 60.5 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.0382e-05 1.5156e-05 0.000144485 0.00011379 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00203203 0.0018606 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml and_latch.blif common 0.35 vpr 60.57 MiB -1 -1 -1 -1 1 0.02 -1 -1 33216 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 3 1 5 6 1 4 5 3 3 9 -1 auto 22.1 MiB 0.00 9 12 7 1 4 60.6 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.8755e-05 1.3531e-05 0.00012903 9.8796e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.00153901 0.00145183 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml false_path_mux.blif common 0.50 vpr 60.45 MiB -1 -1 -1 -1 1 0.06 -1 -1 35348 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61904 4 1 4 6 0 4 6 3 3 9 -1 auto 22.1 MiB 0.00 12 15 9 3 3 60.5 MiB 0.00 0.00 0.67231 -0.67231 -0.67231 nan 0.00 2.3369e-05 1.7039e-05 0.000173745 0.000138562 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00205463 0.00186426 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_2x2.blif common 0.47 vpr 60.48 MiB -1 -1 -1 -1 1 0.06 -1 -1 35020 -1 -1 1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61928 4 4 8 12 0 8 9 3 3 9 -1 auto 22.1 MiB 0.00 24 27 18 6 3 60.5 MiB 0.00 0.00 0.67231 -2.68924 -0.67231 nan 0.00 3.869e-05 2.9429e-05 0.000257326 0.00021682 -1 -1 -1 -1 -1 10 10 53894 53894 38783.3 4309.26 0.00 0.00244349 0.00222744 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x3.blif common 0.51 vpr 60.62 MiB -1 -1 -1 -1 1 0.07 -1 -1 36084 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62076 6 6 12 18 0 12 13 3 3 9 -1 auto 22.1 MiB 0.01 36 43 32 7 4 60.6 MiB 0.00 0.00 0.69831 -4.13786 -0.69831 nan 0.00 7.4526e-05 6.3137e-05 0.000498869 0.000443741 -1 -1 -1 -1 -1 17 12 53894 53894 38783.3 4309.26 0.00 0.00383316 0.00343212 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_3x4.blif common 0.55 vpr 60.62 MiB -1 -1 -1 -1 2 0.07 -1 -1 35568 -1 -1 3 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62076 7 8 22 30 0 15 18 4 4 16 clb auto 22.1 MiB 0.01 51 64 26 37 1 60.6 MiB 0.00 0.00 1.24888 -7.62396 -1.24888 nan 0.00 9.8331e-05 8.571e-05 0.000766204 0.000700688 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.00447879 0.00416054 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_4x4.blif common 0.55 vpr 60.55 MiB -1 -1 -1 -1 4 0.08 -1 -1 35668 -1 -1 2 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62004 8 8 29 37 0 21 18 4 4 16 clb auto 22.0 MiB 0.02 74 64 20 44 0 60.6 MiB 0.00 0.00 2.04839 -11.7951 -2.04839 nan 0.00 0.000135237 0.000115292 0.00112979 0.00104286 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.01 0.00691358 0.00626039 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x5.blif common 0.61 vpr 60.96 MiB -1 -1 -1 -1 4 0.10 -1 -1 36048 -1 -1 4 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62424 10 10 47 57 0 39 24 4 4 16 clb auto 22.1 MiB 0.02 149 92 35 57 0 61.0 MiB 0.00 0.00 2.73035 -18.1288 -2.73035 nan 0.00 0.000225575 0.000203726 0.00149243 0.00139063 -1 -1 -1 -1 -1 123 10 215576 215576 99039.1 6189.95 0.01 0.00763482 0.00712644 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml mult_5x6.blif common 0.83 vpr 60.83 MiB -1 -1 -1 -1 5 0.15 -1 -1 36408 -1 -1 5 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62288 11 11 61 72 0 51 27 5 5 25 clb auto 21.9 MiB 0.03 192 547 116 431 0 60.8 MiB 0.01 0.00 3.17925 -21.2667 -3.17925 nan 0.00 0.000354484 0.000320379 0.00678629 0.00617992 -1 -1 -1 -1 -1 163 16 485046 269470 186194. 7447.77 0.02 0.0240229 0.0219824 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_1bit.blif common 0.49 vpr 60.46 MiB -1 -1 -1 -1 1 0.06 -1 -1 34452 -1 -1 1 3 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61912 3 2 5 7 0 5 6 3 3 9 -1 auto 22.0 MiB 0.00 15 15 9 5 1 60.5 MiB 0.00 0.00 0.67231 -1.34462 -0.67231 nan 0.00 3.2064e-05 2.4155e-05 0.000200579 0.000160863 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00242941 0.00220554 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_2bit.blif common 0.46 vpr 60.28 MiB -1 -1 -1 -1 1 0.06 -1 -1 35352 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61728 5 3 8 11 0 8 9 3 3 9 -1 auto 21.9 MiB 0.00 24 27 21 6 0 60.3 MiB 0.00 0.00 0.67231 -2.01693 -0.67231 nan 0.00 3.5791e-05 2.5977e-05 0.000240831 0.000201092 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00270512 0.00243979 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_3bit.blif common 0.52 vpr 60.61 MiB -1 -1 -1 -1 2 0.06 -1 -1 35400 -1 -1 1 7 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62060 7 4 12 16 0 11 12 3 3 9 -1 auto 22.3 MiB 0.01 33 38 24 11 3 60.6 MiB 0.00 0.00 1.08437 -4.00246 -1.08437 nan 0.00 4.7612e-05 3.9433e-05 0.000326091 0.000287024 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00528941 0.00513278 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_4bit.blif common 0.64 vpr 60.55 MiB -1 -1 -1 -1 2 0.07 -1 -1 35520 -1 -1 1 9 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62008 9 5 15 20 0 14 15 3 3 9 -1 auto 22.2 MiB 0.01 42 51 29 17 5 60.6 MiB 0.00 0.00 1.00731 -4.36655 -1.00731 nan 0.00 8.1588e-05 7.0424e-05 0.000516653 0.000461489 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.01 0.00432254 0.00385687 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml rca_5bit.blif common 0.56 vpr 60.67 MiB -1 -1 -1 -1 3 0.07 -1 -1 35440 -1 -1 1 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62124 11 6 19 25 0 17 18 3 3 9 -1 auto 22.1 MiB 0.01 51 64 33 24 7 60.7 MiB 0.00 0.00 1.34231 -6.71386 -1.34231 nan 0.00 5.6728e-05 4.4391e-05 0.000433977 0.000387108 -1 -1 -1 -1 -1 25 11 53894 53894 38783.3 4309.26 0.00 0.00412344 0.0036326 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.32 vpr 58.18 MiB -1 -1 -1 -1 0 0.02 -1 -1 29676 -1 -1 1 0 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59572 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.4 MiB 0.00 0 0 3 0 0 3 58.2 MiB 0.00 0.00 nan nan 0 0 nan 0.00 6.912e-06 3.191e-06 5.4323e-05 3.6258e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000869388 0.000818801 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.35 vpr 58.39 MiB -1 -1 -1 -1 0 0.02 -1 -1 29676 -1 -1 1 0 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59788 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.6 MiB 0.00 0 0 3 0 0 3 58.4 MiB 0.00 0.00 nan nan 0 0 nan 0.00 6.953e-06 3.324e-06 6.0434e-05 4.1215e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000900109 0.000846276 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.34 vpr 58.16 MiB -1 -1 -1 -1 0 0.02 -1 -1 29952 -1 -1 1 0 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59560 6 1 1 8 0 1 8 3 3 9 -1 auto 19.4 MiB 0.00 0 0 21 0 10 11 58.2 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.728e-06 3.779e-06 5.6927e-05 3.7781e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000875271 0.000824006 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.34 vpr 58.49 MiB -1 -1 -1 -1 0 0.02 -1 -1 29952 -1 -1 1 0 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59892 6 1 1 8 0 1 8 3 3 9 -1 auto 19.7 MiB 0.00 0 0 21 0 10 11 58.5 MiB 0.00 0.00 nan nan 0 0 nan 0.00 7.67e-06 3.755e-06 5.407e-05 3.4606e-05 -1 -1 -1 -1 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000883508 0.000832213 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and.blif common 0.35 vpr 58.67 MiB -1 -1 -1 -1 1 0.02 -1 -1 30336 -1 -1 1 2 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 2 1 3 4 0 3 4 3 3 9 -1 auto 20.2 MiB 0.00 9 9 9 3 3 3 58.7 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 8.934e-06 5.477e-06 7.5979e-05 5.5051e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.000932179 0.000873485 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.39 vpr 59.02 MiB -1 -1 -1 -1 1 0.03 -1 -1 31872 -1 -1 1 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60440 5 1 6 7 0 6 7 3 3 9 -1 auto 20.2 MiB 0.00 18 18 18 13 5 0 59.0 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.1726e-05 8.243e-06 9.5168e-05 7.5133e-05 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00116458 0.00104391 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.40 vpr 59.04 MiB -1 -1 -1 -1 1 0.03 -1 -1 31460 -1 -1 1 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 5 1 6 7 0 6 7 3 3 9 -1 auto 20.2 MiB 0.00 18 18 18 13 5 0 59.0 MiB 0.00 0.00 0.749366 0.67231 -0.67231 -0.67231 nan 0.00 1.7782e-05 1.4011e-05 0.000102036 8.1196e-05 -1 -1 -1 -1 -1 7 12 53894 53894 38783.3 4309.26 0.00 0.00113779 0.00102348 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and_latch.blif common 0.30 vpr 59.04 MiB -1 -1 -1 -1 1 0.02 -1 -1 30348 -1 -1 1 3 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60460 3 1 5 6 1 4 5 3 3 9 -1 auto 20.2 MiB 0.00 9 9 12 7 1 4 59.0 MiB 0.00 0.00 0.603526 0.52647 -0.88231 -0.52647 0.52647 0.00 1.071e-05 7.269e-06 9.5981e-05 7.4232e-05 -1 -1 -1 -1 -1 4 1 53894 53894 38783.3 4309.26 0.00 0.000989233 0.000927378 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml false_path_mux.blif common 0.38 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0.749366 0.67231 -2.68924 -0.67231 nan 0.00 1.9582e-05 1.4101e-05 0.00016501 0.000139818 -1 -1 -1 -1 -1 12 10 53894 53894 38783.3 4309.26 0.00 0.00141198 0.00128363 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x3.blif common 0.41 vpr 59.07 MiB -1 -1 -1 -1 1 0.04 -1 -1 31964 -1 -1 1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60492 6 6 12 18 0 12 13 3 3 9 -1 auto 20.6 MiB 0.00 36 36 43 32 7 4 59.1 MiB 0.00 0.00 0.775365 0.69831 -4.13786 -0.69831 nan 0.00 2.6944e-05 2.2668e-05 0.000255785 0.000229639 -1 -1 -1 -1 -1 15 12 53894 53894 38783.3 4309.26 0.00 0.00187416 0.00169167 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x4.blif common 0.41 vpr 58.84 MiB -1 -1 -1 -1 2 0.04 -1 -1 32088 -1 -1 3 7 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60252 7 8 22 30 0 15 18 4 4 16 clb auto 20.2 MiB 0.01 62 51 64 26 37 1 58.8 MiB 0.00 0.00 1.24888 1.24888 -7.62396 -1.24888 nan 0.00 4.8763e-05 4.2766e-05 0.000476005 0.000445315 -1 -1 -1 -1 -1 37 6 215576 161682 99039.1 6189.95 0.00 0.00254663 0.00237208 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_4x4.blif common 0.44 vpr 58.72 MiB -1 -1 -1 -1 4 0.05 -1 -1 32472 -1 -1 2 8 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60128 8 8 29 37 0 21 18 4 4 16 clb auto 19.7 MiB 0.01 82 74 64 20 44 0 58.7 MiB 0.00 0.00 2.04839 2.04839 -11.7951 -2.04839 nan 0.00 6.5797e-05 5.6879e-05 0.000645839 0.000608138 -1 -1 -1 -1 -1 53 12 215576 107788 99039.1 6189.95 0.00 0.0038309 0.00350874 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x5.blif common 0.48 vpr 58.89 MiB -1 -1 -1 -1 4 0.06 -1 -1 32828 -1 -1 4 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60308 10 10 47 57 0 39 24 4 4 16 clb auto 20.1 MiB 0.01 161 149 92 35 57 0 58.9 MiB 0.00 0.00 2.80144 2.73035 -18.1288 -2.73035 nan 0.00 9.861e-05 8.9144e-05 0.000993051 0.000941145 -1 -1 -1 -1 -1 120 10 215576 215576 99039.1 6189.95 0.01 0.0052426 0.00484221 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x6.blif common 0.57 vpr 59.55 MiB -1 -1 -1 -1 5 0.07 -1 -1 32924 -1 -1 5 11 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60984 11 11 61 72 0 49 27 5 5 25 clb auto 20.6 MiB 0.02 227 192 427 90 337 0 59.6 MiB 0.00 0.00 3.28962 3.19291 -21.0185 -3.19291 nan 0.00 0.000131237 0.000120239 0.0024536 0.00228981 -1 -1 -1 -1 -1 193 14 485046 269470 186194. 7447.77 0.01 0.00892117 0.00812875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_1bit.blif common 0.38 vpr 58.67 MiB -1 -1 -1 -1 1 0.03 -1 -1 31072 -1 -1 1 3 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60076 3 2 5 7 0 5 6 3 3 9 -1 auto 20.2 MiB 0.00 15 15 15 9 5 1 58.7 MiB 0.00 0.00 0.749366 0.67231 -1.34462 -0.67231 nan 0.00 1.2588e-05 9.103e-06 9.9841e-05 7.8482e-05 -1 -1 -1 -1 -1 6 12 53894 53894 38783.3 4309.26 0.00 0.00116119 0.00104412 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_2bit.blif common 0.39 vpr 59.05 MiB -1 -1 -1 -1 1 0.03 -1 -1 32248 -1 -1 1 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60472 5 3 8 11 0 8 9 3 3 9 -1 auto 20.2 MiB 0.00 24 24 27 21 6 0 59.1 MiB 0.00 0.00 0.749366 0.67231 -2.01693 -0.67231 nan 0.00 1.9232e-05 1.3994e-05 0.000149737 0.00012651 -1 -1 -1 -1 -1 10 16 53894 53894 38783.3 4309.26 0.00 0.00145192 0.00129567 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_3bit.blif common 0.40 vpr 58.32 MiB -1 -1 -1 -1 2 0.03 -1 -1 32244 -1 -1 1 7 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59724 7 4 12 16 0 11 12 3 3 9 -1 auto 19.9 MiB 0.00 33 33 38 24 11 3 58.3 MiB 0.00 0.00 1.08437 1.08437 -4.00246 -1.08437 nan 0.00 2.8392e-05 2.3838e-05 0.000201616 0.000178069 -1 -1 -1 -1 -1 17 4 53894 53894 38783.3 4309.26 0.00 0.00139416 0.00129866 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_4bit.blif common 0.40 vpr 59.11 MiB -1 -1 -1 -1 2 0.03 -1 -1 32252 -1 -1 1 9 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60524 9 5 15 20 0 14 15 3 3 9 -1 auto 20.2 MiB 0.00 42 42 51 29 17 5 59.1 MiB 0.00 0.00 1.08437 1.00731 -4.36655 -1.00731 nan 0.00 2.7611e-05 2.2779e-05 0.000249521 0.000223481 -1 -1 -1 -1 -1 17 14 53894 53894 38783.3 4309.26 0.00 0.00204134 0.00184801 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_5bit.blif common 0.39 vpr 59.13 MiB -1 -1 -1 -1 3 0.04 -1 -1 32248 -1 -1 1 11 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60548 11 6 19 25 0 17 18 3 3 9 -1 auto 20.2 MiB 0.00 51 51 64 36 21 7 59.1 MiB 0.00 0.00 1.41937 1.34231 -6.71386 -1.34231 nan 0.00 3.4593e-05 2.804e-05 0.000298489 0.000270122 -1 -1 -1 -1 -1 21 11 53894 53894 38783.3 4309.26 0.00 0.00202423 0.0018334 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt index 33183dc0a9..1f7539b7b4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml const_true.blif common 0.33 vpr 60.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62024 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.3 MiB 0.00 0 3 0 0 3 60.6 MiB 0.00 0.00 nan 0 0 nan 0.00 1.3821e-05 7.858e-06 8.9635e-05 6.0426e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00127569 0.00120513 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml const_false.blif common 0.27 vpr 60.31 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61760 -1 1 1 2 0 1 2 3 3 9 -1 auto 22.0 MiB 0.00 0 3 0 0 3 60.3 MiB 0.00 0.00 nan 0 0 nan 0.00 1.2203e-05 6.662e-06 7.9048e-05 5.258e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.00167909 0.00160437 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_true.blif common 0.30 vpr 60.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61712 6 1 7 8 0 7 8 3 3 9 -1 auto 22.1 MiB 0.00 21 21 14 7 0 60.3 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 3.2696e-05 2.3426e-05 0.000197822 0.000159059 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.0018336 0.0017293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml always_false.blif common 0.27 vpr 60.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62036 6 1 7 8 0 7 8 3 3 9 -1 auto 22.3 MiB 0.00 21 21 14 7 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.7376e-05 1.9376e-05 0.000172772 0.000138442 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00173443 0.0016423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.26 vpr 60.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61804 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.4 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.1966e-05 1.6158e-05 0.000132177 0.000102284 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00191949 0.00184253 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.34 vpr 60.59 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62040 5 1 6 7 0 6 7 3 3 9 -1 auto 22.1 MiB 0.00 18 18 13 5 0 60.6 MiB 0.00 0.00 0.69831 -0.69831 -0.69831 nan 0.00 2.5373e-05 1.8911e-05 0.000175189 0.000138808 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00175813 0.00166803 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.23 vpr 58.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60072 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.9 MiB 0.00 0 0 3 0 0 3 58.7 MiB 0.00 0.00 nan nan 0 0 nan 0.00 6.973e-06 3.123e-06 5.231e-05 3.349e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000854571 0.000803149 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.23 vpr 58.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59872 -1 1 1 2 0 1 2 3 3 9 -1 auto 19.7 MiB 0.00 0 0 3 0 0 3 58.5 MiB 0.00 0.00 nan nan 0 0 nan 0.00 6.791e-06 3.078e-06 5.4255e-05 3.5665e-05 -1 -1 -1 -1 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000868615 0.000818215 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.23 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60456 6 1 7 8 0 7 8 3 3 9 -1 auto 20.2 MiB 0.00 21 21 21 14 7 0 59.0 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.3494e-05 8.753e-06 0.000100498 8.0166e-05 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.00100186 0.000942223 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.22 vpr 58.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60068 6 1 7 8 0 7 8 3 3 9 -1 auto 19.8 MiB 0.00 21 21 21 14 7 0 58.7 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.3653e-05 8.941e-06 0.000104956 8.4056e-05 -1 -1 -1 -1 -1 10 1 53894 53894 20487.3 2276.37 0.00 0.0010448 0.000983594 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.25 vpr 59.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60456 5 1 6 7 0 6 7 3 3 9 -1 auto 20.6 MiB 0.00 18 18 18 13 5 0 59.0 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.2418e-05 8.794e-06 9.9356e-05 7.8577e-05 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00095621 0.000897186 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.23 vpr 58.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 60072 5 1 6 7 0 6 7 3 3 9 -1 auto 20.2 MiB 0.00 18 18 18 13 5 0 58.7 MiB 0.00 0.00 0.775365 0.69831 -0.69831 -0.69831 nan 0.00 1.2428e-05 8.885e-06 0.000101011 7.9941e-05 -1 -1 -1 -1 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00100002 0.000940289 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt index eaf5555874..ed90112915 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - x_gaussian_y_uniform.xml stereovision3.v common 1.83 vpr 66.90 MiB 0.07 10496 -1 -1 4 0.18 -1 -1 36452 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68504 11 30 262 292 2 110 54 7 7 49 clb auto 28.0 MiB 0.20 415 2196 413 1711 72 66.9 MiB 0.04 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.0007561 0.000646489 0.0218848 0.0192021 -1 -1 -1 -1 12 302 11 1.07788e+06 700622 -1 -1 0.20 0.128028 0.113742 2680 3516 -1 297 3 164 241 11232 5767 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0191965 0.0182163 - x_uniform_y_gaussian.xml stereovision3.v common 1.88 vpr 67.18 MiB 0.07 10624 -1 -1 4 0.21 -1 -1 36664 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68792 11 30 262 292 2 110 54 7 7 49 clb auto 28.1 MiB 0.13 404 2298 458 1774 66 67.2 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.00 0.000687045 0.000583062 0.0174363 0.0155371 -1 -1 -1 -1 12 308 8 1.07788e+06 700622 -1 -1 0.31 0.110517 0.0976349 2680 3516 -1 297 3 168 247 11340 5786 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0178597 0.0169935 - x_gaussian_y_gaussian.xml stereovision3.v common 1.87 vpr 66.84 MiB 0.06 10496 -1 -1 4 0.16 -1 -1 36536 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68444 11 30 262 292 2 110 54 7 7 49 clb auto 27.9 MiB 0.18 410 2298 443 1773 82 66.8 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000756768 0.000647761 0.0255781 0.0225686 -1 -1 -1 -1 14 303 4 1.07788e+06 700622 -1 -1 0.40 0.162052 0.141633 2680 3516 -1 295 3 165 244 11438 5780 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0211596 0.0200797 - x_delta_y_uniform.xml stereovision3.v common 1.95 vpr 67.15 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36504 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68764 11 30 262 292 2 110 54 7 7 49 clb auto 28.2 MiB 0.14 450 3012 620 2301 91 67.2 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000754694 0.000686961 0.028 0.0247412 -1 -1 -1 -1 48 342 3 1.07788e+06 700622 -1 -1 0.49 0.268135 0.232895 2680 3516 -1 342 3 170 251 11060 5468 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.01 -1 -1 0.00 0.0196307 0.0186303 - x_delta_y_delta.xml stereovision3.v common 2.11 vpr 67.59 MiB 0.07 10496 -1 -1 4 0.22 -1 -1 36664 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69212 11 30 262 292 2 110 54 7 7 49 clb auto 28.0 MiB 0.13 519 3012 615 2292 105 67.6 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000782235 0.000651544 0.0273675 0.0237579 -1 -1 -1 -1 54 442 17 1.07788e+06 700622 -1 -1 0.52 0.268766 0.234157 2680 3516 -1 431 4 215 308 16404 8615 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.04 0.01 -1 -1 0.00 0.0214181 0.0202532 - x_uniform_y_delta.xml stereovision3.v common 2.05 vpr 67.14 MiB 0.07 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 13 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68756 11 30 262 292 2 110 54 7 7 49 clb auto 28.2 MiB 0.15 435 2502 457 1952 93 67.1 MiB 0.05 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000965335 0.000843275 0.027473 0.0239971 -1 -1 -1 -1 34 323 16 1.07788e+06 700622 -1 -1 0.51 0.30529 0.26214 2680 3516 -1 317 16 376 682 28098 12512 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.06 0.01 -1 -1 0.00 0.0352499 0.0319547 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +x_gaussian_y_uniform.xml stereovision3.v common 4.16 odin 168.00 MiB 2.89 172032 -1 -1 4 0.12 -1 -1 33080 -1 -1 13 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67032 11 30 262 292 2 107 54 7 7 49 clb auto 26.1 MiB 0.07 616 394 1788 342 1398 48 65.5 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000399296 0.000348519 0.0100735 0.00904638 -1 -1 -1 -1 10 309 8 1.07788e+06 700622 -1 -1 0.14 0.055401 0.0477102 2680 3516 -1 281 3 216 332 13740 6540 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0115049 0.010865 +x_uniform_y_gaussian.xml stereovision3.v common 3.83 odin 167.25 MiB 2.62 171264 -1 -1 4 0.12 -1 -1 33080 -1 -1 13 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67008 11 30 262 292 2 107 54 7 7 49 clb auto 26.5 MiB 0.07 616 416 1584 291 1249 44 65.4 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000401666 0.000349934 0.00938292 0.00839959 -1 -1 -1 -1 14 315 2 1.07788e+06 700622 -1 -1 0.07 0.0525086 0.0454362 2680 3516 -1 312 2 155 239 9997 5015 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0106958 0.0102281 +x_gaussian_y_gaussian.xml stereovision3.v common 3.81 odin 167.62 MiB 2.58 171648 -1 -1 4 0.13 -1 -1 33100 -1 -1 13 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67872 11 30 262 292 2 107 54 7 7 49 clb auto 26.7 MiB 0.07 616 414 2094 382 1620 92 66.3 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000393876 0.000341734 0.0111355 0.00990517 -1 -1 -1 -1 14 297 3 1.07788e+06 700622 -1 -1 0.08 0.0574378 0.0496165 2680 3516 -1 298 16 183 323 13761 7064 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0189255 0.016994 +x_delta_y_uniform.xml stereovision3.v common 3.95 odin 167.62 MiB 2.67 171648 -1 -1 4 0.13 -1 -1 33108 -1 -1 13 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67296 11 30 262 292 2 107 54 7 7 49 clb auto 26.4 MiB 0.07 616 433 2604 491 2026 87 65.7 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.00039554 0.000344643 0.0131312 0.0117001 -1 -1 -1 -1 38 323 9 1.07788e+06 700622 -1 -1 0.15 0.0905679 0.0769343 2680 3516 -1 318 3 165 251 11417 5738 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0111863 0.0106205 +x_delta_y_delta.xml stereovision3.v common 4.10 odin 167.25 MiB 2.82 171264 -1 -1 4 0.13 -1 -1 32472 -1 -1 13 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 107 54 7 7 49 clb auto 26.8 MiB 0.07 616 488 3114 640 2376 98 65.7 MiB 0.03 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000404029 0.000349186 0.0152957 0.0135457 -1 -1 -1 -1 54 378 8 1.07788e+06 700622 -1 -1 0.16 0.0934017 0.0794444 2680 3516 -1 377 4 186 272 12468 6162 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.02 0.00 -1 -1 0.00 0.0120601 0.011371 +x_uniform_y_delta.xml stereovision3.v common 4.24 odin 168.00 MiB 2.96 172032 -1 -1 4 0.12 -1 -1 33108 -1 -1 13 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67296 11 30 262 292 2 107 54 7 7 49 clb auto 26.8 MiB 0.07 616 423 2196 403 1708 85 65.7 MiB 0.02 0.00 1.85341 1.85341 -135.015 -1.85341 1.81987 0.00 0.000401189 0.000351038 0.0115871 0.0102993 -1 -1 -1 -1 38 306 15 1.07788e+06 700622 -1 -1 0.14 0.0924229 0.0784187 2680 3516 -1 305 15 191 335 14110 6670 1.85341 1.81987 -135.015 -1.85341 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0182708 0.0164585 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt index a4fce4cf22..550e2e3c38 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - timing/k6_N10_mem32K_40nm.xml stereovision3.v common 2.02 vpr 67.00 MiB 0.08 10496 -1 -1 4 0.20 -1 -1 36452 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68608 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.11 419 1815 318 1436 61 67.0 MiB 0.04 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000706488 0.000606458 0.0228093 0.0209659 -1 -1 -1 -1 8 283 18 1.07788e+06 1.02399e+06 -1 -1 0.38 0.186498 0.171178 2100 3116 -1 280 18 572 1139 59841 29637 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.07 0.00 -1 -1 0.00 0.0346595 0.0310733 - nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 2.04 vpr 66.32 MiB 0.07 10496 -1 -1 4 0.26 -1 -1 36580 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67916 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 428 1698 248 1401 49 66.3 MiB 0.04 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.000764131 0.000648712 0.0183265 0.0161998 -1 -1 -1 -1 10 297 21 1.07788e+06 1.02399e+06 -1 -1 0.45 0.176554 0.15406 2100 3116 -1 286 18 539 1058 53794 27022 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.08 0.00 -1 -1 0.00 0.0402826 0.0356284 - nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.99 vpr 66.21 MiB 0.09 10368 -1 -1 4 0.24 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67800 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.09 447 1815 292 1481 42 66.2 MiB 0.07 0.00 1.93141 -140.772 -1.93141 1.88461 0.01 0.00090328 0.000782565 0.0181809 0.0161296 -1 -1 -1 -1 16 296 17 1.07788e+06 1.02399e+06 -1 -1 0.25 0.115099 0.100427 2100 3116 -1 300 17 545 1102 57605 27890 1.93141 1.88461 -140.772 -1.93141 0 0 -1 -1 0.00 0.12 0.01 -1 -1 0.00 0.0397962 0.0356125 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_mem32K_40nm.xml stereovision3.v common 3.87 odin 167.25 MiB 2.58 171264 -1 -1 4 0.12 -1 -1 33092 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67264 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 439 1981 340 1577 64 65.7 MiB 0.02 0.00 2.02388 2.02388 -140.31 -2.02388 1.9292 0.00 0.000398205 0.000349136 0.00900119 0.00804947 -1 -1 -1 -1 8 310 17 1.07788e+06 1.07788e+06 -1 -1 0.16 0.0586928 0.0501312 2100 3116 -1 300 19 436 776 44386 23435 2.02388 1.9292 -140.31 -2.02388 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.019667 0.0173703 +nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 3.87 odin 167.25 MiB 2.63 171264 -1 -1 4 0.13 -1 -1 33112 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66992 11 30 262 292 2 99 61 7 7 49 clb auto 25.4 MiB 0.04 688 420 1741 256 1424 61 65.4 MiB 0.02 0.00 2.02388 2.02388 -140.31 -2.02388 1.9292 0.00 0.000393852 0.000343606 0.00823658 0.00735727 -1 -1 -1 -1 14 287 20 1.07788e+06 1.07788e+06 -1 -1 0.11 0.059966 0.0511419 2100 3116 -1 283 20 516 944 48724 24190 2.02388 1.9292 -140.31 -2.02388 0 0 -1 -1 0.00 0.04 0.00 -1 -1 0.00 0.0200824 0.0177217 +nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 4.00 odin 167.25 MiB 2.70 171264 -1 -1 4 0.13 -1 -1 33044 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67256 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 446 2341 306 1971 64 65.7 MiB 0.02 0.00 2.02388 2.02388 -140.31 -2.02388 1.9292 0.00 0.000409793 0.000358042 0.0103363 0.00921734 -1 -1 -1 -1 16 306 15 1.07788e+06 1.07788e+06 -1 -1 0.10 0.059307 0.0508105 2100 3116 -1 315 15 490 966 53909 27396 2.02388 1.9292 -140.31 -2.02388 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0173015 0.0154302 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt index e6884fa004..2d449c9784 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_graphics_commands/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 6.17 vpr 66.89 MiB 0.08 10368 -1 -1 4 0.22 -1 -1 36612 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68492 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.11 425 2283 406 1804 73 66.9 MiB 2.36 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.00076202 0.000633481 0.0213386 0.0169977 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 1.35 0.0886305 0.079884 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 6.01 odin 167.25 MiB 2.58 171264 -1 -1 4 0.15 -1 -1 32400 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 1.29 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000406146 0.000350888 0.0105671 0.00931962 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.63 0.0340877 0.0298601 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt index b4a9052cd0..e493cfe81d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml stereovision3.v common 2.01 vpr 61.71 MiB 0.06 10112 -1 -1 4 0.22 -1 -1 36708 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63196 11 30 262 292 2 110 54 6 6 36 clb auto 22.9 MiB 0.13 442 4182 3410 664 108 61.7 MiB 0.07 0.00 2.55648 -171.707 -2.55648 2.31607 0.04 0.000697499 0.000590032 0.035108 0.0301305 -1 -1 -1 -1 36 688 16 862304 700622 64877.6 1802.15 0.32 0.199199 0.171554 2900 12076 -1 568 12 312 493 15436 6065 2.62572 2.28031 -177.78 -2.62572 0 0 80896.3 2247.12 0.00 0.04 0.02 -1 -1 0.00 0.0300653 0.0274931 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml stereovision3.v common 2.97 odin 151.50 MiB 1.65 155136 -1 -1 4 0.12 -1 -1 33080 -1 -1 13 11 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61804 11 30 262 292 2 107 54 6 6 36 clb auto 21.0 MiB 0.07 561 417 4182 3406 658 118 60.4 MiB 0.04 0.00 2.44705 2.32039 -170.792 -2.32039 2.20653 0.02 0.000420451 0.000363005 0.0208819 0.0182741 -1 -1 -1 -1 36 788 25 862304 700622 64877.6 1802.15 0.20 0.113117 0.0953418 2900 12076 -1 552 14 362 618 15589 5868 2.33898 2.20362 -179.305 -2.33898 0 0 80896.3 2247.12 0.00 0.02 0.01 -1 -1 0.00 0.0180321 0.0162621 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt index 8d2903c2d4..026c4d12fe 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N4_90nm.xml diffeq.blif common 18.17 vpr 71.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 438 64 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72740 64 39 1935 1974 1 1077 541 23 23 529 clb auto 31.4 MiB 0.53 10472 141533 36950 100839 3744 71.0 MiB 1.46 0.02 7.46482 -1369.01 -7.46482 7.46482 0.64 0.00605549 0.00528423 0.429203 0.364085 -1 -1 -1 -1 24 13068 28 983127 976439 797780. 1508.09 11.91 2.29628 1.96589 39018 137339 -1 11478 18 6600 23331 1479297 381870 7.27304 7.27304 -1454.66 -7.27304 0 0 1.04508e+06 1975.57 0.03 0.83 0.15 -1 -1 0.03 0.252853 0.225541 - k4_N4_90nm.xml ex5p.blif common 20.35 vpr 67.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 366 8 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68624 8 63 1072 1135 0 894 437 22 22 484 clb auto 27.6 MiB 0.32 12004 99857 28319 69545 1993 67.0 MiB 1.07 0.02 6.86459 -313.968 -6.86459 nan 0.52 0.0035933 0.00315668 0.2475 0.211473 -1 -1 -1 -1 32 16530 34 891726 815929 949946. 1962.70 14.36 0.89434 0.759948 43920 162796 -1 14048 22 8455 31174 3329435 847924 6.8764 nan -316.234 -6.8764 0 0 1.22393e+06 2528.78 0.08 1.43 0.30 -1 -1 0.08 0.237816 0.212077 - k4_N4_90nm.xml s298.blif common 19.44 vpr 73.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 580 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 74984 4 6 1942 1948 1 1169 590 27 27 729 clb auto 33.0 MiB 0.49 13813 156389 45768 109723 898 73.2 MiB 1.80 0.03 12.2682 -96.384 -12.2682 12.2682 0.93 0.0106993 0.00945176 0.491739 0.389383 -1 -1 -1 -1 26 17490 32 1.39333e+06 1.29301e+06 1.22387e+06 1678.84 10.93 1.63745 1.34189 57250 204657 -1 16420 17 8603 42614 3232268 684840 12.0598 12.0598 -95.4975 -12.0598 0 0 1.55812e+06 2137.34 0.10 1.48 0.31 -1 -1 0.10 0.297955 0.263351 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm.xml diffeq.blif common 5.07 vpr 69.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 439 64 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71476 64 39 1935 1974 1 1075 542 23 23 529 clb auto 30.0 MiB 0.17 24088 10407 135291 36283 95683 3325 69.8 MiB 0.58 0.01 23.0912 7.70338 -1562.28 -7.70338 7.70338 0.21 0.00213692 0.00182107 0.151208 0.130418 -1 -1 -1 -1 24 13067 26 983127 978669 797780. 1508.09 2.54 0.447134 0.388629 39018 137339 -1 11571 16 6466 23559 1530116 397333 7.70338 7.70338 -1636.85 -7.70338 0 0 1.04508e+06 1975.57 0.02 0.32 0.08 -1 -1 0.02 0.0908461 0.0823099 +k4_N4_90nm.xml ex5p.blif common 7.45 vpr 65.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 362 8 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67216 8 63 1072 1135 0 892 433 22 22 484 clb auto 26.6 MiB 0.14 20089 11891 97016 28068 66779 2169 65.6 MiB 0.41 0.01 11.9965 7.14697 -323.69 -7.14697 nan 0.19 0.00133 0.00117345 0.0909026 0.0812366 -1 -1 -1 -1 32 16897 50 891726 807012 949946. 1962.70 5.06 0.401673 0.3532 43920 162796 -1 13798 21 8357 30046 2938323 715872 6.93884 nan -322.607 -6.93884 0 0 1.22393e+06 2528.78 0.04 0.50 0.10 -1 -1 0.04 0.0814384 0.0735992 +k4_N4_90nm.xml s298.blif common 9.10 vpr 72.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 579 4 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 73908 4 6 1942 1948 1 1135 589 27 27 729 clb auto 32.1 MiB 0.19 26761 13173 158541 45950 111660 931 72.2 MiB 0.67 0.01 27.8284 12.5893 -95.8017 -12.5893 12.5893 0.29 0.00238069 0.00200478 0.170773 0.146328 -1 -1 -1 -1 24 18368 39 1.39333e+06 1.29078e+06 1.12265e+06 1539.99 5.78 0.571016 0.488765 54650 192211 -1 15957 20 8308 43971 3554658 708435 12.1943 12.1943 -92.9601 -12.1943 0 0 1.47093e+06 2017.74 0.02 0.61 0.11 -1 -1 0.02 0.119128 0.107236 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt index 4db936a1dd..d5ba115c24 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.78 vpr 69.28 MiB 0.09 10496 -1 -1 5 0.19 -1 -1 36448 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70944 11 30 313 321 2 114 55 7 7 49 clb auto 29.8 MiB 0.39 459 2031 574 1374 83 69.3 MiB 0.03 0.00 4.6413 0 0 4.31525 0.00 0.000635584 0.000552586 0.0173645 0.0155707 -1 -1 -1 -1 570 5.27778 228 2.11111 239 439 10467 3202 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 4.62935 4.30491 0 0 -165.142 -1.707 0.05 -1 -1 69.3 MiB 0.14 0.147679 0.140851 69.3 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 4.05 odin 157.12 MiB 2.90 160896 -1 -1 5 0.11 -1 -1 33304 -1 -1 14 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69244 11 30 313 321 2 115 55 7 7 49 clb auto 28.0 MiB 0.18 671 430 3071 674 1846 551 67.6 MiB 0.03 0.00 4.73611 4.6413 0 0 4.32062 0.00 0.000434154 0.000399324 0.0150392 0.0138987 -1 -1 -1 -1 568 5.21101 230 2.11009 310 604 14151 4248 1.07788e+06 754516 219490. 4479.39 9 5100 32136 -1 4.69675 4.35776 0 0 -164.736 -1.707 0.02 -1 -1 67.6 MiB 0.09 0.0951391 0.0915263 67.6 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt index 19fe5d4556..bcb0b5d161 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_multiclock/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack - k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 +arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack +k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.59919 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.59919 -1 1.1662 -1 1.8371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.44782 -1 3.4042 -1 -1.40928 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt index 8285cf5d7b..72debce669 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 2.66 vpr 68.27 MiB 0.06 9984 -1 -1 3 0.36 -1 -1 39780 -1 -1 66 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69908 99 130 363 493 1 250 296 12 12 144 clb auto 29.2 MiB 0.21 805 57484 15208 21002 21274 68.3 MiB 0.11 0.00 40 1774 10 5.66058e+06 4.105e+06 360333. 2502.31 0.52 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 4.12 odin 100.88 MiB 2.61 103296 -1 -1 3 0.20 -1 -1 34096 -1 -1 66 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68528 99 130 363 493 1 256 296 12 12 144 clb auto 27.9 MiB 0.09 2010 809 75232 21521 28755 24956 66.9 MiB 0.06 0.00 48 1681 14 5.66058e+06 4.105e+06 424682. 2949.18 0.24 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt index 735a18dab2..cc33176ec5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.45 vpr 66.93 MiB 0.09 10368 -1 -1 4 0.22 -1 -1 36756 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68532 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00571426 0.00556672 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.81 odin 166.88 MiB 2.93 170880 -1 -1 4 0.12 -1 -1 33300 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67260 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00124911 0.00117605 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt index 402ade2262..3ace4d5412 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.29 vpr 66.33 MiB 0.06 10368 -1 -1 4 0.21 -1 -1 36632 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67920 11 30 262 292 2 99 60 7 7 49 clb auto 27.4 MiB 0.08 427 1815 293 1474 48 66.3 MiB 0.04 0.00 2.45489 -180.219 -2.45489 2.30757 0.05 0.000892007 0.00076546 0.0179963 0.0157273 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0202445 0.0178347 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.51 odin 167.25 MiB 2.60 171264 -1 -1 4 0.12 -1 -1 33280 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67264 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 430 2821 451 2299 71 65.7 MiB 0.02 0.00 2.92675 2.74423 -180.089 -2.74423 2.44742 0.02 0.000405489 0.000350282 0.0120913 0.0106559 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0132838 0.0117791 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt index 8bf865796b..088943051d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_pack_disable/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml mult_5x6.blif common 0.57 vpr 60.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62456 11 11 59 70 0 48 26 4 4 16 clb auto 22.0 MiB 0.04 179 862 260 602 0 61.0 MiB 0.01 0.00 2.46139 -19.889 -2.46139 nan 0.01 0.000234107 0.000208327 0.0069198 0.00625105 -1 -1 -1 -1 28 244 41 215576 215576 17602.3 1100.14 0.10 0.0507337 0.0443992 984 2821 -1 165 13 220 476 6314 3099 2.61613 nan -21.1174 -2.61613 0 0 21084.5 1317.78 0.00 0.02 0.00 -1 -1 0.00 0.0119559 0.010883 - k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.07 vpr 23.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 23940 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 22.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml mult_5x6.blif common 0.39 vpr 59.58 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61008 11 11 59 70 0 48 26 4 4 16 clb auto 20.2 MiB 0.02 205 178 672 211 461 0 59.6 MiB 0.01 0.00 2.48509 2.46139 -19.889 -2.46139 nan 0.01 0.000112867 0.00010304 0.00300915 0.0028022 -1 -1 -1 -1 30 215 23 215576 215576 18771.3 1173.21 0.04 0.0198713 0.0171168 1016 3020 -1 186 15 222 505 8959 4790 2.75695 nan -23.0631 -2.75695 0 0 22855.5 1428.47 0.00 0.01 0.00 -1 -1 0.00 0.00619382 0.00560822 +k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.05 vpr 21.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 21860 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 19.8 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt index af7706738c..9a1a17608d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common 0.24 vpr 64.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66340 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 21 30 9 19 2 64.8 MiB 0.01 0.00 0.646042 -3.51892 -0.646042 0.571 0.01 6.4699e-05 4.5848e-05 0.00182479 0.00174439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00182479 0.00174439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common 0.15 vpr 62.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64396 5 3 11 14 2 9 10 4 4 16 clb auto -1 -1 24 21 30 9 19 2 62.9 MiB 0.00 0.00 0.739166 0.646042 -3.51892 -0.646042 0.571 0.00 3.9352e-05 3.197e-05 0.000998595 0.00095751 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000998595 0.00095751 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt index 25609b75a6..e931e49e90 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 40.74 vpr 978.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001944 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.61 385 628 76 517 35 978.5 MiB 0.06 0.00 6.37842 -68.9926 -6.37842 6.37842 2.79 0.000585035 0.000506509 0.0125856 0.0113967 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.17 0.202681 0.177336 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.09 0.08 -1 -1 0.01 0.0322374 0.0298184 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 42.57 vpr 978.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001668 10 10 168 178 1 68 30 11 8 88 io auto 955.1 MiB 0.58 356 628 86 501 41 978.2 MiB 0.08 0.00 6.32784 -69.1369 -6.32784 6.32784 2.79 0.00106817 0.000941606 0.0173949 0.0157097 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 1.41 0.24274 0.212439 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.08 0.08 -1 -1 0.01 0.0393492 0.0368597 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 41.18 vpr 978.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001944 10 10 168 178 1 68 30 11 8 88 io auto 955.2 MiB 0.77 378 628 92 504 32 978.5 MiB 0.06 0.00 6.37842 -68.9795 -6.37842 6.37842 3.93 0.000461318 0.000398366 0.0135017 0.0123478 -1 -1 -1 -1 30 740 27 0 0 144567. 1642.81 1.27 0.212409 0.18717 11730 32605 -1 579 10 219 802 50034 22946 6.80801 6.80801 -73.0986 -6.80801 0 0 194014. 2204.70 0.01 0.06 0.10 -1 -1 0.01 0.0272644 0.0255028 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 43.49 vpr 978.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1002044 10 10 168 178 1 68 30 11 8 88 io auto 955.6 MiB 0.67 353 582 71 475 36 978.6 MiB 0.10 0.00 6.2342 -69.2052 -6.2342 6.2342 4.26 0.00126519 0.00120018 0.0174025 0.0162066 -1 -1 -1 -1 22 762 19 0 0 110609. 1256.92 0.57 0.121021 0.108951 11258 24748 -1 710 14 413 1547 91286 47129 6.80216 6.80216 -76.023 -6.80216 0 0 134428. 1527.59 0.01 0.08 0.05 -1 -1 0.01 0.0301878 0.0279201 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 22.44 vpr 979.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003284 10 10 168 178 1 65 30 11 8 88 io auto 953.3 MiB 0.33 530 354 766 109 603 54 979.8 MiB 0.05 0.00 6.8164 6.25965 -69.3407 -6.25965 6.25965 1.13 0.000308615 0.00027812 0.00821689 0.00763712 -1 -1 -1 -1 20 842 24 0 0 100248. 1139.18 0.29 0.0541337 0.0478234 11180 23751 -1 740 16 428 1793 101987 51614 6.72979 6.72979 -75.9114 -6.72979 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0172294 0.0158899 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 22.72 vpr 980.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003752 10 10 168 178 1 65 30 11 8 88 io auto 953.4 MiB 0.34 530 359 766 97 619 50 980.2 MiB 0.06 0.00 6.8164 6.26487 -69.3105 -6.26487 6.26487 1.15 0.000305306 0.000278089 0.00832065 0.00774302 -1 -1 -1 -1 22 829 20 0 0 110609. 1256.92 0.27 0.0521795 0.0462508 11258 24748 -1 771 17 378 1439 87505 45574 6.83905 6.83905 -76.8941 -6.83905 0 0 134428. 1527.59 0.00 0.05 0.03 -1 -1 0.00 0.0183082 0.0168294 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 23.08 vpr 980.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003580 10 10 168 178 1 65 30 11 8 88 io auto 953.6 MiB 0.34 530 349 674 94 530 50 980.1 MiB 0.05 0.00 6.77016 6.47558 -68.8469 -6.47558 6.47558 1.55 0.000325761 0.00029813 0.00760044 0.00712011 -1 -1 -1 -1 20 861 19 0 0 100248. 1139.18 0.29 0.0508805 0.0450927 11180 23751 -1 680 16 330 1259 70362 36922 6.87801 6.87801 -76.1492 -6.87801 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0174542 0.0160565 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 22.97 vpr 979.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003340 10 10 168 178 1 65 30 11 8 88 io auto 953.3 MiB 0.33 530 348 720 100 579 41 979.8 MiB 0.05 0.00 6.77016 6.34606 -69.0457 -6.34606 6.34606 1.58 0.000307656 0.000281905 0.00789985 0.00736891 -1 -1 -1 -1 20 851 21 0 0 100248. 1139.18 0.28 0.0526525 0.0466531 11180 23751 -1 743 16 380 1503 81107 41070 6.53785 6.53785 -75.082 -6.53785 0 0 125464. 1425.72 0.00 0.05 0.03 -1 -1 0.00 0.0173662 0.0160076 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt index de612c1c66..3f0bb7eec9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 41.99 vpr 978.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001688 10 10 168 178 1 68 30 11 8 88 io auto 955.2 MiB 0.85 385 628 76 517 35 978.2 MiB 0.09 0.00 6.37842 -68.9926 -6.37842 6.37842 2.49 0.000740479 0.000647957 0.0145497 0.0133659 -1 -1 -1 -1 28 740 24 0 0 134428. 1527.59 1.45 0.22055 0.192568 11590 29630 -1 638 15 260 898 57405 28552 6.7547 6.7547 -73.7765 -6.7547 0 0 173354. 1969.93 0.01 0.11 0.10 -1 -1 0.01 0.0358167 0.033477 - stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 41.03 vpr 978.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001836 10 10 168 178 1 68 30 11 8 88 io auto 955.3 MiB 0.66 356 628 86 501 41 978.4 MiB 0.10 0.00 6.32784 -69.1369 -6.32784 6.32784 2.55 0.000491141 0.000429611 0.0148781 0.0136279 -1 -1 -1 -1 26 696 13 0 0 125464. 1425.72 1.47 0.229896 0.203057 11500 28430 -1 625 14 346 1342 78096 38981 6.62332 6.62332 -73.8789 -6.62332 0 0 163463. 1857.53 0.01 0.11 0.09 -1 -1 0.01 0.0316333 0.0293122 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 23.19 vpr 979.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003496 10 10 168 178 1 65 30 11 8 88 io auto 953.3 MiB 0.34 530 354 766 109 603 54 980.0 MiB 0.06 0.00 6.8164 6.25965 -69.3407 -6.25965 6.25965 1.14 0.000312348 0.000282518 0.00838207 0.00779678 -1 -1 -1 -1 20 842 24 0 0 100248. 1139.18 0.30 0.0549041 0.0486343 11180 23751 -1 740 16 428 1793 101987 51614 6.72979 6.72979 -75.9114 -6.72979 0 0 125464. 1425.72 0.00 0.06 0.03 -1 -1 0.00 0.0177507 0.0163734 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 22.59 vpr 980.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003844 10 10 168 178 1 65 30 11 8 88 io auto 953.4 MiB 0.33 530 359 766 97 619 50 980.3 MiB 0.05 0.00 6.8164 6.26487 -69.3105 -6.26487 6.26487 1.14 0.000309575 0.000282731 0.00841827 0.00784949 -1 -1 -1 -1 22 829 20 0 0 110609. 1256.92 0.27 0.0522527 0.0463362 11258 24748 -1 771 17 378 1439 87505 45574 6.83905 6.83905 -76.8941 -6.83905 0 0 134428. 1527.59 0.00 0.05 0.03 -1 -1 0.00 0.0177843 0.0163266 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt index be79764ceb..aed6680394 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_effort_scaling/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml ex5p.blif common_--place_effort_scaling_circuit 4.26 vpr 76.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78288 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.83 6246 12245 2336 8854 1055 76.5 MiB 0.39 0.01 4.93521 -218.151 -4.93521 nan 0.27 0.00393519 0.00333322 0.167205 0.141172 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.170495 0.143929 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 3.34 vpr 76.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78408 8 63 1072 1135 0 619 135 12 12 144 clb auto 36.4 MiB 2.32 6248 12409 2316 9051 1042 76.6 MiB 0.27 0.01 5.00015 -217.921 -5.00015 nan 0.18 0.00183948 0.00156955 0.109821 0.0973753 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.11472 0.101715 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 6.81 vpr 76.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78560 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.7 MiB 2.45 6557 16051 3559 11939 553 76.7 MiB 0.47 0.01 5.39652 -231.823 -5.39652 nan 1.67 0.00368316 0.00300979 0.191413 0.165252 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.196386 0.169658 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 7.69 vpr 76.65 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78492 8 63 1072 1135 0 619 135 27 27 729 -1 auto 36.4 MiB 2.51 6642 53385 10847 39555 2983 76.7 MiB 1.06 0.02 5.30857 -236.309 -5.30857 nan 1.91 0.00201874 0.00161249 0.24975 0.219272 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.258981 0.227848 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml ex5p.blif common_--place_effort_scaling_circuit 1.79 vpr 75.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77728 8 63 1072 1135 0 611 133 11 11 121 clb auto 36.1 MiB 1.19 7518 6082 8947 1533 6815 599 75.9 MiB 0.13 0.00 5.94011 5.07653 -213.869 -5.07653 nan 0.08 0.00138576 0.00122077 0.0562426 0.0514538 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0584675 0.0534522 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 1.80 vpr 75.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 77728 8 63 1072 1135 0 611 133 11 11 121 clb auto 36.1 MiB 1.19 7518 6142 9355 1631 7067 657 75.9 MiB 0.14 0.00 5.94011 4.97625 -208.188 -4.97625 nan 0.08 0.00135823 0.00118423 0.0600839 0.0547953 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.0623786 0.0568505 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 3.08 vpr 74.73 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76524 8 63 1072 1135 0 611 133 27 27 729 -1 auto 35.4 MiB 1.19 17047 6704 22507 6724 13850 1933 74.7 MiB 0.27 0.00 9.03576 5.62812 -248.555 -5.62812 nan 0.63 0.00135473 0.00118694 0.110186 0.0990543 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.11251 0.101133 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 3.32 vpr 75.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 76840 8 63 1072 1135 0 611 133 27 27 729 -1 auto 35.8 MiB 1.19 17047 6681 64488 18508 41026 4954 75.0 MiB 0.52 0.01 9.03576 5.51074 -242.103 -5.51074 nan 0.63 0.00134141 0.00118319 0.102095 0.0921306 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.104355 0.0941516 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt index b0056cc1ab..26a8d5ab6f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_place_quench_slack/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.86 vpr 66.93 MiB 0.06 10496 -1 -1 4 0.21 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68536 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 427 1815 293 1474 48 66.9 MiB 0.03 0.00 2.45489 -180.219 -2.45489 2.30757 0.06 0.00072366 0.000614909 0.0157761 0.0136171 -1 -1 -1 -1 18 637 26 1.07788e+06 1.02399e+06 45686.6 932.380 0.27 0.140412 0.11741 2616 8308 -1 528 22 686 1665 42264 14116 2.57724 2.36372 -184.812 -2.57724 0 0 59124.6 1206.62 0.00 0.06 0.01 -1 -1 0.00 0.0578011 0.0529737 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 4.31 odin 166.50 MiB 2.94 170496 -1 -1 4 0.12 -1 -1 33280 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67264 11 30 262 292 2 99 61 7 7 49 clb auto 26.0 MiB 0.04 688 430 2821 451 2299 71 65.7 MiB 0.02 0.00 2.92675 2.74423 -180.089 -2.74423 2.44742 0.02 0.000412065 0.000357534 0.0119868 0.0105294 -1 -1 -1 -1 18 673 35 1.07788e+06 1.07788e+06 45686.6 932.380 0.18 0.0733358 0.0615029 2616 8308 -1 591 24 845 2121 68310 27246 2.65985 2.3922 -190.754 -2.65985 0 0 59124.6 1206.62 0.00 0.04 0.00 -1 -1 0.00 0.0228008 0.0197013 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt index c15f882826..eabd84cf1b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_post_routing_sync/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_true.blif common 0.38 vpr 62.46 MiB -1 -1 -1 -1 0 0.02 -1 -1 33172 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63964 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.2 MiB 0.00 0 3 0 0 3 62.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.4078e-05 8.305e-06 7.897e-05 5.195e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00158662 0.00151514 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml const_false.blif common 0.40 vpr 62.46 MiB -1 -1 -1 -1 0 0.02 -1 -1 32980 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63964 -1 1 1 2 0 1 2 3 3 9 -1 auto 24.2 MiB 0.00 0 3 0 0 3 62.5 MiB 0.00 0.00 nan 0 0 nan 0.00 1.1945e-05 6.486e-06 7.545e-05 4.8841e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00148797 0.00142035 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_true.blif common 0.44 vpr 62.59 MiB -1 -1 -1 -1 0 0.02 -1 -1 32992 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64096 6 1 1 8 0 1 8 3 3 9 -1 auto 24.3 MiB 0.00 0 21 0 11 10 62.6 MiB 0.00 0.00 nan 0 0 nan 0.00 2.0091e-05 1.2082e-05 0.000201085 0.000162772 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.00181183 0.00172223 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml always_false.blif common 0.43 vpr 62.71 MiB -1 -1 -1 -1 0 0.02 -1 -1 33076 -1 -1 1 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64216 6 1 1 8 0 1 8 3 3 9 -1 auto 24.3 MiB 0.00 0 21 0 11 10 62.7 MiB 0.00 0.00 nan 0 0 nan 0.00 1.9557e-05 1.1746e-05 0.00010411 6.6917e-05 -1 -1 -1 -1 -1 0 1 3900 3900 7855.82 872.868 0.00 0.0019441 0.00185632 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and.blif common 0.39 vpr 62.59 MiB -1 -1 -1 -1 1 0.02 -1 -1 33300 -1 -1 1 2 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64092 2 1 3 4 0 3 4 3 3 9 -1 auto 24.3 MiB 0.00 9 9 5 0 4 62.6 MiB 0.00 0.00 0.443777 -0.443777 -0.443777 nan 0.00 1.6008e-05 1.0878e-05 0.0001005 7.3545e-05 -1 -1 -1 -1 -1 6 9 3900 3900 7855.82 872.868 0.00 0.00172772 0.00159734 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut.blif common 0.62 vpr 62.37 MiB -1 -1 -1 -1 2 0.06 -1 -1 35272 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63864 5 1 7 8 0 7 7 3 3 9 -1 auto 24.0 MiB 0.00 20 18 12 0 6 62.4 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4824e-05 1.9123e-05 0.000151781 0.000121494 -1 -1 -1 -1 -1 8 6 3900 3900 7855.82 872.868 0.00 0.00207121 0.00193926 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml multiconnected_lut2.blif common 0.55 vpr 62.58 MiB -1 -1 -1 -1 2 0.06 -1 -1 35192 -1 -1 1 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 64080 5 1 7 8 0 7 7 3 3 9 -1 auto 24.2 MiB 0.00 20 18 13 0 5 62.6 MiB 0.00 0.00 0.70303 -0.70303 -0.70303 nan 0.00 2.4985e-05 1.9224e-05 0.000155624 0.000125459 -1 -1 -1 -1 -1 11 12 3900 3900 7855.82 872.868 0.00 0.002084 0.00190667 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml and_latch.blif common 0.39 vpr 62.40 MiB -1 -1 -1 -1 1 0.02 -1 -1 33452 -1 -1 1 3 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower 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/home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62804 8 8 51 59 0 51 22 5 5 25 clb auto 22.8 MiB 0.01 241 211 352 90 254 8 61.3 MiB 0.00 0.00 2.56944 2.55689 -12.2592 -2.55689 nan 0.00 8.6948e-05 7.9106e-05 0.00146035 0.00133589 -1 -1 -1 -1 -1 432 21 23400 23400 33739.5 1349.58 0.02 0.00629716 0.00551312 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml mult_5x5.blif common 0.51 vpr 61.69 MiB -1 -1 -1 -1 7 0.06 -1 -1 32828 -1 -1 11 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 63172 10 10 95 105 0 95 31 6 6 36 clb auto 22.5 MiB 0.01 521 440 511 77 404 30 61.7 MiB 0.01 0.00 2.69967 2.57044 -18.1695 -2.57044 nan 0.00 0.000151669 0.000139304 0.00230938 0.00213343 -1 -1 -1 -1 -1 938 24 165600 42900 61410.5 1705.85 0.05 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VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62636 3 2 5 7 0 5 6 3 3 9 -1 auto 22.5 MiB 0.00 15 15 15 11 0 4 61.2 MiB 0.00 0.00 0.443777 0.443777 -0.887553 -0.443777 nan 0.00 1.2814e-05 9.214e-06 8.9746e-05 7.0022e-05 -1 -1 -1 -1 -1 12 16 3900 3900 7855.82 872.868 0.00 0.0012118 0.00107291 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_2bit.blif common 0.40 vpr 61.17 MiB -1 -1 -1 -1 2 0.03 -1 -1 31864 -1 -1 1 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62636 5 3 9 12 0 9 9 3 3 9 -1 auto 22.5 MiB 0.00 26 26 27 24 0 3 61.2 MiB 0.00 0.00 0.70303 0.70303 -1.84984 -0.70303 nan 0.00 1.6757e-05 1.2973e-05 0.000126203 0.000105114 -1 -1 -1 -1 -1 19 17 3900 3900 7855.82 872.868 0.00 0.00143078 0.00126253 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_3bit.blif common 0.41 vpr 60.45 MiB -1 -1 -1 -1 3 0.03 -1 -1 31860 -1 -1 1 7 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61904 7 4 13 17 0 13 12 3 3 9 -1 auto 21.8 MiB 0.00 37 37 38 34 0 4 60.5 MiB 0.00 0.00 0.962283 0.962283 -3.07137 -0.962283 nan 0.00 2.3628e-05 1.9266e-05 0.000202547 0.00017706 -1 -1 -1 -1 -1 39 18 3900 3900 7855.82 872.868 0.00 0.00173423 0.0015346 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_4bit.blif common 0.40 vpr 60.81 MiB -1 -1 -1 -1 4 0.04 -1 -1 31864 -1 -1 1 9 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62268 9 5 17 22 0 17 15 3 3 9 -1 auto 22.5 MiB 0.00 48 48 51 43 0 8 60.8 MiB 0.00 0.00 1.22154 1.22154 -4.55216 -1.22154 nan 0.00 2.6463e-05 2.2226e-05 0.000209499 0.000186343 -1 -1 -1 -1 -1 65 18 3900 3900 7855.82 872.868 0.00 0.0019581 0.00173204 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm_nonLR.xml rca_5bit.blif common 0.40 vpr 61.19 MiB -1 -1 -1 -1 4 0.04 -1 -1 31864 -1 -1 2 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 62660 11 6 24 30 0 24 19 4 4 16 clb auto 22.5 MiB 0.00 96 81 219 61 139 19 61.2 MiB 0.00 0.00 1.37337 1.3375 -6.59285 -1.3375 nan 0.00 3.6059e-05 3.0725e-05 0.000517674 0.000451633 -1 -1 -1 -1 -1 131 14 7800 7800 17482.0 1092.63 0.01 0.00252497 0.00223247 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt index 1f6be016ab..25b7b0daf3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.79 vpr 67.81 MiB 0.06 9856 -1 -1 3 0.37 -1 -1 39772 -1 54808 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69436 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.13 821 70943 24958 34400 11585 67.8 MiB 0.24 0.00 2.51136 -219.195 -2.51136 2.51136 0.28 0.000896235 0.000803075 0.0731146 0.0664864 -1 -1 -1 -1 40 1499 25 5.66058e+06 4.21279e+06 333335. 2314.82 1.63 0.35542 0.319058 12666 64609 -1 1442 10 553 749 42115 14455 2.64494 2.64494 -235.699 -2.64494 0 0 419432. 2912.72 0.02 0.06 0.11 -1 -1 0.02 0.0374155 0.0350957 0.008441 0.2001 0.06777 0.7321 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 16.21 vpr 71.75 MiB 0.06 9856 -1 -1 15 0.50 -1 -1 38288 -1 56228 38 162 0 5 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73476 162 96 999 932 1 689 301 16 16 256 mult_36 auto 32.3 MiB 0.49 5426 96061 33445 54809 7807 71.8 MiB 1.03 0.02 21.3991 -1811.48 -21.3991 21.3991 0.51 0.00504368 0.00468153 0.493175 0.461597 -1 -1 -1 -1 56 11482 33 1.21132e+07 4.02797e+06 870502. 3400.40 8.42 2.47741 2.31569 26504 172068 -1 9223 22 3083 6041 811453 269172 22.8885 22.8885 -1951.66 -22.8885 0 0 1.11200e+06 4343.75 0.07 0.47 0.29 -1 -1 0.07 0.221232 0.208061 0.007874 0.3571 0.01689 0.626 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.21 odin 100.50 MiB 2.20 102912 -1 -1 3 0.22 -1 -1 34096 -1 52224 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67864 99 130 363 493 1 251 298 12 12 144 clb auto 27.5 MiB 0.07 2086 873 75918 23929 39390 12599 66.3 MiB 0.13 0.00 2.81842 2.17528 -220.25 -2.17528 2.17528 0.09 0.000543287 0.00050845 0.0450868 0.0422277 -1 -1 -1 -1 32 1783 21 5.66058e+06 4.21279e+06 281316. 1953.58 0.21 0.117852 0.108695 11950 52952 -1 1569 8 475 592 37949 12971 2.62567 2.62567 -236.989 -2.62567 0 0 345702. 2400.71 0.01 0.02 0.03 -1 -1 0.01 0.0150796 0.0141971 0.008359 0.1947 0.06177 0.7435 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 7.76 odin 87.38 MiB 2.16 89472 -1 -1 15 0.29 -1 -1 34660 -1 54320 39 162 0 5 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 72880 162 96 999 932 1 692 302 16 16 256 mult_36 auto 31.7 MiB 0.23 9298 5609 93406 28941 57235 7230 71.2 MiB 0.38 0.01 25.0935 21.2697 -1792.21 -21.2697 21.2697 0.18 0.00171388 0.00161089 0.166383 0.156115 -1 -1 -1 -1 42 13435 49 1.21132e+07 4.08187e+06 666210. 2602.38 1.82 0.498385 0.465243 24208 131534 -1 10212 18 3382 6827 1034510 307036 22.5724 22.5724 -1934.15 -22.5724 0 0 835850. 3265.04 0.02 0.21 0.07 -1 -1 0.02 0.0832237 0.0788059 0.00765 0.3347 0.01582 0.6495 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt index d6f9144a21..b3d6ca910d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml stereovision3.v common 1.32 vpr 66.34 MiB 0.08 10496 -1 -1 4 0.22 -1 -1 36740 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67936 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.07 425 2283 406 1804 73 66.3 MiB 0.04 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000792071 0.00065667 0.0233552 0.0207856 -1 -1 -1 -1 414 4.35789 166 1.74737 630 1427 58282 13907 1.07788e+06 1.02399e+06 207176. 4228.08 20 4440 29880 -1 2.3823 2.2863 -180.577 -2.3823 0 0 0.05 -1 -1 66.3 MiB 0.07 0.0694098 0.0624777 66.3 MiB -1 0.01 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.84 vpr 69.28 MiB 0.07 10496 -1 -1 5 0.19 -1 -1 36360 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70940 11 30 313 321 2 115 55 7 7 49 clb auto 29.8 MiB 0.48 448 1927 352 1502 73 69.3 MiB 0.05 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.00080657 0.000690329 0.0283624 0.0258806 -1 -1 -1 -1 595 5.45872 228 2.09174 234 449 14202 4622 1.07788e+06 754516 219490. 4479.39 8 5100 32136 -1 2.70461 2.28805 -176.84 -2.70461 0 0 0.06 -1 -1 69.3 MiB 0.04 0.0633117 0.0585851 69.3 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.67 odin 167.25 MiB 2.72 171264 -1 -1 4 0.12 -1 -1 33080 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67016 11 30 262 292 2 99 61 7 7 49 clb auto 25.4 MiB 0.04 688 437 2341 384 1888 69 65.4 MiB 0.02 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000407854 0.000353027 0.0105395 0.0093127 -1 -1 -1 -1 434 4.56842 177 1.86316 730 1655 64750 15779 1.07788e+06 1.07788e+06 207176. 4228.08 23 4440 29880 -1 2.44651 2.32748 -175.142 -2.44651 0 0 0.02 -1 -1 65.4 MiB 0.03 0.0335535 0.0294506 65.4 MiB -1 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.67 odin 156.75 MiB 2.59 160512 -1 -1 5 0.11 -1 -1 33196 -1 -1 14 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68800 11 30 313 321 2 114 55 7 7 49 clb auto 27.9 MiB 0.18 671 455 1719 301 1356 62 67.2 MiB 0.02 0.00 2.73611 2.6413 -165.526 -2.6413 2.31106 0.00 0.000430761 0.000377162 0.0112262 0.010132 -1 -1 -1 -1 571 5.28704 218 2.01852 192 380 9910 2908 1.07788e+06 754516 219490. 4479.39 12 5100 32136 -1 2.66069 2.29553 -166.559 -2.66069 0 0 0.02 -1 -1 67.2 MiB 0.02 0.0312578 0.0284291 67.2 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt index 9c4fd28b84..b7928059c1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 29.83 vpr 86.25 MiB 0.45 29568 -1 -1 4 2.98 -1 -1 43168 -1 -1 169 193 5 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 88324 193 205 2863 2789 1 1374 572 20 20 400 memory auto 45.0 MiB 2.27 10985 240245 81936 130873 27436 86.3 MiB 2.86 0.03 4.42447 -2617.73 -4.42447 4.42447 0.89 0.00871072 0.007701 1.03653 0.893245 -1 -1 -1 -1 78 21148 33 2.07112e+07 1.18481e+07 2.06176e+06 5154.39 13.92 4.09327 3.61448 52874 439520 -1 19015 17 5137 14374 1050969 231484 5.06231 5.06231 -2806.44 -5.06231 -11.1461 -0.341744 2.60035e+06 6500.87 0.19 0.98 0.77 -1 -1 0.19 0.584807 0.525478 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 22.52 odin 1.01 GiB 11.20 1063224 -1 -1 4 1.55 -1 -1 40168 -1 -1 165 193 5 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 87908 193 205 2863 2789 1 1378 568 20 20 400 memory auto 45.6 MiB 1.04 22943 10817 247423 86121 133897 27405 85.8 MiB 1.23 0.01 6.47551 5.02579 -2678.97 -5.02579 5.02579 0.34 0.00370577 0.00334664 0.475767 0.429036 -1 -1 -1 -1 76 21112 34 2.07112e+07 1.16325e+07 2.02110e+06 5052.76 4.11 1.47433 1.33545 52074 423490 -1 19105 17 5044 13854 1088699 242536 5.48145 5.48145 -2895.27 -5.48145 -14.3689 -0.360359 2.51807e+06 6295.18 0.07 0.34 0.25 -1 -1 0.07 0.216764 0.203405 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt index 812f4d3bdb..7d177a0756 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_init_timing/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.96 vpr 71.51 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73224 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.52 4992 14048 2664 10357 1027 71.5 MiB 0.35 0.02 4.19211 -186.67 -4.19211 nan 0.00 0.00713555 0.00269028 0.139755 0.114328 -1 -1 -1 -1 6642 14.5978 1787 3.92747 3214 12750 489499 77791 9.20055e+06 4.79657e+06 867065. 4423.80 16 18088 133656 -1 4.47188 nan -188.808 -4.47188 0 0 0.22 -1 -1 71.5 MiB 0.32 0.294582 0.254721 71.5 MiB -1 0.05 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 2.24 vpr 71.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73336 8 63 748 811 0 455 160 14 14 196 clb auto 32.0 MiB 0.64 4992 14048 2664 10357 1027 71.6 MiB 0.33 0.01 4.19211 -186.67 -4.19211 nan 0.00 0.00345084 0.002875 0.154792 0.13937 -1 -1 -1 -1 6701 14.7275 1794 3.94286 3137 12291 459530 73860 9.20055e+06 4.79657e+06 867065. 4423.80 18 18088 133656 -1 4.41143 nan -186.654 -4.41143 0 0 0.26 -1 -1 71.6 MiB 0.37 0.334856 0.303047 71.6 MiB -1 0.08 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 0.98 vpr 69.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71276 8 63 748 811 0 451 161 14 14 196 clb auto 30.6 MiB 0.28 7035 5048 13708 2494 10216 998 69.6 MiB 0.13 0.00 6.16893 4.25044 -184.802 -4.25044 nan 0.00 0.0012287 0.00107475 0.0530777 0.0477179 -1 -1 -1 -1 6826 15.1353 1836 4.07095 3768 15421 585680 92261 9.20055e+06 4.85046e+06 867065. 4423.80 21 18088 133656 -1 4.17836 nan -185.935 -4.17836 0 0 0.08 -1 -1 69.6 MiB 0.16 0.128489 0.116855 69.6 MiB -1 0.03 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 0.92 vpr 69.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71596 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.23 7035 5048 13708 2494 10216 998 69.9 MiB 0.12 0.00 6.16893 4.25044 -184.802 -4.25044 nan 0.00 0.00122344 0.00107454 0.0500272 0.0447463 -1 -1 -1 -1 6906 15.3126 1853 4.10865 3897 16323 609528 97595 9.20055e+06 4.85046e+06 867065. 4423.80 21 18088 133656 -1 4.17947 nan -185.454 -4.17947 0 0 0.08 -1 -1 69.9 MiB 0.16 0.127112 0.115123 69.9 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt index ca94c47817..fe3351ad28 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_lookahead/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.33 vpr 71.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73184 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.53 4993 17086 3593 12286 1207 71.5 MiB 0.39 0.01 3.65588 -160.421 -3.65588 nan 0.05 0.00324947 0.00265148 0.171741 0.145172 -1 -1 -1 -1 7077 15.5538 1900 4.17582 3821 15130 1125339 197021 9.20055e+06 4.79657e+06 701736. 3580.29 19 16332 105598 -1 4.24547 nan -186.357 -4.24547 0 0 0.19 -1 -1 71.5 MiB 0.65 0.403427 0.354208 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.06 vpr 71.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72900 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.61 4933 15350 2970 11325 1055 71.2 MiB 0.33 0.01 4.27873 -192.837 -4.27873 nan 0.00 0.00354772 0.00306723 0.134491 0.114487 -1 -1 -1 -1 7099 15.6022 1898 4.17143 3600 14045 536072 90036 9.20055e+06 4.79657e+06 701736. 3580.29 22 16332 105598 -1 4.46795 nan -200.148 -4.46795 0 0 0.16 -1 -1 71.2 MiB 0.37 0.342443 0.304101 71.2 MiB -1 0.04 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 4.12 vpr 71.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73084 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.46 5048 17520 3917 12196 1407 71.4 MiB 0.41 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.0055915 0.00450451 0.174816 0.150375 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.22 -1 -1 71.4 MiB 0.70 0.438594 0.389856 -1 -1 -1 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 3.79 vpr 71.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73092 8 63 748 811 0 455 160 14 14 196 clb auto 31.8 MiB 0.50 5048 17520 3917 12196 1407 71.4 MiB 0.34 0.01 3.77945 -168.167 -3.77945 nan 0.08 0.00371073 0.00310746 0.151921 0.128885 -1 -1 -1 -1 7182 15.7846 1920 4.21978 4190 17148 1255046 221662 9.20055e+06 4.79657e+06 701736. 3580.29 29 16332 105598 -1 4.52207 nan -194.42 -4.52207 0 0 0.16 -1 -1 71.4 MiB 0.65 0.390878 0.342895 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 0.99 vpr 69.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71596 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.23 7019 5149 19389 4557 13188 1644 69.9 MiB 0.16 0.00 5.27085 3.74489 -168.03 -3.74489 nan 0.02 0.00124465 0.00109323 0.0663881 0.0595104 -1 -1 -1 -1 7151 15.8559 1918 4.25277 4270 17535 1282134 224677 9.20055e+06 4.85046e+06 701736. 3580.29 23 16332 105598 -1 4.37015 nan -196.64 -4.37015 0 0 0.06 -1 -1 69.9 MiB 0.22 0.146013 0.13227 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 0.90 vpr 69.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71592 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.23 7019 5029 15019 2779 11014 1226 69.9 MiB 0.13 0.00 5.64572 4.2713 -188.25 -4.2713 nan 0.00 0.0011987 0.00103967 0.0537732 0.0481837 -1 -1 -1 -1 7035 15.5987 1894 4.19956 3783 16134 598321 102284 9.20055e+06 4.85046e+06 701736. 3580.29 20 16332 105598 -1 4.48059 nan -193.333 -4.48059 0 0 0.06 -1 -1 69.9 MiB 0.16 0.128747 0.116894 69.9 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map 1.78 vpr 69.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71272 8 63 748 811 0 451 161 14 14 196 clb auto 30.6 MiB 0.26 7019 5066 19826 4740 13454 1632 69.6 MiB 0.17 0.00 5.43885 3.72182 -172.204 -3.72182 nan 0.03 0.00120644 0.00106134 0.0682631 0.0611189 -1 -1 -1 -1 7315 16.2195 1982 4.39468 4173 17201 1263136 226328 9.20055e+06 4.85046e+06 701736. 3580.29 22 16332 105598 -1 4.28324 nan -195.438 -4.28324 0 0 0.06 -1 -1 69.6 MiB 0.24 0.152364 0.137681 -1 -1 -1 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_extended_map_--reorder_rr_graph_nodes_algorithm_random_shuffle 1.74 vpr 69.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71620 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.24 7019 5066 19826 4740 13454 1632 69.9 MiB 0.16 0.00 5.43885 3.72182 -172.204 -3.72182 nan 0.03 0.00122663 0.00107676 0.0669665 0.0598364 -1 -1 -1 -1 7315 16.2195 1982 4.39468 4173 17201 1263136 226328 9.20055e+06 4.85046e+06 701736. 3580.29 22 16332 105598 -1 4.28324 nan -195.438 -4.28324 0 0 0.06 -1 -1 69.9 MiB 0.24 0.149093 0.134593 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt index 73afad51c4..6c635997d8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_router_update_lb_delays/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 2.09 vpr 71.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73036 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.54 5066 14916 2828 10927 1161 71.3 MiB 0.32 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00299665 0.00251735 0.139481 0.119628 -1 -1 -1 -1 6988 15.3582 1874 4.11868 3892 16491 596262 97679 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.23403 nan -187.789 -4.23403 0 0 0.17 -1 -1 71.3 MiB 0.42 0.337391 0.298836 71.3 MiB -1 0.06 - k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 2.37 vpr 71.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 8 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 73112 8 63 748 811 0 455 160 14 14 196 clb auto 31.9 MiB 0.54 5066 14916 2828 10927 1161 71.4 MiB 0.36 0.01 4.20607 -183.516 -4.20607 nan 0.00 0.00287338 0.00244407 0.145055 0.130505 -1 -1 -1 -1 6949 15.2725 1858 4.08352 3794 15906 573229 94207 9.20055e+06 4.79657e+06 787177. 4016.21 23 17112 118924 -1 4.30087 nan -188.544 -4.30087 0 0 0.23 -1 -1 71.4 MiB 0.57 0.403361 0.368877 71.4 MiB -1 0.07 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 0.94 vpr 69.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71564 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.24 7035 5098 13271 2309 10001 961 69.9 MiB 0.12 0.00 6.18121 4.10809 -187.168 -4.10809 nan 0.00 0.00128225 0.00109058 0.0477565 0.0428347 -1 -1 -1 -1 7155 15.8647 1916 4.24834 4312 18456 674497 110334 9.20055e+06 4.85046e+06 787177. 4016.21 21 17112 118924 -1 4.03206 nan -187.889 -4.03206 0 0 0.07 -1 -1 69.9 MiB 0.18 0.126785 0.115131 69.9 MiB -1 0.02 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 0.95 vpr 69.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 8 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71584 8 63 748 811 0 451 161 14 14 196 clb auto 30.9 MiB 0.25 7035 5098 13271 2309 10001 961 69.9 MiB 0.12 0.00 6.18121 4.10809 -187.168 -4.10809 nan 0.00 0.00120781 0.00105229 0.0479501 0.0431803 -1 -1 -1 -1 7141 15.8337 1913 4.24168 4366 18775 685171 111801 9.20055e+06 4.85046e+06 787177. 4016.21 21 17112 118924 -1 4.03206 nan -187.889 -4.03206 0 0 0.07 -1 -1 69.9 MiB 0.18 0.1252 0.11384 69.9 MiB -1 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt index d51a653450..8051226a91 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - slicem.xml carry_chain.blif common 1.14 vpr 59.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 61108 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 20.9 MiB 0.25 70 15 4 10 1 59.7 MiB 0.00 0.00 0.532448 -5.19346 -0.532448 0.532448 0.00 0.000126011 0.000111009 0.000872338 0.000798258 -1 -1 -1 -1 25 262 18 133321 74067 -1 -1 0.48 0.0703731 0.0607281 1252 5405 -1 274 13 122 122 23159 13821 1.78919 1.78919 -18.223 -1.78919 0 0 -1 -1 0.00 0.02 0.01 -1 -1 0.00 0.00593831 0.00529293 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +slicem.xml carry_chain.blif common 0.53 vpr 58.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 59564 1 -1 48 34 1 35 6 5 5 25 BLK_IG-SLICEM auto 19.0 MiB 0.14 70 70 15 4 10 1 58.2 MiB 0.00 0.00 0.552322 0.523836 -5.19346 -0.523836 0.523836 0.00 7.6032e-05 6.8877e-05 0.00055081 0.000512464 -1 -1 -1 -1 27 337 26 133321 74067 -1 -1 0.09 0.0136703 0.0113579 1284 5874 -1 249 10 84 84 16544 9291 1.47622 1.47622 -16.7882 -1.47622 0 0 -1 -1 0.00 0.01 0.00 -1 -1 0.00 0.00278874 0.00253319 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt index 2974b610be..b4ab494efb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - arch.xml ndff.blif common 0.30 vpr 59.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60508 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 20.6 MiB 0.00 31 59 13 43 3 59.1 MiB 0.00 0.00 0.247067 -2.25231 -0.247067 0.247067 0.00 3.5462e-05 2.8363e-05 0.000299521 0.0002448 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00397217 0.00338578 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00197845 0.00188555 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml ndff.blif common 0.28 vpr 57.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58920 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 18.7 MiB 0.00 36 31 59 13 43 3 57.5 MiB 0.00 0.00 0.247067 0.247067 -2.25231 -0.247067 0.247067 0.00 1.8925e-05 1.4636e-05 0.000174021 0.000141152 -1 -1 -1 -1 3 28 27 59253.6 44440.2 -1 -1 0.01 0.00226351 0.00192699 160 440 -1 25 3 17 25 782 371 0.259819 0.259819 -2.4911 -0.259819 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.00105692 0.000999002 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt index 936401071c..9fe75f14f5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.54 vpr 68.95 MiB 0.06 10496 -1 -1 5 0.18 -1 -1 36448 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70604 11 30 313 321 2 114 55 7 7 49 clb auto 29.5 MiB 0.39 459 2031 574 1374 83 68.9 MiB 0.04 0.00 4.6413 0 0 4.31525 0.00 0.000717512 0.000626394 0.019463 0.0174272 -1 -1 -1 -1 569 5.26852 227 2.10185 207 393 9602 2945 1.07788e+06 754516 219490. 4479.39 7 5100 32136 -1 4.62935 4.30491 0 0 -165.142 -1.707 0.05 -1 -1 68.9 MiB 0.06 0.0634405 0.0562085 68.9 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.69 odin 157.12 MiB 2.59 160896 -1 -1 5 0.11 -1 -1 33072 -1 -1 14 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68988 11 30 313 321 2 115 55 7 7 49 clb auto 28.1 MiB 0.18 671 430 3071 674 1846 551 67.4 MiB 0.03 0.00 4.73611 4.6413 0 0 4.32062 0.00 0.000386901 0.000352993 0.0151663 0.0140063 -1 -1 -1 -1 573 5.25688 232 2.12844 279 564 13433 4035 1.07788e+06 754516 219490. 4479.39 9 5100 32136 -1 4.69675 4.35776 0 0 -164.736 -1.707 0.02 -1 -1 67.4 MiB 0.02 0.0314829 0.0292009 67.4 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt index f1ae261048..0a40c0c344 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.44 vpr 65.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66884 5 3 11 14 2 9 10 4 4 16 clb auto 27.1 MiB 0.01 21 30 5 21 4 65.3 MiB 0.00 0.00 0.814658 -2.77132 -0.814658 0.571 0.01 3.9163e-05 3.0734e-05 0.00023521 0.000191167 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00213897 0.00197887 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00188153 0.00176769 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.42 vpr 65.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66820 5 3 11 14 2 9 10 4 4 16 clb auto 26.9 MiB 0.01 22 30 6 14 10 65.3 MiB 0.00 0.00 0.571 0 0 0.571 0.01 6.1332e-05 3.1443e-05 0.00028123 0.000216755 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.00219985 0.00199813 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0028018 0.00269609 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.40 vpr 65.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66764 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.01 21 30 5 22 3 65.2 MiB 0.00 0.00 0.646297 -2.19033 -0.646297 0.571 0.01 3.8778e-05 3.099e-05 0.000214053 0.000176854 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.01 0.00219902 0.00204346 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00216696 0.00200612 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.40 vpr 65.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66872 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 21 30 7 16 7 65.3 MiB 0.00 0.00 1.6463 -5.31965 -1.6463 0.571 0.01 4.3301e-05 3.3225e-05 0.000258104 0.000204952 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.01 0.00214578 0.0019473 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00224405 0.00207678 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.38 vpr 65.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66984 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.01 22 30 8 15 7 65.4 MiB 0.00 0.00 1.44967 -2.9103 -1.44967 0.571 0.01 5.0024e-05 3.2956e-05 0.000205951 0.000157313 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00254156 0.00219599 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0022282 0.00180897 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.40 vpr 65.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66984 5 3 11 14 2 9 10 4 4 16 clb auto 27.0 MiB 0.00 21 30 5 23 2 65.4 MiB 0.00 0.00 0.146298 0 0 0.571 0.01 5.2455e-05 4.3444e-05 0.00030806 0.000256078 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.01 0.00225516 0.00206503 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00187829 0.00175106 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.32 vpr 63.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65400 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 21 30 5 21 4 63.9 MiB 0.00 0.00 0.814658 0.814658 -2.77132 -0.814658 0.571 0.00 2.0271e-05 1.5643e-05 0.000137507 0.000110743 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.00 0.00121331 0.00111096 564 862 -1 18 4 13 13 306 148 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00107463 0.00100361 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.32 vpr 63.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65400 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 22 30 6 14 10 63.9 MiB 0.00 0.00 0.571 0.571 0 0 0.571 0.00 1.8331e-05 1.4261e-05 0.000126631 0.000104171 -1 -1 -1 -1 8 30 5 107788 107788 4794.78 299.674 0.01 0.0012183 0.00111406 564 862 -1 22 5 17 17 362 153 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0010897 0.0010211 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.32 vpr 63.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 5 3 11 14 2 9 10 4 4 16 clb auto 25.2 MiB 0.00 22 21 30 5 22 3 63.9 MiB 0.00 0.00 0.646297 0.646297 -2.19033 -0.646297 0.571 0.00 2.1315e-05 1.627e-05 0.00014761 0.000119233 -1 -1 -1 -1 8 20 3 107788 107788 4794.78 299.674 0.00 0.00121983 0.00109956 564 862 -1 19 5 16 16 356 157 0.57241 0.571 -2.00713 -0.57241 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00113618 0.0010542 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.32 vpr 63.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65204 5 3 11 14 2 9 10 4 4 16 clb auto 25.0 MiB 0.00 22 21 30 7 16 7 63.7 MiB 0.00 0.00 1.64604 1.6463 -5.31965 -1.6463 0.571 0.00 2.2253e-05 1.6668e-05 0.000148974 0.000117954 -1 -1 -1 -1 8 19 2 107788 107788 4794.78 299.674 0.00 0.0011956 0.00107329 564 862 -1 18 4 13 13 292 139 1.57153 0.571 -4.99677 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0011244 0.001039 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.32 vpr 63.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65164 5 3 11 14 2 9 10 4 4 16 clb auto 25.0 MiB 0.00 22 22 30 8 15 7 63.6 MiB 0.00 0.00 1.44967 1.44967 -2.9103 -1.44967 0.571 0.00 2.6442e-05 1.7426e-05 0.000158037 0.000124446 -1 -1 -1 -1 8 20 11 107788 107788 4794.78 299.674 0.01 0.00146404 0.00127645 564 862 -1 25 5 17 17 497 261 1.46961 0.571 -2.77989 -1.46961 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00117295 0.00107893 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.32 vpr 63.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65404 5 3 11 14 2 9 10 4 4 16 clb auto 25.6 MiB 0.00 22 21 30 5 23 2 63.9 MiB 0.00 0.00 0.146298 0.146298 0 0 0.571 0.00 2.1536e-05 1.7057e-05 0.000154377 0.000122283 -1 -1 -1 -1 8 20 2 107788 107788 4794.78 299.674 0.00 0.00124069 0.00113576 564 862 -1 19 5 16 16 368 166 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00116895 0.00106687 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt index 5a4eb2784d..0c39541efc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.55 vpr 66.09 MiB 0.01 7168 -1 -1 1 0.03 -1 -1 33640 -1 -1 3 9 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67672 9 8 75 70 1 36 20 5 5 25 clb auto 27.1 MiB 0.69 94 695 228 460 7 66.1 MiB 0.01 0.00 2.48207 -26.1618 -2.48207 2.48207 0.03 0.000181733 0.000161557 0.00585234 0.0052913 -1 -1 -1 -1 52 134 15 151211 75605.7 63348.9 2533.96 0.11 0.0432562 0.0374575 2316 10503 -1 114 8 106 124 3566 1793 2.40307 2.40307 -27.5996 -2.40307 0 0 82390.3 3295.61 0.00 0.01 0.02 -1 -1 0.00 0.0069119 0.0064541 13 18 19 7 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.05 vpr 66.50 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33588 -1 -1 2 11 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68092 11 10 108 97 1 47 23 4 4 16 clb auto 27.2 MiB 3.14 125 439 123 270 46 66.5 MiB 0.01 0.00 3.45122 -41.5692 -3.45122 3.45122 0.01 0.000220655 0.000197533 0.0046684 0.00428671 -1 -1 -1 -1 30 238 26 50403.8 50403.8 19887.8 1242.99 0.18 0.0734016 0.0633094 992 2748 -1 177 19 176 222 5882 3651 3.90204 3.90204 -49.9067 -3.90204 0 0 24232.7 1514.54 0.00 0.02 0.00 -1 -1 0.00 0.013296 0.0120352 15 27 29 8 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 5.44 vpr 66.68 MiB 0.01 7040 -1 -1 1 0.03 -1 -1 33700 -1 -1 7 13 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68284 13 12 149 129 1 69 32 6 6 36 clb auto 27.4 MiB 4.03 199 682 229 444 9 66.7 MiB 0.02 0.00 3.51316 -53.1567 -3.51316 3.51316 0.06 0.000399911 0.000364812 0.00775114 0.00715794 -1 -1 -1 -1 40 438 24 403230 176413 88484.8 2457.91 0.50 0.147128 0.127344 3734 16003 -1 329 29 379 534 18280 7787 3.72931 3.72931 -57.4119 -3.72931 0 0 110337. 3064.92 0.00 0.02 0.01 -1 -1 0.00 0.0175574 0.0158074 25 38 42 9 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 3.95 vpr 66.76 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33776 -1 -1 6 15 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68364 15 14 196 165 1 93 35 5 5 25 clb auto 27.2 MiB 2.85 306 947 216 708 23 66.8 MiB 0.02 0.00 3.70693 -62.6491 -3.70693 3.70693 0.02 0.000376121 0.000333163 0.00931262 0.00852228 -1 -1 -1 -1 44 480 22 151211 151211 54748.7 2189.95 0.20 0.0954411 0.083284 2196 9177 -1 392 18 349 466 14859 7098 4.20858 4.20858 -72.9456 -4.20858 0 0 71025.7 2841.03 0.00 0.03 0.01 -1 -1 0.00 0.0211201 0.0192846 36 51 57 11 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 8.23 vpr 67.12 MiB 0.01 7040 -1 -1 1 0.06 -1 -1 33688 -1 -1 5 17 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68736 17 16 251 206 1 119 38 5 5 25 clb auto 27.6 MiB 7.05 397 2054 481 1553 20 67.1 MiB 0.04 0.00 3.86806 -74.2346 -3.86806 3.86806 0.03 0.00048716 0.000431817 0.0193024 0.0173986 -1 -1 -1 -1 50 602 24 151211 126010 61632.8 2465.31 0.24 0.130358 0.114428 2268 9834 -1 534 19 619 1012 32161 14755 4.95834 4.95834 -93.7979 -4.95834 0 0 77226.2 3089.05 0.00 0.04 0.01 -1 -1 0.00 0.0271021 0.0248239 44 66 75 13 0 0 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.16 vpr 67.18 MiB 0.02 7040 -1 -1 1 0.04 -1 -1 33916 -1 -1 8 19 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68792 19 18 308 249 1 137 45 6 6 36 clb auto 27.7 MiB 5.92 455 2365 460 1885 20 67.2 MiB 0.03 0.00 4.8546 -99.6039 -4.8546 4.8546 0.03 0.000494067 0.000457319 0.0145592 0.0132203 -1 -1 -1 -1 62 737 27 403230 201615 131137. 3642.71 0.40 0.139917 0.121866 4226 23319 -1 634 19 613 910 31131 12187 5.08188 5.08188 -101.573 -5.08188 0 0 160622. 4461.73 0.00 0.04 0.02 -1 -1 0.00 0.0328006 0.0301511 55 83 93 14 0 0 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 2.20 vpr 64.71 MiB 1.08 63744 -1 -1 1 0.02 -1 -1 30512 -1 -1 3 9 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66260 9 8 75 70 1 34 20 5 5 25 clb auto 25.9 MiB 0.37 123 90 614 218 387 9 64.7 MiB 0.01 0.00 2.48207 2.48207 -27.847 -2.48207 2.48207 0.01 8.9175e-05 8.0798e-05 0.00283336 0.00262372 -1 -1 -1 -1 44 151 38 151211 75605.7 54748.7 2189.95 0.07 0.024736 0.0208178 2196 9177 -1 119 9 90 109 2746 1383 2.64007 2.64007 -30.0799 -2.64007 0 0 71025.7 2841.03 0.00 0.01 0.01 -1 -1 0.00 0.00414305 0.00382499 13 18 19 7 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 3.53 vpr 64.86 MiB 1.18 64512 -1 -1 1 0.02 -1 -1 30520 -1 -1 2 11 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66420 11 10 108 97 1 49 23 4 4 16 clb auto 25.4 MiB 1.64 144 130 311 98 183 30 64.9 MiB 0.01 0.00 3.45122 3.45122 -42.5068 -3.45122 3.45122 0.01 0.000119844 0.000109458 0.00231654 0.00219242 -1 -1 -1 -1 38 205 31 50403.8 50403.8 23356.0 1459.75 0.07 0.03038 0.0258258 1064 3436 -1 155 11 118 137 3972 2416 3.45122 3.45122 -47.4838 -3.45122 0 0 29887.0 1867.94 0.00 0.01 0.00 -1 -1 0.00 0.0058126 0.00537566 15 27 29 8 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 4.94 vpr 65.21 MiB 1.21 64896 -1 -1 1 0.02 -1 -1 30160 -1 -1 7 13 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66772 13 12 149 129 1 68 32 6 6 36 clb auto 25.9 MiB 2.86 259 213 732 224 501 7 65.2 MiB 0.01 0.00 3.50789 3.50789 -53.116 -3.50789 3.50789 0.02 0.00015593 0.00014271 0.00384461 0.00361887 -1 -1 -1 -1 56 371 18 403230 176413 117789. 3271.93 0.11 0.0376034 0.0323292 4086 21443 -1 348 11 215 316 13445 5456 3.49231 3.49231 -56.5872 -3.49231 0 0 149557. 4154.36 0.00 0.01 0.01 -1 -1 0.00 0.00749166 0.00694517 25 38 42 9 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 3.40 vpr 65.59 MiB 1.10 65280 -1 -1 1 0.02 -1 -1 30016 -1 -1 7 15 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67168 15 14 196 165 1 92 36 6 6 36 clb auto 25.9 MiB 1.39 403 300 744 201 529 14 65.6 MiB 0.01 0.00 3.89713 3.62628 -64.1883 -3.62628 3.62628 0.02 0.000200715 0.000184274 0.00449226 0.00423814 -1 -1 -1 -1 36 756 35 403230 176413 82124.2 2281.23 0.15 0.0526833 0.045269 3630 14583 -1 550 23 686 1034 36633 15919 4.66971 4.66971 -82.2718 -4.66971 0 0 100559. 2793.30 0.00 0.02 0.01 -1 -1 0.00 0.0130599 0.0117913 37 51 57 11 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 5.30 vpr 65.45 MiB 1.11 65280 -1 -1 1 0.02 -1 -1 30616 -1 -1 5 17 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67016 17 16 251 206 1 120 38 5 5 25 clb auto 25.9 MiB 3.28 489 407 2495 683 1791 21 65.4 MiB 0.02 0.00 3.91442 3.88071 -74.5105 -3.88071 3.88071 0.01 0.000248397 0.000228904 0.0121506 0.0113203 -1 -1 -1 -1 50 657 26 151211 126010 61632.8 2465.31 0.13 0.0691504 0.0602187 2268 9834 -1 542 20 727 1123 36489 16871 4.71841 4.71841 -93.0154 -4.71841 0 0 77226.2 3089.05 0.00 0.02 0.01 -1 -1 0.00 0.0153429 0.0139339 45 66 75 13 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 5.72 vpr 65.76 MiB 1.12 66432 -1 -1 1 0.03 -1 -1 30284 -1 -1 7 19 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67336 19 18 308 249 1 134 44 6 6 36 clb auto 25.8 MiB 3.62 593 481 1815 377 1429 9 65.8 MiB 0.02 0.00 4.92231 4.8546 -99.9033 -4.8546 4.8546 0.02 0.000312002 0.000288444 0.0097168 0.00911256 -1 -1 -1 -1 68 826 27 403230 176413 143382. 3982.83 0.18 0.0775224 0.0678547 4366 25715 -1 720 17 520 914 34542 12871 4.61234 4.61234 -99.3851 -4.61234 0 0 176130. 4892.50 0.00 0.02 0.02 -1 -1 0.00 0.0163957 0.0151214 53 83 93 14 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt index 8a6305788b..a49d1d9aff 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - sub_tiles.xml sub_tiles.blif common 17.34 vpr 59.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60480 6 7 19 26 0 19 26 3 3 9 -1 auto 20.6 MiB 0.00 51 216 43 63 110 59.1 MiB 0.00 0.00 3.682 -25.774 -3.682 nan 15.93 4.894e-05 4.1022e-05 0.00272802 0.000370563 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.13 0.00475066 0.00224296 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.05 -1 -1 0.00 0.00235645 0.00226006 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common 4.61 vpr 57.15 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58520 6 7 19 26 0 19 26 3 3 9 -1 auto 18.3 MiB 0.00 51 51 216 43 63 110 57.1 MiB 0.00 0.00 3.92819 3.682 -25.774 -3.682 nan 3.89 2.224e-05 1.7929e-05 0.000209289 0.000167911 -1 -1 -1 -1 6 19 3 14813.4 192574 -1 -1 0.06 0.00150829 0.00137685 1370 14749 -1 19 3 36 39 5813 2852 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00 0.02 -1 -1 0.00 0.00103372 0.000973401 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt index 518626ca87..4de8a3daf1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sub_tiles_directs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - heterogeneous_tile.xml sub_tile_directs.blif common 0.35 vpr 58.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 60280 2 2 4 5 0 4 5 3 3 9 -1 auto 20.6 MiB 0.00 8 12 0 0 12 58.9 MiB 0.00 0.00 1.899 -3.798 -1.899 nan 0.03 1.7797e-05 1.2853e-05 0.000104532 7.7041e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.01 0.00210372 0.00170648 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.0014857 0.00144705 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +heterogeneous_tile.xml sub_tile_directs.blif common 0.28 vpr 57.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 58424 2 2 4 5 0 4 5 3 3 9 -1 auto 18.7 MiB 0.00 8 8 12 0 0 12 57.1 MiB 0.00 0.00 1.899 1.899 -3.798 -1.899 nan 0.01 9.441e-06 6.18e-06 6.6293e-05 4.7993e-05 -1 -1 -1 -1 3 8 1 0 0 -1 -1 0.00 0.00117047 0.00107644 132 326 -1 8 1 4 4 200 164 2.09013 nan -4.05732 -2.09013 0 0 -1 -1 0.00 0.00 0.00 -1 -1 0.00 0.000883847 0.000852072 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt index 2adfcb2953..0cbb99585c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.13 vpr 66.94 MiB 0.07 9984 -1 -1 3 0.37 -1 -1 39768 -1 -1 19 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68544 99 74 307 381 1 199 193 8 8 64 io memory auto 27.3 MiB 0.07 869 22473 4565 15889 2019 66.9 MiB 0.09 0.00 2.15432 -215.614 -2.15432 2.15432 0.09 0.000919068 0.000833008 0.0321902 0.029066 -1 -1 -1 -1 32 1554 36 2.23746e+06 1.57199e+06 106908. 1670.44 0.41 0.172041 0.155343 4378 18911 -1 1152 12 699 1089 60199 20903 2.21433 2.21433 -220.084 -2.21433 0 0 130676. 2041.82 0.01 0.06 0.03 -1 -1 0.01 0.0316397 0.0293511 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.61 odin 99.75 MiB 2.20 102144 -1 -1 3 0.20 -1 -1 34100 -1 -1 19 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 99 74 307 381 1 197 193 8 8 64 io memory auto 25.6 MiB 0.03 1382 812 18574 3262 13483 1829 65.7 MiB 0.04 0.00 2.24422 2.11879 -214.824 -2.11879 2.11879 0.04 0.000433013 0.000401281 0.016597 0.015422 -1 -1 -1 -1 34 1407 30 2.23746e+06 1.57199e+06 111309. 1739.21 0.31 0.116364 0.104552 4442 19988 -1 1106 23 739 1099 89273 34816 2.38477 2.38477 -220.891 -2.38477 0 0 136889. 2138.88 0.00 0.04 0.01 -1 -1 0.00 0.0224369 0.0204566 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt index b4f05d4d12..beed161e95 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - EArch.xml styr.blif common_--target_ext_pin_util_1 1.31 vpr 68.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70324 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.20 399 703 140 536 27 68.7 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000310541 0.000262563 0.00936798 0.00854482 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.46 0.175458 0.152388 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.01 -1 -1 0.00 0.0280432 0.0256776 - EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.18 vpr 68.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70172 10 10 168 178 1 73 31 6 6 36 clb auto 28.9 MiB 0.19 399 703 140 536 27 68.5 MiB 0.01 0.00 2.34639 -26.9899 -2.34639 2.34639 0.02 0.000328824 0.000280405 0.00830952 0.00754823 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.31 0.10752 0.0932813 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0371511 0.0342602 - EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 4.10 vpr 69.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70728 10 10 168 178 1 162 111 14 14 196 clb auto 29.4 MiB 0.90 1467 5165 686 4267 212 69.1 MiB 0.05 0.00 2.95542 -36.8348 -2.95542 2.95542 0.39 0.000594399 0.00050939 0.0158932 0.0140866 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.49 0.204118 0.178235 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.04 0.10 0.10 -1 -1 0.04 0.0402804 0.0376719 - EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.27 vpr 68.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70312 10 10 168 178 1 75 33 7 7 49 clb auto 29.2 MiB 0.22 414 605 98 486 21 68.7 MiB 0.02 0.00 2.40687 -27.3475 -2.40687 2.40687 0.06 0.000598343 0.000517434 0.011833 0.0108149 -1 -1 -1 -1 26 1062 27 1.07788e+06 700622 75813.7 1547.22 0.28 0.112886 0.100348 3816 13734 -1 940 18 540 1691 67850 23781 2.86939 2.86939 -35.5441 -2.86939 0 0 91376.6 1864.83 0.00 0.05 0.02 -1 -1 0.00 0.0342617 0.0315172 - EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.32 vpr 68.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70636 10 10 168 178 1 163 124 14 14 196 clb auto 29.3 MiB 0.71 1526 7540 1144 6026 370 69.0 MiB 0.04 0.00 3.12689 -38.2571 -3.12689 3.12689 0.24 0.000341831 0.000287957 0.0139093 0.0123738 -1 -1 -1 -1 20 3129 15 9.20055e+06 5.60498e+06 295730. 1508.82 0.36 0.0484505 0.0438885 18004 60473 -1 3052 13 680 3211 188673 40435 3.88935 3.88935 -46.4141 -3.88935 0 0 387483. 1976.95 0.03 0.08 0.07 -1 -1 0.03 0.0262959 0.0240352 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.51 vpr 68.54 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70184 10 10 168 178 1 73 31 6 6 36 clb auto 29.0 MiB 0.19 399 703 140 536 27 68.5 MiB 0.03 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000592996 0.000513744 0.0148871 0.0136124 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.60 0.233947 0.201424 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.05 0.01 -1 -1 0.00 0.0337396 0.0309919 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.26 vpr 68.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69936 10 10 168 178 1 73 31 6 6 36 clb auto 28.8 MiB 0.14 399 703 140 536 27 68.3 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000607215 0.000528624 0.0138198 0.0125584 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.45 0.178959 0.157093 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.01 -1 -1 0.00 0.0299846 0.0274172 - EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 4.05 vpr 68.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70468 10 10 168 178 1 162 111 14 14 196 clb auto 29.3 MiB 0.89 1467 5165 686 4267 212 68.8 MiB 0.05 0.00 2.95542 -36.8348 -2.95542 2.95542 0.31 0.000662054 0.000579378 0.0167691 0.0149922 -1 -1 -1 -1 24 2876 16 9.20055e+06 4.90435e+06 355930. 1815.97 1.58 0.235946 0.204687 18592 71249 -1 2738 14 605 2492 132798 29734 3.39858 3.39858 -42.8555 -3.39858 0 0 449262. 2292.15 0.03 0.07 0.12 -1 -1 0.03 0.0296338 0.0273566 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.49 vpr 68.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69976 10 10 168 178 1 73 31 6 6 36 clb auto 28.8 MiB 0.21 399 703 140 536 27 68.3 MiB 0.02 0.00 2.34639 -26.9899 -2.34639 2.34639 0.04 0.000326035 0.000277526 0.0147842 0.0134826 -1 -1 -1 -1 30 794 18 646728 592834 55714.4 1547.62 0.61 0.214908 0.181228 2692 9921 -1 727 18 505 1726 58085 22424 2.63063 2.63063 -33.1038 -2.63063 0 0 68154.2 1893.17 0.00 0.04 0.02 -1 -1 0.00 0.0279877 0.0256826 - EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.10 vpr 29.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30628 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.7 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.11 vpr 30.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31144 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 28.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.11 vpr 30.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 31020 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.2 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.11 vpr 30.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 30716 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 29.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml styr.blif common_--target_ext_pin_util_1 0.74 vpr 66.83 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68436 10 10 168 178 1 75 32 6 6 36 clb auto 27.5 MiB 0.12 467 424 582 89 470 23 66.8 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000318215 0.000285844 0.00697564 0.00651637 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.13 0.0549471 0.0483289 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0179114 0.0164534 +EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.72 vpr 66.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68232 10 10 168 178 1 75 32 6 6 36 clb auto 27.3 MiB 0.11 467 424 582 89 470 23 66.6 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000303979 0.00027269 0.0068902 0.00644065 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.13 0.0537591 0.0473192 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0181402 0.0166799 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 1.55 vpr 67.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69188 10 10 168 178 1 162 110 14 14 196 clb auto 27.9 MiB 0.42 2218 1472 5633 779 4632 222 67.6 MiB 0.03 0.00 4.05086 3.03976 -37.3505 -3.03976 3.03976 0.14 0.000313482 0.000283471 0.00907432 0.00831983 -1 -1 -1 -1 26 2737 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.30 0.047994 0.0421993 18784 74779 -1 2724 12 481 1718 95989 21869 3.66555 3.66555 -44.1461 -3.66555 0 0 467681. 2386.13 0.01 0.03 0.04 -1 -1 0.01 0.0131228 0.0120698 +EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.79 vpr 67.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68880 10 10 168 178 1 73 34 7 7 49 clb auto 27.9 MiB 0.13 556 403 749 133 594 22 67.3 MiB 0.01 0.00 2.47538 2.3678 -27.2356 -2.3678 2.3678 0.02 0.000307279 0.00028161 0.00737336 0.00690186 -1 -1 -1 -1 28 1121 29 1.07788e+06 754516 79600.7 1624.51 0.14 0.0554092 0.048859 3864 14328 -1 1032 22 640 2278 94416 33063 2.98849 2.98849 -34.8096 -2.98849 0 0 95067.4 1940.15 0.00 0.04 0.01 -1 -1 0.00 0.0201049 0.0183091 +EArch.xml styr.blif common_--target_ext_pin_util_0.0 1.45 vpr 67.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69236 10 10 168 178 1 163 124 14 14 196 clb auto 28.2 MiB 0.44 2325 1534 6922 992 5667 263 67.6 MiB 0.03 0.00 4.16044 3.06133 -37.5377 -3.06133 3.06133 0.15 0.000313903 0.000278072 0.0099182 0.00909839 -1 -1 -1 -1 20 3156 16 9.20055e+06 5.60498e+06 295730. 1508.82 0.16 0.0253782 0.0230502 18004 60473 -1 3023 14 646 2892 171027 37325 3.649 3.649 -45.9039 -3.649 0 0 387483. 1976.95 0.01 0.04 0.03 -1 -1 0.01 0.013617 0.0123981 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 0.73 vpr 66.88 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68484 10 10 168 178 1 75 32 6 6 36 clb auto 27.2 MiB 0.12 467 424 582 89 470 23 66.9 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000320702 0.000273299 0.00689141 0.00642895 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0536186 0.0471862 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.017806 0.0163794 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 0.72 vpr 67.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68812 10 10 168 178 1 75 32 6 6 36 clb auto 27.5 MiB 0.11 467 424 582 89 470 23 67.2 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000303891 0.000272677 0.00685626 0.00641014 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.12 0.0539114 0.0475008 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0176095 0.016187 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 1.56 vpr 67.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69188 10 10 168 178 1 162 110 14 14 196 clb auto 27.9 MiB 0.42 2218 1472 5633 779 4632 222 67.6 MiB 0.03 0.00 4.05086 3.03976 -37.3505 -3.03976 3.03976 0.15 0.000312308 0.000281937 0.00901349 0.00826828 -1 -1 -1 -1 26 2737 13 9.20055e+06 4.85046e+06 387483. 1976.95 0.28 0.049063 0.0432355 18784 74779 -1 2724 12 481 1718 95989 21869 3.66555 3.66555 -44.1461 -3.66555 0 0 467681. 2386.13 0.02 0.03 0.04 -1 -1 0.02 0.0153966 0.0139896 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 0.74 vpr 67.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 10 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 68816 10 10 168 178 1 75 32 6 6 36 clb auto 27.9 MiB 0.11 467 424 582 89 470 23 67.2 MiB 0.01 0.00 2.35562 2.31651 -27.9526 -2.31651 2.31651 0.02 0.000304422 0.000273333 0.00690797 0.0064615 -1 -1 -1 -1 30 842 27 646728 646728 55714.4 1547.62 0.13 0.0543441 0.0478096 2692 9921 -1 714 17 501 1525 53444 20549 2.38855 2.38855 -30.6143 -2.38855 0 0 68154.2 1893.17 0.00 0.03 0.01 -1 -1 0.00 0.0181313 0.0166801 +EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.09 vpr 28.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 29316 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 27.1 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.09 vpr 28.25 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 28932 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 27.1 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_1.0 0.09 vpr 28.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 29468 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 26.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0_clb_1.0 0.09 vpr 29.00 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 29700 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 27.5 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt index 95f2081009..6ad99d63bd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_tight_floorplan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 9.08 vpr 75.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 150 229 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 77084 229 197 2152 2349 1 1013 576 16 16 256 io auto 35.8 MiB 4.29 8858 177806 51921 111135 14750 75.3 MiB 1.45 0.02 2.93018 -671.396 -2.93018 2.93018 0.00 0.00692729 0.00619106 0.572476 0.497763 -1 -1 -1 -1 -1 11350 10 1.05632e+07 8.0841e+06 4.24953e+06 16599.7 0.34 0.862195 0.757255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml bigkey.blif common_-read_vpr_constraints_tasks/regression_tests/vtr_reg_strong/strong_tight_floorplan/bigkey_tight.xml 4.10 vpr 73.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 118 229 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 75160 229 197 2152 2349 1 1012 544 16 16 256 io auto 34.3 MiB 2.07 13816 8635 175845 51740 110676 13429 73.4 MiB 0.62 0.01 3.6187 2.93018 -676.548 -2.93018 2.93018 0.00 0.00283798 0.00249544 0.241352 0.217084 -1 -1 -1 -1 -1 11066 15 1.05632e+07 6.35949e+06 4.24953e+06 16599.7 0.17 0.379716 0.346843 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt index a285dc5eca..14d88ca4ff 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.34 vpr 67.74 MiB 0.06 9856 -1 -1 3 0.39 -1 -1 39776 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69364 99 130 363 493 1 251 298 12 12 144 clb auto 28.5 MiB 0.15 804 66963 21682 33533 11748 67.7 MiB 0.29 0.00 2.23767 -220.613 -2.23767 2.23767 0.27 0.00107588 0.000959454 0.0879605 0.0803385 -1 -1 -1 -1 38 1665 16 5.66058e+06 4.21279e+06 319130. 2216.18 0.81 0.341856 0.310926 12522 62564 -1 1367 8 564 725 39208 13509 2.60043 2.60043 -237.701 -2.60043 0 0 406292. 2821.48 0.03 0.05 0.14 -1 -1 0.03 0.0261531 0.0245164 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.24 odin 100.50 MiB 2.56 102912 -1 -1 3 0.20 -1 -1 33480 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67716 99 130 363 493 1 252 298 12 12 144 clb auto 26.9 MiB 0.07 2018 885 69948 23010 34855 12083 66.1 MiB 0.12 0.00 2.57832 2.17528 -217.156 -2.17528 2.17528 0.09 0.000528944 0.000494779 0.0406305 0.0380401 -1 -1 -1 -1 40 1646 17 5.66058e+06 4.21279e+06 333335. 2314.82 0.33 0.153201 0.140265 12666 64609 -1 1625 10 525 650 46110 15051 2.57635 2.57635 -244.199 -2.57635 0 0 419432. 2912.72 0.01 0.03 0.04 -1 -1 0.01 0.01659 0.0155376 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt index ddf76e6dee..837f472eb4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_fail/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.16 vpr 67.80 MiB 0.06 9984 -1 -1 3 0.37 -1 -1 39748 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69432 99 130 363 493 1 251 298 12 12 144 clb auto 28.7 MiB 0.14 877 59998 22493 27317 10188 67.8 MiB 0.17 0.00 2.17528 -133.517 -2.17528 2.17528 0.25 0.000598743 0.00053199 0.0416228 0.0366674 -1 -1 -1 -1 40 1685 15 5.66058e+06 4.21279e+06 333335. 2314.82 1.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/impossible_pass_timing.sdc 3.83 odin 100.12 MiB 2.31 102528 -1 -1 3 0.20 -1 -1 34240 -1 -1 68 99 1 0 exited with return code 1 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67928 99 130 363 493 1 252 298 12 12 144 clb auto 27.1 MiB 0.07 2007 832 63978 23229 30524 10225 66.3 MiB 0.09 0.00 2.23767 2.17638 -131.403 -2.17638 2.17638 0.09 0.000343257 0.000316088 0.0239793 0.0221824 -1 -1 -1 -1 40 1539 8 5.66058e+06 4.21279e+06 333335. 2314.82 0.45 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt index 4503f0925f..c421de990b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_no_fail/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 3.64 vpr 67.62 MiB 0.06 9856 -1 -1 3 0.30 -1 -1 39896 -1 -1 68 99 1 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 69248 99 130 363 493 1 252 298 12 12 144 clb auto 28.5 MiB 0.14 956 73928 27133 34341 12454 67.6 MiB 0.26 0.00 2.30557 0 0 2.30557 0.25 0.000962793 0.000867177 0.0597068 0.0524058 -1 -1 -1 -1 38 1840 8 5.66058e+06 4.21279e+06 319130. 2216.18 1.37 0.282428 0.244945 12522 62564 -1 1734 8 415 510 29213 8865 2.61298 2.61298 0 0 0 0 406292. 2821.48 0.02 0.03 0.09 -1 -1 0.02 0.0187719 0.0170722 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common_-sdc_file_sdc/samples/easy_pass_timing.sdc 2.02 odin 99.38 MiB 0.19 101760 -1 -1 3 0.20 -1 -1 34100 -1 -1 68 99 1 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67928 99 130 363 493 1 253 298 12 12 144 clb auto 27.5 MiB 0.07 1922 792 82883 30333 38996 13554 66.3 MiB 0.12 0.00 2.3756 2.31285 0 0 2.31285 0.09 0.000331378 0.000305141 0.0302311 0.0279261 -1 -1 -1 -1 38 1683 10 5.66058e+06 4.21279e+06 319130. 2216.18 0.43 0.2022 0.172985 12522 62564 -1 1509 8 399 488 29742 9782 3.03498 3.03498 0 0 0 0 406292. 2821.48 0.01 0.02 0.04 -1 -1 0.01 0.00995122 0.00912237 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt index 0a5e59f029..f7c73ad0d4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.62 vpr 67.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68616 5 3 11 14 2 9 10 4 4 16 clb auto 28.6 MiB 0.01 21 30 9 19 2 67.0 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 4.8501e-05 3.4711e-05 0.00027851 0.000219913 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00215999 0.00198392 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.00181366 0.00173531 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.62 vpr 67.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68636 5 3 11 14 2 9 10 4 4 16 clb auto 28.5 MiB 0.01 21 30 9 19 2 67.0 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 5.1152e-05 3.666e-05 0.000287379 0.000227035 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.03 0.0023614 0.00216487 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.0022135 0.00167838 - k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.55 vpr 67.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68936 5 3 11 14 2 9 10 4 4 16 clb auto 28.9 MiB 0.01 21 30 9 19 2 67.3 MiB 0.00 0.00 0.620042 -3.41492 -0.620042 0.545 0.01 5.7208e-05 4.2383e-05 0.000322556 0.000257546 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.02 0.00215648 0.00197387 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.01 0.00 -1 -1 0.00 0.00181267 0.00173458 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.38 vpr 65.69 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67264 5 3 11 14 2 9 10 4 4 16 clb auto 27.1 MiB 0.00 24 21 30 9 19 2 65.7 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 3.3685e-05 2.6567e-05 0.000176156 0.000142145 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0012472 0.00113885 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00105449 0.00100376 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.39 vpr 65.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66872 5 3 11 14 2 9 10 4 4 16 clb auto 27.1 MiB 0.00 24 21 30 9 19 2 65.3 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.3413e-05 1.6094e-05 0.000169182 0.000135305 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.00129475 0.00118612 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00106629 0.00101606 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.38 vpr 65.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66904 5 3 11 14 2 9 10 4 4 16 clb auto 26.8 MiB 0.00 24 21 30 9 19 2 65.3 MiB 0.00 0.00 0.713166 0.620042 -3.41492 -0.620042 0.545 0.00 2.3273e-05 1.6103e-05 0.000163476 0.000130225 -1 -1 -1 -1 20 24 1 107788 107788 10441.3 652.579 0.01 0.0012479 0.00114186 750 1675 -1 23 1 7 7 146 95 0.563256 0.545 -3.71515 -0.563256 0 0 13752.8 859.551 0.00 0.00 0.00 -1 -1 0.00 0.00105471 0.00100166 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt index 9d457582f1..c2be7db575 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.68 vpr 69.25 MiB 0.08 10496 -1 -1 5 0.17 -1 -1 36364 -1 -1 14 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 70908 11 30 313 321 2 115 55 7 7 49 clb auto 29.8 MiB 0.39 448 1927 352 1502 73 69.2 MiB 0.04 0.00 2.6627 -173.06 -2.6627 2.30313 0.00 0.000798161 0.000674358 0.0213182 0.0191108 -1 -1 -1 -1 -1 595 8 1.07788e+06 754516 219490. 4479.39 0.04 0.060298 0.0550487 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 4.59 odin 156.75 MiB 2.86 160512 -1 -1 5 0.11 -1 -1 33040 -1 -1 14 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 69036 11 30 313 321 2 114 55 7 7 49 clb auto 28.1 MiB 0.19 671 455 1719 301 1356 62 67.4 MiB 0.02 0.00 2.73611 2.6413 -165.526 -2.6413 2.31106 0.00 0.000436888 0.00038314 0.0112765 0.0101768 -1 -1 -1 -1 -1 571 12 1.07788e+06 754516 219490. 4479.39 0.02 0.0313028 0.0285028 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt index 070113b937..b4552167e5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_timing_update_type/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 1.31 vpr 66.76 MiB 0.06 10368 -1 -1 4 0.22 -1 -1 36924 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68364 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.08 425 2283 406 1804 73 66.8 MiB 0.04 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000550429 0.00044745 0.0205892 0.0175295 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0715823 0.0554655 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 1.35 vpr 67.11 MiB 0.08 10368 -1 -1 4 0.22 -1 -1 36664 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 68720 11 30 262 292 2 99 60 7 7 49 clb auto 27.5 MiB 0.09 425 2283 406 1804 73 67.1 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000592669 0.000483133 0.0176652 0.0153201 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.08 0.0695138 0.0618702 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 1.40 vpr 66.21 MiB 0.07 10368 -1 -1 4 0.18 -1 -1 36668 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67804 11 30 262 292 2 99 60 7 7 49 clb auto 27.1 MiB 0.09 425 2283 406 1804 73 66.2 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000259913 0.000168736 0.00804711 0.00632437 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.05 0.0326926 0.0257255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 1.40 vpr 66.24 MiB 0.07 10368 -1 -1 4 0.22 -1 -1 36412 -1 -1 19 11 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 67828 11 30 262 292 2 99 60 7 7 49 clb auto 27.3 MiB 0.09 425 2283 406 1804 73 66.2 MiB 0.03 0.00 2.45115 -182.341 -2.45115 2.3368 0.00 0.000820125 0.000270462 0.0105947 0.00836537 -1 -1 -1 -1 -1 414 20 1.07788e+06 1.02399e+06 207176. 4228.08 0.07 0.0358221 0.028376 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 3.60 odin 166.88 MiB 2.66 170880 -1 -1 4 0.13 -1 -1 33280 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 66768 11 30 262 292 2 99 61 7 7 49 clb auto 25.5 MiB 0.04 688 437 2341 384 1888 69 65.2 MiB 0.02 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000395156 0.000341516 0.0102679 0.0090536 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.03 0.0322466 0.0280758 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 3.51 odin 167.25 MiB 2.57 171264 -1 -1 4 0.12 -1 -1 33076 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67268 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 0.02 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.000413775 0.000358594 0.0103638 0.00913727 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.03 0.0330507 0.0288222 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 3.69 odin 166.88 MiB 2.75 170880 -1 -1 4 0.12 -1 -1 33100 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67312 11 30 262 292 2 99 61 7 7 49 clb auto 25.6 MiB 0.04 688 437 2341 384 1888 69 65.7 MiB 0.01 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 2.2455e-05 6.817e-06 0.00420545 0.00333599 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.02 0.0164335 0.0121801 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 3.50 odin 167.25 MiB 2.58 171264 -1 -1 4 0.12 -1 -1 33076 -1 -1 20 11 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 67076 11 30 262 292 2 99 61 7 7 49 clb auto 25.8 MiB 0.04 688 437 2341 384 1888 69 65.5 MiB 0.01 0.00 2.91853 2.7389 -178.372 -2.7389 2.43544 0.00 0.00042027 7.6147e-05 0.00464448 0.00344743 -1 -1 -1 -1 -1 434 23 1.07788e+06 1.07788e+06 207176. 4228.08 0.02 0.0166439 0.012083 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt index ec4372e5ea..673bf352e8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 76.86 vpr 1.16 GiB 42 758 0 0 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1215732 13 29 26295 20086 1 12439 800 39 29 1131 LAB auto 1063.5 MiB 14.49 75097 245792 47628 188491 9673 1158.4 MiB 19.32 0.31 4.99421 -5497.03 -3.99421 2.87584 0.01 0.0645942 0.0566793 4.57717 3.66743 87123 7.00515 21186 1.70347 25964 36365 9630576 1720385 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.30154 2.77187 -5700.98 -4.30154 0 0 8.99 -1 -1 1158.4 MiB 6.77 7.11559 5.86421 1158.4 MiB -1 3.90 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 33.45 vpr 1.16 GiB 42 749 0 0 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1215128 13 29 26295 20086 1 12646 791 39 29 1131 LAB auto 1077.7 MiB 7.76 231619 75107 234775 43541 180854 10380 1154.5 MiB 5.72 0.08 5.55061 5.16398 -5504.03 -4.16398 2.86102 0.00 0.0202234 0.0176008 1.61204 1.32664 87307 6.90501 21230 1.67906 25811 34329 9106433 1637889 0 0 2.05929e+07 18207.7 13 331560 3499109 -1 5.36451 2.98815 -5707.14 -4.36451 0 0 3.40 -1 -1 1154.5 MiB 2.57 2.62249 2.22124 1154.5 MiB -1 1.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt index 9097fbde85..661d83a8e0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 18.00 vpr 70.38 MiB 0.05 10112 -1 -1 6 0.25 -1 -1 38052 -1 -1 15 66 0 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 72072 66 96 1000 687 1 578 192 18 18 324 mult_27 auto 31.1 MiB 2.15 5241 46091 14804 26339 4948 70.4 MiB 0.71 0.01 16.7702 -967.772 -16.7702 16.7702 0.75 0.00350611 0.00326694 0.374139 0.351063 -1 -1 -1 -1 54 12671 42 6.4517e+06 1.13409e+06 1.49609e+06 4617.55 10.37 1.47511 1.37701 50360 316156 -1 11227 19 3612 7762 1892477 579383 16.9221 16.9221 -1089.8 -16.9221 0 0 1.91711e+06 5917.01 0.13 0.79 0.45 -1 -1 0.13 0.185679 0.177041 133 202 146 33 66 33 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 9.33 odin 81.00 MiB 1.68 82944 -1 -1 6 0.10 -1 -1 34340 -1 -1 16 66 0 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 71400 66 96 1000 687 1 578 193 18 18 324 mult_27 auto 30.4 MiB 0.92 8817 5194 44753 13259 26140 5354 69.7 MiB 0.26 0.00 17.614 16.4128 -968.178 -16.4128 16.4128 0.30 0.0014073 0.00132261 0.124398 0.117084 -1 -1 -1 -1 56 13393 29 6.4517e+06 1.15929e+06 1.55150e+06 4788.57 4.23 0.469667 0.437453 50684 323660 -1 11784 18 3706 7635 1966406 594465 16.8068 16.8068 -1080.85 -16.8068 0 0 1.95585e+06 6036.58 0.05 0.32 0.17 -1 -1 0.05 0.0718067 0.0681523 133 202 146 33 66 33 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt index 9b26c986cc..e643843024 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.53 vpr 65.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66664 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.03 88 59 31 28 0 65.1 MiB 0.01 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.00022667 0.0001997 0.00145978 0.00134015 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.01 -1 -1 65.1 MiB 0.01 0.0151269 0.0141345 65.1 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.49 vpr 65.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66748 6 8 39 47 1 20 17 5 5 25 clb auto 26.8 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.35996 -15.7932 -1.35996 1.35996 0.00 0.000166651 0.000146123 0.00118945 0.00110009 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5197 2020 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 65.2 MiB 0.01 0.0110046 0.0100571 65.2 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.25 vpr 65.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66768 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000189994 0.000167385 0.00110293 0.00101544 -1 -1 -1 -1 -1 -1 -1 -1 654 1027 31303 15229 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 65.2 MiB 0.03 -1 -1 65.2 MiB -1 0.00 - k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.27 vpr 65.18 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 66748 6 8 39 47 1 20 17 5 5 25 clb auto 26.9 MiB 0.02 88 59 31 28 0 65.2 MiB 0.00 0.00 1.36028 -15.8 -1.36028 1.36028 0.00 0.000187343 0.000161123 0.00133988 0.00123837 -1 -1 -1 -1 142 7.47368 66 3.47368 654 1027 31303 15229 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9824 -1.84852 0 0 0.00 -1 -1 65.2 MiB 0.04 -1 -1 65.2 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.18 vpr 63.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65280 6 8 39 47 1 20 17 5 5 25 clb auto 25.6 MiB 0.01 107 88 59 31 28 0 63.8 MiB 0.00 0.00 1.35996 1.35996 -15.7932 -1.35996 1.35996 0.00 7.95e-05 7.0842e-05 0.000731547 0.000688264 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5199 2021 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 63.8 MiB 0.01 0.00503698 0.00449014 63.8 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.17 vpr 63.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 64948 6 8 39 47 1 20 17 5 5 25 clb auto 24.7 MiB 0.01 107 88 59 31 28 0 63.4 MiB 0.00 0.00 1.35996 1.35996 -15.7932 -1.35996 1.35996 0.00 8.6645e-05 7.8106e-05 0.000722456 0.000680613 -1 -1 -1 -1 77 4.05263 38 2.00000 131 232 5199 2021 323364 161682 20103.2 804.128 18 1140 2762 -1 1.30886 1.30886 -16.2255 -1.30886 0 0 0.00 -1 -1 63.4 MiB 0.01 0.00495254 0.0044188 63.4 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.18 vpr 63.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65456 6 8 39 47 1 20 17 5 5 25 clb auto 25.2 MiB 0.01 107 88 59 31 28 0 63.9 MiB 0.00 0.00 1.36028 1.36028 -15.8 -1.36028 1.36028 0.00 8.0337e-05 7.1715e-05 0.000713888 0.000671769 -1 -1 -1 -1 -1 -1 -1 -1 656 1029 31338 15241 -1 -1 -1 -1 -1 996 1634 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 63.9 MiB 0.02 -1 -1 63.9 MiB -1 0.00 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.19 vpr 63.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 65452 6 8 39 47 1 20 17 5 5 25 clb auto 25.2 MiB 0.01 107 88 59 31 28 0 63.9 MiB 0.00 0.00 1.36028 1.36028 -15.8 -1.36028 1.36028 0.00 7.9041e-05 7.056e-05 0.000715746 0.000673799 -1 -1 -1 -1 141 7.42105 65 3.42105 656 1029 31338 15241 323364 161682 9037.03 361.481 -1 996 1634 -1 1.84852 1.84852 -21.9119 -1.84852 0 0 0.00 -1 -1 63.9 MiB 0.02 -1 -1 63.9 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt index a8c8aed1d5..f1eab466d0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.42 vpr 61.41 MiB 0.07 9984 -1 -1 6 0.21 -1 -1 36540 -1 -1 69 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62880 11 30 336 366 2 175 110 11 11 121 clb auto 21.7 MiB 0.07 1099 5370 731 4291 348 61.4 MiB 0.07 0.00 3.52668 -265.051 -3.52668 3.51868 0.00 0.000895008 0.000764708 0.0287001 0.0253164 -1 -1 -1 -1 1048 6.12865 1048 6.12865 944 2940 139156 30294 180575 153823 597941. 4941.66 16 20106 83797 -1 3.39028 3.32725 -266.23 -3.39028 -0.21991 -0.0734 0.19 -1 -1 61.4 MiB 0.11 0.0797492 0.0714232 61.4 MiB -1 0.02 - k6_frac_N10_40nm.xml stereovision3.v common 1.89 vpr 62.21 MiB 0.06 9984 -1 -1 4 0.20 -1 -1 36668 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63704 11 30 262 292 2 110 54 6 6 36 clb auto 22.6 MiB 0.15 403 1584 300 1231 53 62.2 MiB 0.04 0.00 2.57043 -171.01 -2.57043 2.32238 0.00 0.000808513 0.00071129 0.0212101 0.0190689 -1 -1 -1 -1 496 4.67925 221 2.08491 205 325 10915 3976 862304 700622 161034. 4473.17 9 3844 24048 -1 2.61311 2.27483 -177.098 -2.61311 0 0 0.05 -1 -1 62.2 MiB 0.04 0.0510796 0.0464992 62.2 MiB -1 0.00 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_90nm.xml stereovision3.v common 2.89 odin 150.38 MiB 1.43 153984 -1 -1 6 0.13 -1 -1 33108 -1 -1 65 11 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61452 11 30 336 366 2 170 106 11 11 121 clb auto 20.2 MiB 0.03 1794 1031 5856 842 4573 441 60.0 MiB 0.03 0.00 6.01276 3.5056 -244.76 -3.5056 3.41098 0.00 0.000488407 0.00042394 0.0143258 0.0124795 -1 -1 -1 -1 976 5.87952 976 5.87952 913 2746 123850 27697 180575 144906 597941. 4941.66 13 20106 83797 -1 3.39028 3.23041 -241.825 -3.39028 -0.29331 -0.0734 0.06 -1 -1 60.0 MiB 0.04 0.0373196 0.0327378 60.0 MiB -1 0.01 +k6_frac_N10_40nm.xml stereovision3.v common 2.72 odin 151.50 MiB 1.49 155136 -1 -1 4 0.12 -1 -1 33092 -1 -1 13 11 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61812 11 30 262 292 2 107 54 6 6 36 clb auto 21.0 MiB 0.07 561 400 1890 329 1495 66 60.4 MiB 0.02 0.00 2.44705 2.33435 -170.194 -2.33435 2.21316 0.00 0.000391369 0.000340655 0.0103276 0.00922097 -1 -1 -1 -1 486 4.71845 224 2.17476 223 387 11633 4030 862304 700622 161034. 4473.17 11 3844 24048 -1 2.35133 2.20841 -178.735 -2.35133 0 0 0.01 -1 -1 60.4 MiB 0.02 0.0264885 0.0239184 60.4 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt index c745d2940f..26a328ea29 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k4_N4_90nm.xml stereovision3.v common 2.36 vpr 61.16 MiB 0.06 9984 -1 -1 6 0.24 -1 -1 36564 -1 -1 69 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 62624 11 30 336 366 2 175 110 11 11 121 clb auto 21.6 MiB 0.08 1099 5370 731 4291 348 61.2 MiB 0.08 0.00 3.52668 -265.051 -3.52668 3.51868 0.00 0.00109238 0.000939106 0.0296397 0.0256861 -1 -1 -1 -1 1048 6.12865 1048 6.12865 944 2940 139156 30294 180575 153823 597941. 4941.66 16 20106 83797 -1 3.39028 3.32725 -266.23 -3.39028 -0.21991 -0.0734 0.18 -1 -1 61.2 MiB 0.09 0.0740596 0.0653877 61.2 MiB -1 0.03 - k6_frac_N10_40nm.xml stereovision3.v common 1.71 vpr 62.40 MiB 0.03 10112 -1 -1 4 0.22 -1 -1 36668 -1 -1 13 11 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 63900 11 30 262 292 2 110 54 6 6 36 clb auto 22.9 MiB 0.13 403 1584 300 1231 53 62.4 MiB 0.04 0.00 2.57043 -171.01 -2.57043 2.32238 0.00 0.000733682 0.000641677 0.0178767 0.0155436 -1 -1 -1 -1 496 4.67925 221 2.08491 205 325 10915 3976 862304 700622 161034. 4473.17 9 3844 24048 -1 2.61311 2.27483 -177.098 -2.61311 0 0 0.04 -1 -1 62.4 MiB 0.04 0.0527381 0.04796 62.4 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +k4_N4_90nm.xml stereovision3.v common 2.70 odin 150.38 MiB 1.41 153984 -1 -1 6 0.13 -1 -1 33088 -1 -1 65 11 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61452 11 30 336 366 2 170 106 11 11 121 clb auto 20.2 MiB 0.03 1794 1031 5856 842 4573 441 60.0 MiB 0.03 0.00 6.01276 3.5056 -244.76 -3.5056 3.41098 0.00 0.000497775 0.000433363 0.0139955 0.0121762 -1 -1 -1 -1 976 5.87952 976 5.87952 913 2746 123850 27697 180575 144906 597941. 4941.66 13 20106 83797 -1 3.39028 3.23041 -241.825 -3.39028 -0.29331 -0.0734 0.06 -1 -1 60.0 MiB 0.03 0.0306655 0.026842 60.0 MiB -1 0.01 +k6_frac_N10_40nm.xml stereovision3.v common 2.71 odin 151.50 MiB 1.50 155136 -1 -1 4 0.12 -1 -1 33096 -1 -1 13 11 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 61808 11 30 262 292 2 107 54 6 6 36 clb auto 21.4 MiB 0.07 561 400 1890 329 1495 66 60.4 MiB 0.02 0.00 2.44705 2.33435 -170.194 -2.33435 2.21316 0.00 0.000402419 0.000348636 0.010636 0.00949069 -1 -1 -1 -1 486 4.71845 224 2.17476 223 387 11633 4030 862304 700622 161034. 4473.17 11 3844 24048 -1 2.35133 2.20841 -178.735 -2.35133 0 0 0.01 -1 -1 60.4 MiB 0.02 0.0275467 0.0248744 60.4 MiB -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt index 8249d51c4a..d52059ea85 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - stratixiv_arch.timing.xml styr.blif common 34.23 vpr 978.34 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 1001816 10 10 168 178 1 68 30 11 8 88 io auto 955.5 MiB 0.58 371 490 69 397 24 978.3 MiB 0.06 0.00 6.66046 -72.2933 -6.66046 6.66046 0.00 0.000593468 0.00051514 0.0111956 0.0102241 -1 -1 -1 -1 549 8.19403 169 2.52239 264 964 62268 28521 0 0 194014. 2204.70 13 11730 32605 -1 6.70864 6.70864 -73.3171 -6.70864 0 0 0.08 -1 -1 978.3 MiB 0.07 0.0418866 0.0386921 978.3 MiB -1 0.01 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +stratixiv_arch.timing.xml styr.blif common 21.78 vpr 980.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-12603-g716d96fe0-dirty release IPO VTR_ASSERT_LEVEL=2 Clang 18.1.3 on Linux-6.8.0-58-generic x86_64 2025-05-01T22:32:41 betzgrp-wintermute /home/zhan6738/VTR/vtr-verilog-to-routing/vtr_flow/tasks 1003552 10 10 168 178 1 65 30 11 8 88 io auto 953.5 MiB 0.34 530 402 720 97 571 52 980.0 MiB 0.06 0.00 6.8225 6.61671 -72.4654 -6.61671 6.61671 0.00 0.000306484 0.000274172 0.0081464 0.00757142 -1 -1 -1 -1 669 10.4531 198 3.09375 255 965 67200 31259 0 0 194014. 2204.70 14 11730 32605 -1 6.73871 6.73871 -74.3689 -6.73871 0 0 0.04 -1 -1 980.0 MiB 0.05 0.0248116 0.0230171 980.0 MiB -1 0.01