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Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase
Odin II Logic Synthesis Tool: Verilog Preproc and Parser related
Odin II Logic Synthesis Tool: regression test related
Odin II Logic Synthesis Tool: Simulation related
Odin II Logic Synthesis Tool: Technology Mapping High level contruct into hard or soft logic
Odin II Logic Synthesis Tool: Unsorted item
Pull requests that update Python code
Regression against previous behaviour
Utility & Infrastructure scripts
Pull requests that update Submodules code
The Titan benchmarks: www.eecg.utoronto.ca/~kmurray/titan
VPR FPGA Placement & Routing Tool
The VTR verilog benchmarks included with the VTR Flow
VTR Design Flow (scripts/benchmarks/architectures)
The Yosys+Odin-II synthesizer: the Yosys coarse-grained Tcl script and Odin-II partial mapping flow
Yosys synthesizer and its interaction with VTR
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