[LibArchFPGA] Updating Model Data Structures

The logical models (the technology-mapped logical blocks) for an
architecture were stored using two independent linked lists. One for the
library models (the models that all architectures have, such as luts and
ffs) and one of the user models. This linked lists were hard to traverse
and were injecting pointers all across VPR.

Created a new class to store and manage the logical models. This class
maintains a unique ID for each logical model (similar to the netlist
data structures in VPR). It also contains helper methods to make working
with the logical models easier.

Author: AlexandreSinger

libs/libarchfpga/src/arch_check.cpp

@@ -26,7 +26,7 @@ extern "C" {
  * @param file architecture file
  * @param line line in the architecture file that generates the failure
  */
-bool check_model_clocks(t_model* model, const char* file, uint32_t line);
+bool check_model_clocks(const t_model& model, const char* file, uint32_t line);
 
 /**
  * @brief Checks the correctness of the combinational sinks in the model inputs to outputs connections
@@ -35,7 +35,7 @@ bool check_model_clocks(t_model* model, const char* file, uint32_t line);
  * @param file architecture file
  * @param line line in the architecture file that generates the failure
  */
-bool check_model_combinational_sinks(const t_model* model, const char* file, uint32_t line);
+bool check_model_combinational_sinks(const t_model& model, const char* file, uint32_t line);
 
 /**
  * @brief Checks whether the I/O ports can have timing specifications based on their connectivity.
@@ -47,7 +47,7 @@ bool check_model_combinational_sinks(const t_model* model, const char* file, uin
  * @param file architecture file
  * @param line line in the architecture file that generates the failure
  */
-void warn_model_missing_timing(const t_model* model, const char* file, uint32_t line);
+void warn_model_missing_timing(const t_model& model, const char* file, uint32_t line);
 
 /**
  * @brief Checks the consistency of the mappings between a logical block and the corresponding physical tile.

libs/libarchfpga/src/arch_check.h

@@ -18,18 +18,9 @@
 /* Value for UNDEFINED data */
 constexpr int UNDEFINED = -1;
 
-/** The total number of predefined blif models */
-constexpr int NUM_MODELS_IN_LIBRARY = 4;
-
 /* Maximum value for minimum channel width to avoid overflows of short data type.               */
 constexpr int MAX_CHANNEL_WIDTH = 8000;
 
-/* Built-in library models */
-constexpr const char* MODEL_NAMES = ".names";
-constexpr const char* MODEL_LATCH = ".latch";
-constexpr const char* MODEL_INPUT = ".input";
-constexpr const char* MODEL_OUTPUT = ".output";
-
 enum class e_arch_format {
     VTR,            ///<VTR-specific device XML format
     FPGAInterchange ///<FPGA Interchange device format