Merge branch 'master' into placement_search_range

Author: amin1377

.clang-format

@@ -69,6 +69,7 @@ IndentCaseLabels: true
 IndentWidth:     4
 IndentWrappedFunctionNames: false
 IndentPPDirectives: None
+InsertNewlineAtEOF: true
 JavaScriptQuotes: Leave
 JavaScriptWrapImports: true
 KeepEmptyLinesAtTheStartOfBlocks: true

.github/workflows/stale.yml

@@ -0,0 +1,31 @@
+name: 'Close Stale Issues'
+on:
+  schedule:
+    # Run everyday at 1 PM UTC
+    - cron: '0 13 * * *'
+
+jobs:
+  stale:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/stale@v9
+        with:
+          # The message to be shown for stale issues
+          stale-issue-message: 'This issue has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you believe this is still an issue, please add a comment.'
+          close-issue-message: 'This issue has been marked stale for 15 days and has been automatically closed.'
+          # If you want to exempt an issue from being marked stale/deleted, label it as 'no-stale'
+          exempt-issue-labels: 'no-stale'
+          days-before-issue-stale: 365
+          days-before-issue-close: 15
+          # Start from the oldest issues
+          ascending: true
+          
+          # The configuration below can be used to allow the same behaviour with PRs.
+          # Since we currently don't want to close old PRs, it is commented out but 
+          # left here in case we change our mind.
+
+          # stale-pr-message: 'This PR has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you are still working on this PR, please add a comment.'
+          # close-pr-message: 'This PR has been marked stale for 15 days and has been automatically closed.'
+          # exempt-pr-labels: 'no-stale'
+          # days-before-pr-stale: 365
+          # days-before-pr-close: 15

CONTRIBUTING.md

@@ -77,7 +77,7 @@ This information helps us to quickly reproduce (and hopefully fix) the issue:
 
     Tell us what version of VTR you are using (e.g. the output of `vpr --version`), which Operating System and compiler you are using, or any other relevant information about where or how you are building/running VTR.
 
-Once you've gathered all the information [open an Issue](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new?template=bug_report.md) on our issue tracker.
+Once you've gathered all the information [open an Issue](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new?template=bug_report.md) on our issue tracker. Issues that do not have any activity for a year will be automatically marked as stale and will be closed after 15 days of being marked as stale.
 
 If you know how to fix the issue, or already have it coded-up, please also consider [submitting the fix](#submitting-code-to-vtr).
 This is likely the fastest way to get bugs fixed!

Makefile

@@ -48,14 +48,14 @@ ifeq ($(VERBOSE),1)
 override CMAKE_PARAMS := -DVTR_ENABLE_VERBOSE=on ${CMAKE_PARAMS}
 endif
 
-# -s : Suppresss makefile output (e.g. entering/leaving directories)
+# -s : Suppresses makefile output (e.g. entering/leaving directories)
 # --output-sync target : For parallel compilation ensure output for each target is synchronized (make version >= 4.0)
 MAKEFLAGS := -s
 
 SOURCE_DIR := $(PWD)
 BUILD_DIR ?= build
 
-#Check for the cmake exectuable
+#Check for the cmake executable
 CMAKE := $(shell command -v cmake 2> /dev/null)
 
 #Show test log on failures with 'make test'

doc/src/api/vtrutil/index.rst

@@ -11,4 +11,5 @@ VTRUTIL API
    container_utils
    logging
    geometry
+   parallel
    other

doc/src/api/vtrutil/parallel.rst

@@ -0,0 +1,13 @@
+=====
+Parallel
+=====
+
+vtr_thread_pool
+-------------
+.. doxygenfile:: vtr_thread_pool.h
+   :project: vtr
+   :sections: briefdescription detaileddescription func innernamespace enum
+
+.. doxygenclass:: vtr::thread_pool
+   :project: vtr
+   :members:

doc/src/vpr/command_line_usage.rst

@@ -379,6 +379,14 @@ Use the options below to override this default naming behaviour.
 
     .. seealso:: :ref:`Routing Resource XML File <vpr_route_resource_file>`.
 
+.. option:: --read_rr_edge_override <file>
+
+    Reads a file that overrides the intrinsic delay of specific edges in RR graph.
+
+    This option should be used with both :option:`--read_rr_graph` and :option:`--write_rr_graph`. When used this way,
+    VPR reads the RR graph, updates the delays of selected edges using :option:`--read_rr_edge_override`,
+    and writes the updated RR graph. The modified RR graph can then be used in later VPR runs.
+
 .. option:: --read_vpr_constraints <file>
 
     Reads the :ref:`VPR constraints <vpr_constraints>` that the flow must respect from the specified XML file.
@@ -1214,7 +1222,7 @@ Analytical Placement is generally split into three stages:
       Uses the legalized solution as anchor-points to pull the solution to a
       more legal solution (similar to the approach from SimPL :cite:`Kim2013_SimPL`).
 
-    **Default:** ``qp-hybrid``
+    **Default:** ``lp-b2b``
 
 .. option:: --ap_partial_legalizer {bipartitioning | flow-based}
 
@@ -1253,6 +1261,15 @@ Analytical Placement is generally split into three stages:
 
     **Default:** ``annealer``
 
+.. option:: --ap_timing_tradeoff <float>
+
+    Controls the trade-off between wirelength (HPWL) and delay minimization in the AP flow.
+
+    A value of 0.0 makes the AP flow focus completely on wirelength minimization,
+    while a value of 1.0 makes the AP flow focus completely on timing optimization.
+
+    **Default:** ``0.5``
+
 .. option:: --ap_verbosity <int>
 
     Controls the verbosity of the AP flow output.

doc/src/vpr/file_formats.rst

@@ -1100,6 +1100,28 @@ To aid in handling large graphs, rr_graph files can also be :ref:`saved in <file
 
 .. _end:
 
+RR Graph Edge Attribute Override File Format (.txt)
+---------------------------------------------------
+This file lets users override attributes of specific edges in the RR graph. Currently, only the intrinsic delay (Tdel)
+can be changed. The expected format is:
+
+.. code-block:: none
+
+    # edge    Tdel
+    64812     5.9e-11
+    9981      4.2e-11
+    1234      7.1e-11
+    4321      9.4e-11
+    (42, 64)  7.3e-11
+
+.. _end:
+
+Lines starting with # are comments and ignored. Each other line should specify either: an edge ID and its new delay, or
+a source/sink node pair and its delay.
+
+This allows more accurate modeling of switch delays in the RR graph without creating many switch types
+in the architecture file and limiting them to small regions. This can be useful for more detailed modeling of
+a fabricated FPGA where layout differences lead to small delay differences in the same type of routing switch.
 
 Network-on-Chip (NoC) Traffic Flows Format (.flows)
 ---------------------------------------------------

libs/EXTERNAL/libcatch2

@@ -126,7 +126,7 @@ struct t_cluster_placement_primitive {
     t_pb_graph_node* pb_graph_node;
     bool valid;
     float base_cost;        /* cost independent of current status of packing */
-    float incremental_cost; /* cost dependant on current status of packing */
+    float incremental_cost; /* cost dependent on current status of packing */
 };
 
 #endif

libs/libarchfpga/src/cad_types.h

@@ -80,6 +80,10 @@ class DeviceGrid {
     inline int get_height_offset(const t_physical_tile_loc& tile_loc) const {
         return grid_[tile_loc.layer_num][tile_loc.x][tile_loc.y].height_offset;
     }
+    ///@brief Returns true if the given location is the root location (bottom left corner) of a tile.
+    inline bool is_root_location(const t_physical_tile_loc& tile_loc) const {
+        return get_width_offset(tile_loc) == 0 && get_height_offset(tile_loc) == 0;
+    }
 
     ///@brief Returns a rectangle which represents the bounding box of the tile at the given location.
     inline vtr::Rect<int> get_tile_bb(const t_physical_tile_loc& tile_loc) const {

libs/libarchfpga/src/device_grid.h

@@ -71,6 +71,42 @@ bool t_rr_switch_inf::configurable() const {
     return switch_type_is_configurable(type());
 }
 
+bool t_rr_switch_inf::operator==(const t_rr_switch_inf& other) const {
+    return R == other.R
+           && Cin == other.Cin
+           && Cout == other.Cout
+           && Cinternal == other.Cinternal
+           && Tdel == other.Tdel
+           && mux_trans_size == other.mux_trans_size
+           && buf_size == other.buf_size
+           && power_buffer_type == other.power_buffer_type
+           && power_buffer_size == other.power_buffer_size
+           && intra_tile == other.intra_tile
+           && type() == other.type();
+}
+
+std::size_t t_rr_switch_inf::Hasher::operator()(const t_rr_switch_inf& s) const {
+    std::size_t hash_val = 0;
+
+    auto hash_combine = [&hash_val](auto&& val) {
+        hash_val ^= std::hash<std::decay_t<decltype(val)>>{}(val) + 0x9e3779b9 + (hash_val << 6) + (hash_val >> 2);
+    };
+
+    hash_combine(s.R);
+    hash_combine(s.Cin);
+    hash_combine(s.Cout);
+    hash_combine(s.Cinternal);
+    hash_combine(s.Tdel);
+    hash_combine(s.mux_trans_size);
+    hash_combine(s.buf_size);
+    hash_combine(static_cast<int>(s.power_buffer_type));
+    hash_combine(s.power_buffer_size);
+    hash_combine(s.intra_tile);
+    hash_combine(static_cast<int>(s.type()));
+
+    return hash_val;
+}
+
 void t_rr_switch_inf::set_type(SwitchType type_val) {
     type_ = type_val;
 }
@@ -360,4 +396,4 @@ const t_physical_tile_port* t_sub_tile::get_port_by_pin(int pin) const {
     }
 
     return nullptr;
-}
+}

libs/libarchfpga/src/physical_types.cpp

@@ -540,10 +540,13 @@ struct t_port_power {
     bool reverse_scaled; /* Scale by (1-prob) */
 };
 
-//The type of Fc specification
+/**
+ * @enum e_fc_type
+ * @brief The type of Fc specification
+ */
 enum class e_fc_type {
-    IN, //The fc specification for an input pin
-    OUT //The fc specification for an output pin
+    IN, /**< Fc specification for an input pin. */
+    OUT /**< Fc specification for an output pin. */
 };
 
 //The value type of the Fc specification
@@ -1562,6 +1565,7 @@ enum e_directionality {
     UNI_DIRECTIONAL,
     BI_DIRECTIONAL
 };
+
 /* X_AXIS: Data that describes an x-directed wire segment (CHANX)                     *
  * Y_AXIS: Data that describes an y-directed wire segment (CHANY)                     *     
  * BOTH_AXIS: Data that can be applied to both x-directed and y-directed wire segment */
@@ -1584,16 +1588,31 @@ enum class SegResType {
     NUM_RES_TYPES
 };
 
-constexpr std::array<const char*, static_cast<size_t>(SegResType::NUM_RES_TYPES)> RES_TYPE_STRING = {{"GCLK", "GENERAL"}}; //String versions of segment resource types
+/// String versions of segment resource types
+constexpr std::array<const char*, static_cast<size_t>(SegResType::NUM_RES_TYPES)> RES_TYPE_STRING{"GCLK", "GENERAL"};
 
+/// Defines the type of switch block used in FPGA routing.
 enum e_switch_block_type {
+    /// If the type is SUBSET, I use a Xilinx-like switch block where track i in one channel always
+    /// connects to track i in other channels.
     SUBSET,
+
+    /// If type is WILTON, I use a switch block where track i
+    /// does not always connect to track i in other channels.
+    /// See Steve Wilton, PhD Thesis, University of Toronto, 1996.
     WILTON,
+
+    /// The UNIVERSAL switch block is from Y. W. Chang et al, TODAES, Jan. 1996, pp. 80 - 101.
     UNIVERSAL,
+
+    /// The FULL switch block type allows for complete connectivity between tracks.
     FULL,
+
+    /// A CUSTOM switch block has also been added which allows a user to describe custom permutation functions and connection patterns.
+    /// See comment at top of SRC/route/build_switchblocks.c
     CUSTOM
 };
-typedef enum e_switch_block_type t_switch_block_type;
+
 enum e_Fc_type {
     ABSOLUTE,
     FRACTIONAL
@@ -1902,16 +1921,28 @@ struct t_rr_switch_inf {
     bool intra_tile = false;
 
   public:
-    //Returns the type of switch
+    /// Returns the type of switch
     SwitchType type() const;
 
-    //Returns true if this switch type isolates its input and output into
-    //separate DC-connected subcircuits
+    /// Returns true if this switch type isolates its input and output into
+    /// separate DC-connected subcircuits
     bool buffered() const;
 
-    //Returns true if this switch type is configurable
+    /// Returns true if this switch type is configurable
     bool configurable() const;
 
+    bool operator==(const t_rr_switch_inf& other) const;
+
+    /**
+     * @brief Functor for computing a hash value for t_rr_switch_inf.
+     *
+     * This custom hasher enables the use of t_rr_switch_inf objects as keys
+     * in unordered containers such as std::unordered_map or std::unordered_set.
+     */
+    struct Hasher {
+        std::size_t operator()(const t_rr_switch_inf& s) const;
+    };
+
   public:
     void set_type(SwitchType type_val);
 

libs/libarchfpga/src/physical_types.h

@@ -4818,4 +4818,4 @@ static T* get_type_by_name(std::string_view type_name, std::vector<T>& types) {
 
     archfpga_throw(__FILE__, __LINE__,
                    "Could not find type: %s\n", type_name);
-}
+}

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -684,4 +684,4 @@ static void process_noc_overrides(pugi::xml_node noc_overrides_tag,
             bad_tag(override_tag, loc_data, noc_overrides_tag, {"router", "link"});
         }
     }
-}
+}

libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp

@@ -116,4 +116,4 @@ void DeclareModel_bb(FILE* Echo, const t_model* model) {
 
     // endmodule
     fprintf(Echo, "endmodule\n\n");
-}
+}

libs/libarchfpga/src/write_models_bb.cpp

@@ -1,2 +1,2 @@
 #define CATCH_CONFIG_MAIN
-#include "catch2/catch_test_macros.hpp"
+#include "catch2/catch_test_macros.hpp"

libs/libarchfpga/test/main.cpp

@@ -269,4 +269,4 @@ TEST_CASE("Verifying mesh topology creation", "[NoC Arch Tests]") {
             REQUIRE(vtr::isclose(golden_results_y[expected_router_id], test_noc.router_list[expected_router_id].device_y_position));
         }
     }
-}
+}

libs/libarchfpga/test/test_read_xml_arch_file.cpp

@@ -15,4 +15,4 @@ int main() {
 
     log_print_info("Test complete\n");
     return 0;
-}
+}

libs/liblog/src/main.cpp

@@ -53,10 +53,10 @@ void check_rr_graph(const RRGraphView& rr_graph,
                     const vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data,
                     const DeviceGrid& grid,
                     const t_chan_width& chan_width,
-                    const t_graph_type graph_type,
+                    const e_graph_type graph_type,
                     bool is_flat) {
     e_route_type route_type = DETAILED;
-    if (graph_type == GRAPH_GLOBAL) {
+    if (graph_type == e_graph_type::GLOBAL) {
         route_type = GLOBAL;
     }
 

libs/librrgraph/src/base/check_rr_graph.cpp

@@ -10,7 +10,7 @@ void check_rr_graph(const RRGraphView& rr_graph,
                     const vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data,
                     const DeviceGrid& grid,
                     const t_chan_width& chan_width,
-                    const t_graph_type graph_type,
+                    const e_graph_type graph_type,
                     bool is_flat);
 
 void check_rr_node(const RRGraphView& rr_graph,

libs/librrgraph/src/base/check_rr_graph.h

@@ -1,7 +1,5 @@
 #include "get_parallel_segs.h"
 
-/*Gets t_segment_inf for parallel segments as defined by the user. 
- *Segments that have BOTH_AXIS attribute value are always included in the returned vector.*/
 std::vector<t_segment_inf> get_parallel_segs(const std::vector<t_segment_inf>& segment_inf,
                                              t_unified_to_parallel_seg_index& seg_index_map,
                                              enum e_parallel_axis parallel_axis) {