Merge branch 'master' into feature-remove-warnings

Author: AlexandreSinger

.clang-format

@@ -15,7 +15,7 @@ AllowShortIfStatementsOnASingleLine: true
 AllowShortLoopsOnASingleLine: false
 AlwaysBreakAfterDefinitionReturnType: None
 AlwaysBreakAfterReturnType: None
-AlwaysBreakBeforeMultilineStrings: true
+AlwaysBreakBeforeMultilineStrings: false
 AlwaysBreakTemplateDeclarations: true
 BinPackArguments: true
 BinPackParameters: false
@@ -34,7 +34,7 @@ BraceWrapping:
   SplitEmptyFunction: false
   SplitEmptyRecord: true
   SplitEmptyNamespace: true
-BreakBeforeBinaryOperators: All
+BreakBeforeBinaryOperators: NonAssignment
 BreakBeforeBraces: Custom
 BreakBeforeInheritanceComma: false
 BreakBeforeTernaryOperators: true
@@ -68,10 +68,11 @@ IncludeIsMainRegex: '([-_](test|unittest))?$'
 IndentCaseLabels: true
 IndentWidth:     4
 IndentWrappedFunctionNames: false
-IndentPPDirectives: AfterHash
+IndentPPDirectives: None
+InsertNewlineAtEOF: true
 JavaScriptQuotes: Leave
 JavaScriptWrapImports: true
-KeepEmptyLinesAtTheStartOfBlocks: false
+KeepEmptyLinesAtTheStartOfBlocks: true
 MacroBlockBegin: ''
 MacroBlockEnd:   ''
 MaxEmptyLinesToKeep: 1

.github/scripts/install_dependencies.sh

@@ -55,7 +55,7 @@ sudo apt install -y \
   clang-16 \
   clang-17 \
   clang-18 \
-  clang-format-14 \
+  clang-format-18 \
   libtbb-dev
 
 pip install -r requirements.txt

.github/workflows/nightly_test.yml

@@ -22,8 +22,6 @@ on:
   #     - '**.md'
   #     - '**.rst'
   workflow_dispatch:
-  schedule:
-  - cron: '0 0 * * *' # daily
 
 # We want to cancel previous runs for a given PR or branch / ref if another CI
 # run is requested.

.github/workflows/nightly_test_manual.yml

@@ -63,37 +63,44 @@ jobs:
     # TODO: We could expose more parallelism if we had one task list which ran
     #       all of these.
     - name: 'Run Nightly Test 1'
+      if: success() || failure()
       run: |
         source .venv/bin/activate
         ./run_reg_test.py -j12 vtr_reg_nightly_test1
 
     - name: 'Run Nightly Test 2'
+      if: success() || failure()
       run: |
         source .venv/bin/activate
         ./run_reg_test.py -j12 vtr_reg_nightly_test2
 
     - name: 'Run Nightly Test 3'
+      if: success() || failure()
       run: |
         source .venv/bin/activate
         ./run_reg_test.py -j12 vtr_reg_nightly_test3
 
 
     - name: 'Run Nightly Test 4'
+      if: success() || failure()
       run: |
         source .venv/bin/activate
         ./run_reg_test.py -j12 vtr_reg_nightly_test4
 
     - name: 'Run Nightly Test 5'
+      if: success() || failure()
       run: |
         source .venv/bin/activate
         ./run_reg_test.py -j12 vtr_reg_nightly_test5
 
     - name: 'Run Nightly Test 6'
+      if: success() || failure()
       run: |
         source .venv/bin/activate
         ./run_reg_test.py -j12 vtr_reg_nightly_test6
 
     - name: 'Run Nightly Test 7'
+      if: success() || failure()
       run: |
         source .venv/bin/activate
         ./run_reg_test.py -j12 vtr_reg_nightly_test7

.github/workflows/stale.yml

@@ -0,0 +1,31 @@
+name: 'Close Stale Issues'
+on:
+  schedule:
+    # Run everyday at 1 PM UTC
+    - cron: '0 13 * * *'
+
+jobs:
+  stale:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/stale@v9
+        with:
+          # The message to be shown for stale issues
+          stale-issue-message: 'This issue has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you believe this is still an issue, please add a comment.'
+          close-issue-message: 'This issue has been marked stale for 15 days and has been automatically closed.'
+          # If you want to exempt an issue from being marked stale/deleted, label it as 'no-stale'
+          exempt-issue-labels: 'no-stale'
+          days-before-issue-stale: 365
+          days-before-issue-close: 15
+          # Start from the oldest issues
+          ascending: true
+          
+          # The configuration below can be used to allow the same behaviour with PRs.
+          # Since we currently don't want to close old PRs, it is commented out but 
+          # left here in case we change our mind.
+
+          # stale-pr-message: 'This PR has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you are still working on this PR, please add a comment.'
+          # close-pr-message: 'This PR has been marked stale for 15 days and has been automatically closed.'
+          # exempt-pr-labels: 'no-stale'
+          # days-before-pr-stale: 365
+          # days-before-pr-close: 15

.github/workflows/test.yml

@@ -89,6 +89,8 @@ jobs:
       with:
         python-version: 3.10.10
     - uses: actions/checkout@v4
+      with:
+        submodules: 'true'
 
     - name: Install dependencies
       run: ./.github/scripts/install_dependencies.sh

CONTRIBUTING.md

@@ -77,7 +77,7 @@ This information helps us to quickly reproduce (and hopefully fix) the issue:
 
     Tell us what version of VTR you are using (e.g. the output of `vpr --version`), which Operating System and compiler you are using, or any other relevant information about where or how you are building/running VTR.
 
-Once you've gathered all the information [open an Issue](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new?template=bug_report.md) on our issue tracker.
+Once you've gathered all the information [open an Issue](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new?template=bug_report.md) on our issue tracker. Issues that do not have any activity for a year will be automatically marked as stale and will be closed after 15 days of being marked as stale.
 
 If you know how to fix the issue, or already have it coded-up, please also consider [submitting the fix](#submitting-code-to-vtr).
 This is likely the fastest way to get bugs fixed!

Makefile

@@ -48,14 +48,14 @@ ifeq ($(VERBOSE),1)
 override CMAKE_PARAMS := -DVTR_ENABLE_VERBOSE=on ${CMAKE_PARAMS}
 endif
 
-# -s : Suppresss makefile output (e.g. entering/leaving directories)
+# -s : Suppresses makefile output (e.g. entering/leaving directories)
 # --output-sync target : For parallel compilation ensure output for each target is synchronized (make version >= 4.0)
 MAKEFLAGS := -s
 
 SOURCE_DIR := $(PWD)
 BUILD_DIR ?= build
 
-#Check for the cmake exectuable
+#Check for the cmake executable
 CMAKE := $(shell command -v cmake 2> /dev/null)
 
 #Show test log on failures with 'make test'

cmake/modules/AutoClangFormat.cmake

@@ -21,11 +21,11 @@ add_custom_target(format-cpp-files
     COMMAND find ${DIRS_TO_FORMAT_CPP} ${FIND_TO_FORMAT_CPP})
 
 #
-# Use clang-format-14 for code format
+# Use clang-format for code format
 #
 add_custom_target(format-cpp
     COMMAND find ${DIRS_TO_FORMAT_CPP} ${FIND_TO_FORMAT_CPP} |
-    xargs -P ${CPU_COUNT} clang-format-14 -style=file -i)
+    xargs -P ${CPU_COUNT} clang-format-18 -style=file -i)
 
 #
 # Use simple python script for fixing C like boxed comments

dev/pylint_check.py

@@ -132,7 +132,7 @@ def expand_paths():
     """Build a list of all python files to process by going through 'paths_to_lint'"""
 
     paths = []
-    for (path, is_recursive) in paths_to_lint:
+    for path, is_recursive in paths_to_lint:
         # Make sure all hard-coded paths point to .py files
         if path.is_file():
             if path.suffix.lower() != ".py":

dev/submit_slurm.py

@@ -188,7 +188,7 @@ def get_resource_estimates(filepath):
                 mem_bytes = float(match.groupdict()["mem_bytes"])
 
     time_minutes = time_sec / 60
-    mem_mb = mem_bytes / (1024 ** 2)
+    mem_mb = mem_bytes / (1024**2)
 
     return time_minutes, mem_mb
 

dev/vtr_gdb_pretty_printers.py

@@ -7,8 +7,10 @@
 
     https://docs.verilogtorouting.org/en/latest/dev/developing#vtr-pretty-printers
 """
+
 import re
 
+
 # VTR related
 class VtrStrongIdPrinter:
     def __init__(self, val, typename="vtr::StrongId"):

doc/src/api/vpr/mapping.rst

@@ -1,7 +1,7 @@
 ===============
 Netlist mapping
 ===============
-As shown in the previous section, there are multiple levels of abstraction (multiple netlists) in VPR which are the ClusteredNetlist and the AtomNetlist. To fully use these netlists, we provide some functions to map between them. 
+As shown in the previous section, there are multiple levels of abstraction (multiple netlists) in VPR which are the ClusteredNetlist and the AtomNetlist. To fully use these netlists, we provide some functions to map between them.
 
 In this section, we will state how to map between the atom and clustered netlists.
 
@@ -16,11 +16,11 @@ To get the block Id of a cluster in the ClusteredNetlist from the block Id of on
 
 .. code-block:: cpp
 
-    ClusterBlockId clb_index = g_vpr_ctx.atom().lookup.atom_clb(atom_blk_id);
+    ClusterBlockId clb_index = g_vpr_ctx.atom().lookup().atom_clb(atom_blk_id);
 
 
 * Using re_cluster_util.h helper functions
-    
+
 .. code-block:: cpp
 
     ClusterBlockId clb_index = atom_to_cluster(atom_blk_id);
@@ -53,7 +53,7 @@ To get the net Id in the ClusteredNetlist from its Id in the AtomNetlist, use At
 
 .. code-block:: cpp
 
-   ClusterNetId clb_net = g_vpr_ctx.atom().lookup.clb_net(atom_net);
+   ClusterNetId clb_net = g_vpr_ctx.atom().lookup().clb_net(atom_net);
 
 
 Cluster net Id to Atom net Id
@@ -62,4 +62,4 @@ To get the net Id in the AtomNetlist from its Id in the ClusteredNetlist, use At
 
 .. code-block:: cpp
 
-   ClusterNetId atom_net = g_vpr_ctx.atom().lookup.atom_net(clb_net);
+   ClusterNetId atom_net = g_vpr_ctx.atom().lookup().atom_net(clb_net);

doc/src/api/vtrutil/index.rst

@@ -11,4 +11,5 @@ VTRUTIL API
    container_utils
    logging
    geometry
+   parallel
    other

doc/src/api/vtrutil/parallel.rst

@@ -0,0 +1,13 @@
+=====
+Parallel
+=====
+
+vtr_thread_pool
+-------------
+.. doxygenfile:: vtr_thread_pool.h
+   :project: vtr
+   :sections: briefdescription detaileddescription func innernamespace enum
+
+.. doxygenclass:: vtr::thread_pool
+   :project: vtr
+   :members:

doc/src/arch/reference.rst

@@ -849,7 +849,7 @@ Each tile type is specified with the ``<tile>`` tag withing the ``<tiles>`` tag.
 
 Tile
 ~~~~
-.. arch:tag:: <tile name="string" capacity="int" width="int" height="int" area="float"/>
+.. arch:tag:: <tile name="string" width="int" height="int" area="float"/>
 
     A tile refers to a placeable element within an FPGA architecture and describes its physical compositions on the grid.
     The following attributes are applicable to each tile.

doc/src/vpr/command_line_usage.rst

@@ -379,6 +379,14 @@ Use the options below to override this default naming behaviour.
 
     .. seealso:: :ref:`Routing Resource XML File <vpr_route_resource_file>`.
 
+.. option:: --read_rr_edge_override <file>
+
+    Reads a file that overrides the intrinsic delay of specific edges in RR graph.
+
+    This option should be used with both :option:`--read_rr_graph` and :option:`--write_rr_graph`. When used this way,
+    VPR reads the RR graph, updates the delays of selected edges using :option:`--read_rr_edge_override`,
+    and writes the updated RR graph. The modified RR graph can then be used in later VPR runs.
+
 .. option:: --read_vpr_constraints <file>
 
     Reads the :ref:`VPR constraints <vpr_constraints>` that the flow must respect from the specified XML file.
@@ -657,7 +665,7 @@ For people not working on CAD, you can probably leave all the options to their d
 
     .. note::
 
-        If a pin utilization target is unspecified it defaults to 1.0 (i.e. 100% utilization).
+        If some pin utilizations are specified, ``auto`` mode is turned off and the utilization target for any unspecified pin types defaults to 1.0 (i.e. 100% utilization).
 
         For example:
 
@@ -926,6 +934,13 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe
 
     **Default:** ``move_block_type``
 
+.. option:: --place_quench_only {on | off}
+    
+    If this option is set to ``on``, the placement will skip the annealing phase and only perform the placement quench.
+    This option is useful when the the quality of initial placement is good enough and there is no need to perform the 
+    annealing phase.
+
+    **Default:** ``off``
 
 
 .. option:: --placer_debug_block <int>
@@ -1188,6 +1203,44 @@ Analytical Placement is generally split into three stages:
 
     Analytical Placement is experimental and under active development.
 
+.. option:: --ap_analytical_solver {qp-hybrid | lp-b2b}
+
+    Controls which Analytical Solver the Global Placer will use in the AP Flow.
+    The Analytical Solver solves for a placement which optimizes some objective
+    function, ignorant of the FPGA legality constraints. This provides a "lower-
+    bound" solution. The Global Placer will legalize this solution and feed it
+    back to the analytical solver to make its solution more legal.
+
+    * ``qp-hybrid`` Solves for a placement that minimizes the quadratic HPWL of
+      the flat placement using a hybrid clique/star net model (as described in
+      FastPlace :cite:`Viswanathan2005_FastPlace`).
+      Uses the legalized solution as anchor-points to pull the solution to a
+      more legal solution (similar to the approach from SimPL :cite:`Kim2013_SimPL`).
+
+    * ``lp-b2b`` Solves for a placement that minimizes the linear HPWL of the
+      flat placement using the Bound2Bound net model (as described in Kraftwerk2 :cite:`Spindler2008_Kraftwerk2`).
+      Uses the legalized solution as anchor-points to pull the solution to a
+      more legal solution (similar to the approach from SimPL :cite:`Kim2013_SimPL`).
+
+    **Default:** ``lp-b2b``
+
+.. option:: --ap_partial_legalizer {bipartitioning | flow-based}
+
+    Controls which Partial Legalizer the Global Placer will use in the AP Flow.
+    The Partial Legalizer legalizes a placement generated by an Analytical Solver.
+    It is used within the Global Placer to guide the solver to a more legal
+    solution.
+
+    * ``bipartitioning`` Creates minimum windows around over-dense regions of
+      the device bi-partitions the atoms in these windows such that the region
+      is no longer over-dense and the atoms are in tiles that they can be placed
+      into.
+
+    * ``flow-based`` Flows atoms from regions that are overfilled to regions that
+      are underfilled.
+
+    **Default:** ``bipartitioning``
+
 .. option:: --ap_full_legalizer {naive | appack}
 
     Controls which Full Legalizer to use in the AP Flow.
@@ -1198,6 +1251,42 @@ Analytical Placement is generally split into three stages:
 
     **Default:** ``appack``
 
+.. option:: --ap_detailed_placer {none | annealer}
+
+    Controls which Detailed Placer to use in the AP Flow.
+
+    * ``none`` Do not use any Detailed Placer.
+
+    * ``annealer`` Use the Annealer from the Placement stage as a Detailed Placer. This will use the same Placer Options from the Place stage to configure the annealer. 
+
+    **Default:** ``annealer``
+
+.. option:: --ap_timing_tradeoff <float>
+
+    Controls the trade-off between wirelength (HPWL) and delay minimization in the AP flow.
+
+    A value of 0.0 makes the AP flow focus completely on wirelength minimization,
+    while a value of 1.0 makes the AP flow focus completely on timing optimization.
+
+    **Default:** ``0.5``
+
+.. option:: --ap_verbosity <int>
+
+    Controls the verbosity of the AP flow output.
+    Larger values produce more detailed output, which may be useful for
+    debugging the algorithms in the AP flow.
+
+    * ``1 <= verbosity < 10`` Print standard, stage-level messages. This will
+      print messages at the GP, FL, or DP level.
+
+    * ``10 <= verbosity < 20`` Print more detailed messages of what is happening
+      within stages. For example, show high-level information on the legalization
+      iterations within the Global Placer.
+
+    * ``20 <= verbosity`` Print very detailed messages on intra-stage algorithms.
+
+    **Default:** ``1``
+
 
 .. _router_options: