Merge branch 'master' into openfpga

Author: tangxifan

doc/src/vpr/command_line_usage.rst

@@ -1306,6 +1306,15 @@ The following options are only valid when the router is in timing-driven mode (t
 
     **Default:** ``1.2``
 
+.. option:: --astar_offset <float>
+
+    Sets how aggressive the directed search used by the timing-driven router is.
+    It is a subtractive adjustment to the lookahead heuristic.
+
+    Values between 0 and 1e-9 are resonable; higher values may increase quality at the expense of run-time.
+
+    **Default:** ``0.0``
+
 .. option:: --router_profiler_astar_fac <float>
 
     Controls the directedness of the timing-driven router's exploration when doing router delay profiling of an architecture.

vpr/src/base/SetupVPR.cpp

@@ -434,6 +434,7 @@ static void SetupRoutingArch(const t_arch& Arch,
 static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) {
     RouterOpts->do_check_rr_graph = Options.check_rr_graph;
     RouterOpts->astar_fac = Options.astar_fac;
+    RouterOpts->astar_offset = Options.astar_offset;
     RouterOpts->router_profiler_astar_fac = Options.router_profiler_astar_fac;
     RouterOpts->bb_factor = Options.bb_factor;
     RouterOpts->criticality_exp = Options.criticality_exp;

vpr/src/base/ShowSetup.cpp

@@ -382,6 +382,7 @@ static void ShowRouterOpts(const t_router_opts& RouterOpts) {
 
     if (TIMING_DRIVEN == RouterOpts.router_algorithm) {
         VTR_LOG("RouterOpts.astar_fac: %f\n", RouterOpts.astar_fac);
+        VTR_LOG("RouterOpts.astar_offset: %f\n", RouterOpts.astar_offset);
         VTR_LOG("RouterOpts.router_profiler_astar_fac: %f\n", RouterOpts.router_profiler_astar_fac);
         VTR_LOG("RouterOpts.criticality_exp: %f\n", RouterOpts.criticality_exp);
         VTR_LOG("RouterOpts.max_criticality: %f\n", RouterOpts.max_criticality);

vpr/src/base/read_options.cpp

@@ -2499,6 +2499,14 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
         .default_value("1.2")
         .show_in(argparse::ShowIn::HELP_ONLY);
 
+    route_timing_grp.add_argument(args.astar_offset, "--astar_offset")
+        .help(
+            "Controls the directedness of the timing-driven router's exploration."
+            " It is a subtractive adjustment to the lookahead heuristic."
+            " Values between 0 and 1e-9 are resonable; higher values may increase quality at the expense of run-time.")
+        .default_value("0.0")
+        .show_in(argparse::ShowIn::HELP_ONLY);
+
     route_timing_grp.add_argument(args.router_profiler_astar_fac, "--router_profiler_astar_fac")
         .help(
             "Controls the directedness of the timing-driven router's exploration"

vpr/src/base/read_options.h

@@ -220,6 +220,7 @@ struct t_options {
 
     /* Timing-driven router options only */
     argparse::ArgValue<float> astar_fac;
+    argparse::ArgValue<float> astar_offset;
     argparse::ArgValue<float> router_profiler_astar_fac;
     argparse::ArgValue<float> max_criticality;
     argparse::ArgValue<float> criticality_exp;

vpr/src/base/vpr_types.h

@@ -1343,6 +1343,8 @@ struct t_placer_opts {
  *             an essentially breadth-first search, astar_fac = 1 is near   *
  *             the usual astar algorithm and astar_fac > 1 are more         *
  *             aggressive.                                                  *
+ * astar_offset: Offset that is subtracted from the lookahead (expected     *
+ *               future costs) in the timing-driven router.                 *
  * max_criticality: The maximum criticality factor (from 0 to 1) any sink   *
  *                  will ever have (i.e. clip criticality to this number).  *
  * criticality_exp: Set criticality to (path_length(sink) / longest_path) ^ *
@@ -1433,6 +1435,7 @@ struct t_router_opts {
     enum e_router_algorithm router_algorithm;
     enum e_base_cost_type base_cost_type;
     float astar_fac;
+    float astar_offset;
     float router_profiler_astar_fac;
     float max_criticality;
     float criticality_exp;

vpr/src/place/timing_place_lookup.cpp

@@ -1190,7 +1190,8 @@ void OverrideDelayModel::compute_override_delay_model(
     RouterDelayProfiler& route_profiler,
     const t_router_opts& router_opts) {
     t_router_opts router_opts2 = router_opts;
-    router_opts2.astar_fac = 0.;
+    router_opts2.astar_fac = 0.f;
+    router_opts2.astar_offset = 0.f;
 
     //Look at all the direct connections that exist, and add overrides to delay model
     auto& device_ctx = g_vpr_ctx.device();

vpr/src/route/connection_router.cpp

@@ -1,6 +1,7 @@
 #include "connection_router.h"
-#include "rr_graph.h"
 
+#include <algorithm>
+#include "rr_graph.h"
 #include "binary_heap.h"
 #include "four_ary_heap.h"
 #include "bucket.h"
@@ -660,8 +661,8 @@ float ConnectionRouter<Heap>::compute_node_cost_using_rcv(const t_conn_cost_para
     float expected_total_delay_cost;
     float expected_total_cong_cost;
 
-    float expected_total_cong = cost_params.astar_fac * expected_cong + backwards_cong;
-    float expected_total_delay = cost_params.astar_fac * expected_delay + backwards_delay;
+    float expected_total_cong = expected_cong + backwards_cong;
+    float expected_total_delay = expected_delay + backwards_delay;
 
     //If budgets specified calculate cost as described by RCV paper:
     //    R. Fung, V. Betz and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While
@@ -813,7 +814,7 @@ void ConnectionRouter<Heap>::evaluate_timing_driven_node_costs(t_heap* to,
                        rr_node_arch_name(target_node, is_flat_).c_str(),
                        describe_rr_node(device_ctx.rr_graph, device_ctx.grid, device_ctx.rr_indexed_data, target_node, is_flat_).c_str(),
                        expected_cost, to->R_upstream);
-        total_cost += to->backward_path_cost + cost_params.astar_fac * expected_cost;
+        total_cost += to->backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset);
     }
     to->cost = total_cost;
 }
@@ -905,12 +906,8 @@ void ConnectionRouter<Heap>::add_route_tree_node_to_heap(
 
     if (!rcv_path_manager.is_enabled()) {
         // tot_cost = backward_path_cost + cost_params.astar_fac * expected_cost;
-        float tot_cost = backward_path_cost
-                         + cost_params.astar_fac
-                               * router_lookahead_.get_expected_cost(inode,
-                                                                     target_node,
-                                                                     cost_params,
-                                                                     R_upstream);
+        float expected_cost = router_lookahead_.get_expected_cost(inode, target_node, cost_params, R_upstream);
+        float tot_cost = backward_path_cost + cost_params.astar_fac * std::max(0.f, expected_cost - cost_params.astar_offset);
         VTR_LOGV_DEBUG(router_debug_, "  Adding node %8d to heap from init route tree with cost %g (%s)\n",
                        inode,
                        tot_cost,

vpr/src/route/connection_router_interface.h

@@ -23,6 +23,7 @@ struct t_conn_delay_budget {
 struct t_conn_cost_params {
     float criticality = 1.;
     float astar_fac = 1.2;
+    float astar_offset = 0.f;
     float bend_cost = 1.;
     float pres_fac = 1.;
     const t_conn_delay_budget* delay_budget = nullptr;

vpr/src/route/route_net.tpp

@@ -139,6 +139,7 @@ inline NetResultFlags route_net(ConnectionRouter& router,
     t_conn_delay_budget conn_delay_budget;
     t_conn_cost_params cost_params;
     cost_params.astar_fac = router_opts.astar_fac;
+    cost_params.astar_offset = router_opts.astar_offset;
     cost_params.bend_cost = router_opts.bend_cost;
     cost_params.pres_fac = pres_fac;
     cost_params.delay_budget = ((budgeting_inf.if_set()) ? &conn_delay_budget : nullptr);

vpr/src/route/router_delay_profiling.cpp

@@ -95,6 +95,7 @@ bool RouterDelayProfiler::calculate_delay(RRNodeId source_node,
     t_conn_cost_params cost_params;
     cost_params.criticality = 1.;
     cost_params.astar_fac = router_opts.router_profiler_astar_fac;
+    cost_params.astar_offset = router_opts.astar_offset;
     cost_params.bend_cost = router_opts.bend_cost;
 
     route_budgets budgeting_inf(net_list_, is_flat_);
@@ -164,6 +165,7 @@ vtr::vector<RRNodeId, float> calculate_all_path_delays_from_rr_node(RRNodeId src
     t_conn_cost_params cost_params;
     cost_params.criticality = 1.;
     cost_params.astar_fac = router_opts.astar_fac;
+    cost_params.astar_offset = router_opts.astar_offset;
     cost_params.bend_cost = router_opts.bend_cost;
     /* This function is called during placement. Thus, the flat routing option should be disabled. */
     //TODO: Placement is run with is_flat=false. However, since is_flat is passed, det_routing_arch should

vpr/test/test_connection_router.cpp

@@ -41,6 +41,7 @@ static float do_one_route(RRNodeId source_node,
     t_conn_cost_params cost_params;
     cost_params.criticality = router_opts.max_criticality;
     cost_params.astar_fac = router_opts.astar_fac;
+    cost_params.astar_offset = router_opts.astar_offset;
     cost_params.bend_cost = router_opts.bend_cost;
 
     const Netlist<>& net_list = is_flat ? (const Netlist<>&)g_vpr_ctx.atom().nlist : (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist;

vtr_flow/arch/ispd/ultrascale_ispd.xml

@@ -504,12 +504,11 @@
           </pb_type>
           <interconnect>
             <!-- Fracturable LUT connectivity: Based on Fig 3-1 of 'UltraScale Architecture CLB User Guide' UG574 (v1.5) -->
-            <!-- UPDATED based on known legal external ISPD placements -->
-            <complete name="I0" input="LUT6_2.I0" output="LUTX[0].I0 LUTX[1].I0 LUTX[0].I1 LUTX[1].I1 LUTX[0].I2 LUTX[1].I2 LUTX[0].I3 LUTX[1].I3 LUTX[0].I4 LUTX[1].I4"/>
-            <complete name="I1" input="LUT6_2.I1" output="LUTX[0].I0 LUTX[1].I0 LUTX[0].I1 LUTX[1].I1 LUTX[0].I2 LUTX[1].I2 LUTX[0].I3 LUTX[1].I3 LUTX[0].I4 LUTX[1].I4"/>
-            <complete name="I2" input="LUT6_2.I2" output="LUTX[0].I0 LUTX[1].I0 LUTX[0].I1 LUTX[1].I1 LUTX[0].I2 LUTX[1].I2 LUTX[0].I3 LUTX[1].I3 LUTX[0].I4 LUTX[1].I4"/>
-            <complete name="I3" input="LUT6_2.I3" output="LUTX[0].I0 LUTX[1].I0 LUTX[0].I1 LUTX[1].I1 LUTX[0].I2 LUTX[1].I2 LUTX[0].I3 LUTX[1].I3 LUTX[0].I4 LUTX[1].I4"/>
-            <complete name="I4" input="LUT6_2.I4" output="LUTX[0].I0 LUTX[1].I0 LUTX[0].I1 LUTX[1].I1 LUTX[0].I2 LUTX[1].I2 LUTX[0].I3 LUTX[1].I3 LUTX[0].I4 LUTX[1].I4"/>
+            <direct name="I0" input="LUT6_2.I0" output="LUTX[0].I0 LUTX[1].I0"/>
+            <direct name="I1" input="LUT6_2.I1" output="LUTX[0].I1 LUTX[1].I1"/>
+            <direct name="I2" input="LUT6_2.I2" output="LUTX[0].I2 LUTX[1].I2"/>
+            <direct name="I3" input="LUT6_2.I3" output="LUTX[0].I3 LUTX[1].I3"/>
+            <direct name="I4" input="LUT6_2.I4" output="LUTX[0].I4 LUTX[1].I4"/>
             <direct name="O6" input="LUTX[0].O" output="LUT6_2.O6"/>
             <direct name="O5" input="LUTX[1].O" output="LUT6_2.O5"/>
           </interconnect>