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AlexandreSingerAlexandreSinger
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Merge pull request #2990 from AlexandreSinger/feature-ap-fixed-blocks
[AP] General Fixed/Unfixed Blocks Cleanup
2 parents 735448c + 1b89c8a commit 1e479b9

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16 files changed

+78
-53
lines changed

16 files changed

+78
-53
lines changed

‎vpr/src/analytical_place/analytical_solver.cpp

+19
Original file line numberDiff line numberDiff line change
@@ -446,6 +446,25 @@ void B2BSolver::solve(unsigned iteration, PartialPlacement& p_placement) {
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// Store an initial placement into the p_placement object as a starting point
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// for the B2B solver.
448448
if (iteration == 0) {
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// If there are no fixed blocks, running bound2bound will always yield
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// the trivial solution (all blocks on top of each other anywhere on the
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// device). Skip having to solve for this by just putting all the blocks
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// at the center of the device.
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// TODO: This can be further improved by using the average compatible
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// tile location for each AP block. The center is just an
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// approximation.
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if (num_fixed_blocks_ == 0) {
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for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) {
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APRowId row_id = APRowId(row_id_idx);
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APBlockId blk_id = row_id_to_blk_id_[row_id];
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p_placement.block_x_locs[blk_id] = device_grid_width_ / 2.0;
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p_placement.block_y_locs[blk_id] = device_grid_height_ / 2.0;
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}
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block_x_locs_solved = p_placement.block_x_locs;
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block_y_locs_solved = p_placement.block_y_locs;
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return;
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}
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// In the first iteration, we have no prior information.
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// Run the intial placer to get a first guess.
451470
switch (initial_placement_ty_) {

‎vpr/src/analytical_place/ap_netlist.h

+3-3
Original file line numberDiff line numberDiff line change
@@ -35,10 +35,10 @@
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*/
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struct APFixedBlockLoc {
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// Value that represents an unfixed dimension.
38-
static constexpr int UNFIXED_DIM = -1;
38+
static constexpr float UNFIXED_DIM = -1;
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// The dimensions to fix.
40-
int x = UNFIXED_DIM;
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int y = UNFIXED_DIM;
40+
float x = UNFIXED_DIM;
41+
float y = UNFIXED_DIM;
4242
int layer_num = UNFIXED_DIM;
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int sub_tile = UNFIXED_DIM;
4444
};

‎vpr/src/analytical_place/gen_ap_netlist_from_atoms.cpp

+7-2
Original file line numberDiff line numberDiff line change
@@ -89,8 +89,13 @@ APNetlist gen_ap_netlist_from_atoms(const AtomNetlist& atom_netlist,
8989
const vtr::Rect<int>& region_rect = region.get_rect();
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VTR_ASSERT(region_rect.xmin() == region_rect.xmax() && "AP: Expect each region to be a single point in x!");
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VTR_ASSERT(region_rect.ymin() == region_rect.ymax() && "AP: Expect each region to be a single point in y!");
92-
int blk_x_loc = region_rect.xmin();
93-
int blk_y_loc = region_rect.ymin();
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// Here we offset by 0.5 to put the fixed point in the center of the
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// tile (assuming the tile is 1x1).
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// TODO: Think about what to do when the user fixes blocks to large
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// tiles. However, this solution will at least keep the atoms
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// away from the edge of tiles.
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float blk_x_loc = region_rect.xmin() + 0.5f;
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float blk_y_loc = region_rect.ymin() + 0.5f;
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// Get the layer.
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VTR_ASSERT(region.get_layer_range().first == region.get_layer_range().second && "AP: Expect each region to be a single point in layer!");
96101
int blk_layer_num = region.get_layer_range().first;

‎vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt

+1
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ vpr_status;output.txt;vpr_status=(.*)
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crit_path_delay;vpr.out;Critical path: (.*) ns
66
post_gp_hpwl;vpr.out;\s*Placement HPWL: (.*)
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post_fl_hpwl;vpr.out;Initial placement BB estimate of wirelength: (.*)
8+
post_dp_hpwl;vpr.out;BB estimate of min-dist \(placement\) wire length: (.*)
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total_wirelength;vpr.out;\s*Total wirelength: (\d+)
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post_gp_overfilled_bins;vpr.out;\s*Number of overfilled bins: (\d+)
1011
post_gp_avg_overfill;vpr.out;\s*Average overfill magnitude: (.*)

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt

+4-4
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time
2-
k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 3.59 vpr 75.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77156 9 19 897 28 0 562 109 16 16 256 -1 mcnc_medium -1 -1 9742 6119 10249 1760 5821 2668 75.3 MiB 2.81 0.01 6.60912 5.26997 -81.789 -5.26997 nan 0.05 0.00179692 0.00145997 0.0947522 0.0791883 75.3 MiB 2.81 75.3 MiB 1.73 9723 17.3316 2505 4.46524 4006 19859 666446 110600 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.51321 nan -87.5291 -5.51321 0 0 0.34 -1 -1 75.3 MiB 0.25 0.210289 0.182458 75.3 MiB -1 0.05
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k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.99 vpr 76.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 52 256 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77936 256 245 954 501 0 582 553 22 22 484 -1 mcnc_large -1 -1 8094 7501 39126 389 7567 31170 76.1 MiB 1.14 0.02 5.73036 4.09857 -784.452 -4.09857 nan 0.12 0.0036209 0.00320967 0.0974498 0.0783511 76.1 MiB 1.14 76.1 MiB 0.58 10270 17.6460 2810 4.82818 2238 5018 286471 63337 2.15576e+07 2.80249e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.45761 nan -846.555 -4.45761 0 0 0.37 -1 -1 76.1 MiB 0.25 0.241683 0.211802 76.1 MiB -1 0.12
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k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 12.92 vpr 106.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 290 10 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108560 10 10 2659 20 0 1285 310 22 22 484 -1 mcnc_large -1 -1 35642 24564 56902 15498 35924 5480 106.0 MiB 10.38 0.02 9.2649 6.61089 -64.2928 -6.61089 nan 0.15 0.00607931 0.0048535 0.385282 0.31707 106.0 MiB 10.38 106.0 MiB 5.44 37798 29.4148 9576 7.45214 8278 52602 2224659 293057 2.15576e+07 1.56293e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.83554 nan -66.0686 -6.83554 0 0 1.10 -1 -1 106.0 MiB 0.85 0.754783 0.64805 106.0 MiB -1 0.15
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k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.71 vpr 76.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 41 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78472 41 35 1006 76 0 578 158 16 16 256 -1 mcnc_medium -1 -1 10490 6475 10406 884 4940 4582 76.6 MiB 3.58 0.01 6.29657 4.68967 -140.848 -4.68967 nan 0.09 0.00393615 0.00326892 0.130272 0.112932 76.6 MiB 3.58 76.6 MiB 2.21 10487 18.1436 2747 4.75259 4099 21208 684107 115230 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 18 28900 206586 -1 4.97595 nan -146.106 -4.97595 0 0 0.33 -1 -1 76.6 MiB 0.51 0.372342 0.333335 76.6 MiB -1 0.09
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k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.63 vpr 75.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 9 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77436 9 19 897 28 0 565 111 16 16 256 -1 mcnc_medium -1 -1 6985 6104 4899 468 3178 1253 75.6 MiB 3.56 0.01 5.45737 4.88762 -81.315 -4.88762 nan 0.09 0.00332256 0.00272635 0.0920151 0.0793873 75.6 MiB 3.56 75.6 MiB 2.42 9609 17.0372 2580 4.57447 4604 23759 790399 131608 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.07748 nan -84.5559 -5.07748 0 0 0.33 -1 -1 75.6 MiB 0.47 0.288973 0.25613 75.6 MiB -1 0.09
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k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.81 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 256 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78036 256 245 954 501 0 584 559 22 22 484 -1 mcnc_large -1 -1 7428 7369 18967 157 2360 16450 76.2 MiB 0.93 0.02 4.87092 4.07054 -789.645 -4.07054 nan 0.13 0.00365979 0.00331889 0.047619 0.043593 76.2 MiB 0.93 76.2 MiB 0.59 10168 17.4110 2803 4.79966 2303 5353 301769 65803 2.15576e+07 3.12585e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.58117 nan -866.844 -4.58117 0 0 0.37 -1 -1 76.2 MiB 0.25 0.188446 0.174077 76.2 MiB -1 0.13
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k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 11.93 vpr 105.82 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 289 10 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108360 10 10 2659 20 0 1312 309 22 22 484 -1 mcnc_large -1 -1 30891 24822 37893 7171 26674 4048 105.8 MiB 9.23 0.02 9.04847 6.65923 -63.8387 -6.65923 nan 0.16 0.00660438 0.00519941 0.309592 0.257376 105.8 MiB 9.23 105.8 MiB 4.50 37153 28.3178 9567 7.29192 8219 52828 2194741 285748 2.15576e+07 1.55754e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.35737 nan -66.9799 -7.35737 0 0 1.18 -1 -1 105.8 MiB 0.93 0.709043 0.615207 105.8 MiB -1 0.16
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k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.73 vpr 76.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 41 -1 -1 success v8.0.0-12490-ge99a5ee8c release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-21T16:53:01 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78628 41 35 1006 76 0 573 160 16 16 256 -1 mcnc_medium -1 -1 7311 6476 7538 345 3855 3338 76.8 MiB 3.59 0.01 5.73065 5.08486 -143.975 -5.08486 nan 0.09 0.0040653 0.00347069 0.103188 0.0899686 76.8 MiB 3.59 76.8 MiB 2.31 10018 17.4834 2728 4.76091 4171 21468 688416 120931 1.05632e+07 4.5271e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29306 nan -148.307 -5.29306 0 0 0.37 -1 -1 76.8 MiB 0.47 0.321818 0.287107 76.8 MiB -1 0.09

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