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doc/src/tutorials/timing_analysis/index.rst
@@ -11,7 +11,13 @@ not support all timing constraints and does not provide a TCL interface to allow
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you to directly interrogate the timing graph. VPR also has limited support for
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multi-clock timing analysis, which tools like OpenSTA have better support for.
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-A user flow which would use this would perform the following steps:
+.. _fig_timing_analysis_design_cycle:
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+
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+.. figure:: timing_analysis_design_cycle.png
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+ Timing analysis design cycle flow diagram.
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+A user design cycle which would use this would perform the following steps:
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1. Run VPR with the timing commands it can support.
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2. Perform timing analysis on the resulting netlist using OpenSTA with
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more complex timing commands.
doc/src/tutorials/timing_analysis/timing_analysis_design_cycle.png
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