From 1e81c5af7c76452758b2bbb07db2a8af9317fd20 Mon Sep 17 00:00:00 2001
From: Marno van der Maas <mvdmaas+git@lowrisc.org>
Date: Fri, 11 Apr 2025 11:32:35 +0100
Subject: [PATCH 1/2] Update lowrisc_ibex to lowRISC/ibex@594ea976
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Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
594ea976c9dad793f87edf91ec1c4c1df447e6dc

* [dv] Plan test for DM accesses in debug mode (Andreas Kurth)
* fix: Illegal instruction display message (Hao)
* Verification should be done with ibex_cosim branch (Marno van der
  Maas)
* [ci] switch CI runner from Ubuntu 20.04 to 22.04 (Gary Guo)
* [ci] update verible version to match OT (Gary Guo)
* [ci] remove Azure Pipelines magic commands (Gary Guo)
* [cosim] Update comment on `set_mip` in Cosim interface (Greg
  Chadwick)
* [rtl] Remove low utility assertions (Greg Chadwick)
* [rtl] Flush pipe on all CSR modifications (Greg Chadwick)
* [rtl] Read csr_addr direct from instruction (Greg Chadwick)
* [ibex_core] Fix assertion when SecureIbex is false (Rupert
  Swarbrick)
* [ibex_register_file_fpga] Drop two confusing comments (Rupert
  Swarbrick)
* Fix typo in comment in ibex_id_stage.sv (Katharina)
* [ibex_tracer] Use static variables in always/final blocks (Robert
  Schilling)
* [rtl] Drive oh_raddr_*_err if RdataMuxCheck=0 (Rupert Swarbrick)
* Update core_ibex_pmp_fcov_if.sv (Priyanshu Mishra)
* [rtl,pmp] Allow all accesses to Debug Module in debug mode (Andreas
  Kurth)
* [controller] Add assertion on pipeline flush when entering debug
  mode (Andreas Kurth)
* ibex_pcounts: resolve uninitialize warning (Marno van der Maas)
* [rtl] Fix non-DSP reset in ibex_counter (Pascal Nasahl)
* Revert "[rtl] Fix counter reset value on FPGA" (Pascal Nasahl)
* [rtl] Fix counter reset value on FPGA (Pascal Nasahl)
* [ci] remove Azure Pipelines (Gary Guo)
* [rtl] Fix zero value in FPGA RF (Pascal Nasahl)
* Block diagram: make feature text readable (Marno van der Maas)
* Block diagram: fixes and improved looks (Marno van der Maas)
* [dv] Cleanup some code in the compile_tb.py module (Harry Callahan)
* [dv] Tweak ISS linker arg construction for Xcelium (Harry Callahan)
* [pmp] Use top-level straps for PMP reset values (Robert Schilling)
* Update more documentation links (Elliot Baptist)
* Update verification_stages.rst OT links (Elliot Baptist)
* [rtl] Fix wrong address in latch RF (Pascal Nasahl)
* [rtl] fix a typo. (lingscale)
* [doc] fix a typo. (lingscale)
* Fix icache regression failure on VCS (Gary Guo)
* [rtl] Remove ECC related data_rdata_i -> instr_X_o feedthroughs
  (Greg Chadwick)
* Add SECURITY.md (Greg Chadwick)
* [dv] Increase iterations and instructions in riscv_rf_intg_test
  (Greg Chadwick)
* [dv] Alter riscv_rf_intg_test to cover more scenarios (Greg
  Chadwick)
* [rtl] Fix logic for generating ECC related alerts (Greg Chadwick)
* [dv] Add spurious responses to memory agent (Greg Chadwick)
* [dv] Add riscv_ram_intg_test This test injects a fault into
  different MuBi encoded signals within the prim_ram_1p_scr and
  prim_ram_1p_adv and checks whether a fatal alert is triggered.
  (Pascal Nasahl)
* [cosim] Clang lint fix (Greg Chadwick)
* [ci] Bump co-sim version (Greg Chadwick)
* [dv] Output warning message on problematic MIP changes (Greg
  Chadwick)
* [cosim] Correctly deal with checking top of range memory accesses
  (Greg Chadwick)
* [dv] Update testbench to use new 'pre_val' MIP (Greg Chadwick)
* [dv] Fix model mismatches in cases where an access crosses PMP
  regions (Greg Chadwick)
* [dv] Fix exception_stall_instr_cross illegal bins (Greg Chadwick)
* [dv] Add riscv_rf_ctrl_intg_test (Greg Chadwick)
* [ci] update private CI (Gary Guo)
* [dv] Add cover points for memory interface behaviour (Greg Chadwick)
* [dv] Fix race condition in ibex_mem_intf_agent (Greg Chadwick)
* [doc] Fix C++ style guide link in README (James Wainwright)
* [dv] Remove phase argument from collect_trans (Pascal Nasahl)
* [dv] Add mubi and prim_count pkg to DV environment (Pascal Nasahl)
* Update lowrisc_ip to lowRISC/opentitan@d268f271f4 (Pascal Nasahl)
* [rtl] Add error port to iCache (Pascal Nasahl)
* [rtl] Update RAM ports inside ibex_top (Pascal Nasahl)
* [rtl] Guard against false memory responses for secure configurations
  (Greg Chadwick)
* Expand the coverage plan after a review (Marno van der Maas)
* [rtl] Expose ICacheScrNumPrinceRoundsHalf parameter (Pirmin Vogel)
* Add missing copyright headers (James Wainwright)
* [simple_system] Bump C++ version in core files (Rupert Swarbrick)
* Keep to patch numbering convention (Marno van der Maas)
* [ci] Add missing sudo in CI (Gary Guo)
* [dv] Output VCS simulation log to file (Greg Chadwick)
* [dv] Add flag needed to allow force under VCS (Greg Chadwick)
* [dv] Fix use of plusargs (Greg Chadwick)
* [fcov] Fix illegal bins related to stall types (Greg Chadwick)
* [dv] Handle missing paths when producing regression log (Greg
  Chadwick)
* [dv] Only run SecureIbex relevant tests for SecureIbex configs (Greg
  Chadwick)
* [dv] Fix regression for non PMP configs (Greg Chadwick)
* [dv] Fix path for vcs.tcl for wave dumping (Greg Chadwick)
* [dv, cov] Log coverage merge stdout for VCS (Greg Chadwick)
* [cosim] Fix SIGSEGV in ~SpikeCosim (Greg Chadwick)
* [dv] Skip SVG generation in DV flow if svg module is missing (Greg
  Chadwick)
* [dv] Flow modifications for CentOS 7 for testbench compile (Greg
  Chadwick)
* Require Pydantic 2 or above (Marno van der Maas)
* [rtl] Update use of prim_count following port changes (Greg
  Chadwick)
* Update lowrisc_ip to lowRISC/opentitan@e0c4026501 (Greg Chadwick)
* [tracer] Fix reporting of load/store data (Adrian Lees)
* [bus] Return error if decode fails (Adrian Lees)
* Update old `cpuctrl` CSR name in `cs_registers.rst` (Luís Marques)
* Update benchmarks README to better explain how to try different
  configs (Greg Chadwick)
* Enable the icache in coremark (Greg Chadwick)
* Add icache_enable function to simple_system_common.h (Greg Chadwick)
* Fix stale merge commit issue in private CI (Gary Guo)
* [doc] Require sphinx version >= 7.0 (Greg Chadwick)
* [rtl] Harden lockstep enable against FI (Pascal Nasahl)
* Update verilator version (Pascal Nasahl)
* [icache] Disable S&P diffusion layer in memory scrambling (Michael
  Schaffner)
* Update lowrisc_ip to lowRISC/opentitan@4cf2479b8e (Michael
  Schaffner)
* [dv] Fix paths in `merge_cov.py` (Sᴜᴘᴇʀ Lᴇᴇ)
* Add NOTICE file (Michael Munday)
* Tweak questa timescale argument (Harry Callahan)
* Fixup the questa build/sim command templates in rtl_simulation.yaml
  (Harry Callahan)

Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
---
 vendor/lowrisc_ibex.lock.hjson                |   2 +-
 vendor/lowrisc_ibex/.svlint.toml              |   2 +-
 vendor/lowrisc_ibex/NOTICE                    |  10 +
 vendor/lowrisc_ibex/README.md                 |   2 +-
 vendor/lowrisc_ibex/SECURITY.md               |   8 +
 vendor/lowrisc_ibex/azure-pipelines.yml       | 129 ----
 vendor/lowrisc_ibex/ci/azp-private.yml        |  31 -
 vendor/lowrisc_ibex/ci/ibex-rtl-ci-steps.yml  |  90 ---
 vendor/lowrisc_ibex/ci/install-build-deps.sh  |  16 +-
 vendor/lowrisc_ibex/ci/run-cosim-test.sh      |   5 +-
 vendor/lowrisc_ibex/ci/vars.env               |   6 +-
 vendor/lowrisc_ibex/ci/vars.yml               |  16 -
 vendor/lowrisc_ibex/ci/vars_to_logging_cmd.py |  43 --
 .../doc/01_overview/verification_overview.rst |   2 +-
 .../lowrisc_ibex/doc/02_user/integration.rst  |   6 +
 .../doc/03_reference/coverage_plan.rst        |  39 +-
 .../doc/03_reference/cs_registers.rst         |   2 +-
 .../lowrisc_ibex/doc/03_reference/debug.rst   |   6 +-
 .../doc/03_reference/images/blockdiagram.svg  | 728 ++++++++----------
 .../instruction_decode_execute.rst            |   2 +-
 vendor/lowrisc_ibex/doc/03_reference/pmp.rst  |  10 +-
 .../doc/03_reference/verification.rst         |   8 +-
 .../doc/03_reference/verification_stages.rst  |   8 +-
 .../doc/04_developer/concierge.rst            |   2 -
 vendor/lowrisc_ibex/doc/requirements.txt      |   2 +-
 vendor/lowrisc_ibex/dv/cosim/cosim.h          |  16 +-
 vendor/lowrisc_ibex/dv/cosim/cosim_dpi.cc     |  31 +-
 vendor/lowrisc_ibex/dv/cosim/cosim_dpi.h      |   9 +-
 vendor/lowrisc_ibex/dv/cosim/cosim_dpi.svh    |   5 +-
 vendor/lowrisc_ibex/dv/cosim/spike_cosim.cc   | 134 +++-
 vendor/lowrisc_ibex/dv/cosim/spike_cosim.h    |  14 +-
 .../dv/cs_registers/lint/verilator_waiver.vlt |   2 +-
 .../ibex_riscv_compliance.core                |   2 +-
 .../lint/verilator_waiver.vlt                 |   2 +-
 .../rtl/ibex_riscv_compliance.sv              |   2 +
 vendor/lowrisc_ibex/dv/uvm/core_ibex/Makefile |   6 +
 .../ibex_cosim_agent/ibex_cosim_scoreboard.sv |   7 +-
 .../ibex_cosim_agent/ibex_rvfi_monitor.sv     |   3 +-
 .../ibex_cosim_agent/ibex_rvfi_seq_item.sv    |   6 +-
 .../ibex_mem_intf_agent/ibex_mem_intf.sv      |   8 +
 .../ibex_mem_intf_monitor.sv                  |  51 +-
 .../ibex_mem_intf_request_driver.sv           |   2 +-
 .../ibex_mem_intf_response_agent.sv           |   3 +
 .../ibex_mem_intf_response_agent_cfg.sv       |  20 +-
 .../ibex_mem_intf_response_driver.sv          |  32 +-
 .../ibex_mem_intf_response_seq_lib.sv         |  53 +-
 .../ibex_mem_intf_response_sequencer.sv       |   9 +
 .../ibex_mem_intf_seq_item.sv                 |  26 +-
 .../core_ibex/env/core_ibex_dut_probe_if.sv   |   3 +
 .../dv/uvm/core_ibex/env/core_ibex_env_cfg.sv |   8 +
 .../dv/uvm/core_ibex/env/core_ibex_rvfi_if.sv |   6 +-
 .../uvm/core_ibex/fcov/core_ibex_fcov_if.sv   |  98 ++-
 .../core_ibex/fcov/core_ibex_pmp_fcov_if.sv   |   2 +-
 .../lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f   |   4 +-
 .../ibex_asm_program_gen.sv                   |   7 +
 .../ibex_directed_instr_lib.sv                |   6 +-
 .../riscv_dv_extension/testlist.yaml          |  58 +-
 .../uvm/core_ibex/scripts/collect_results.py  |  22 +-
 .../dv/uvm/core_ibex/scripts/compile_tb.py    | 107 ++-
 .../dv/uvm/core_ibex/scripts/merge_cov.py     |  18 +-
 .../uvm/core_ibex/scripts/report_lib/util.py  |  10 +-
 .../dv/uvm/core_ibex/scripts/run_rtl.py       |   1 +
 .../dv/uvm/core_ibex/tb/core_ibex_tb_top.sv   |  67 +-
 .../core_ibex/tests/core_ibex_base_test.sv    |  11 +
 .../uvm/core_ibex/tests/core_ibex_test_lib.sv | 201 ++++-
 .../dv/uvm/core_ibex/tests/core_ibex_vseq.sv  |  20 +
 .../dv/uvm/core_ibex/yaml/rtl_simulation.yaml |  20 +-
 .../dv/uvm/icache/doc/ibex_icache_dv_plan.md  |   6 +-
 .../uvm/icache/dv/fcov/ibex_icache_fcov_if.sv |  12 +-
 .../ibex_icache_core_monitor.sv               |   2 +-
 .../ibex_icache_mem_monitor.sv                |   2 +-
 vendor/lowrisc_ibex/dv/uvm/icache/dv/tb/tb.sv |  99 +--
 .../dv/verilator/pcount/cpp/ibex_pcounts.cc   |   3 +-
 .../ibex_simple_system_cosim.core             |   2 +-
 .../ibex_simple_system_cosim_checker.sv       |  14 +-
 .../examples/simple_system/README.md          |   2 +-
 .../simple_system/ibex_simple_system.core     |   2 +-
 .../simple_system/lint/verilator_waiver.vlt   |   2 +-
 .../simple_system/rtl/ibex_simple_system.sv   |   2 +
 .../examples/sw/benchmarks/README.md          |   6 +-
 .../sw/benchmarks/coremark/ibex/core_portme.c |   1 +
 .../common/simple_system_common.h             |  17 +
 vendor/lowrisc_ibex/ibex_core.core            |   2 +-
 vendor/lowrisc_ibex/ibex_top.core             |   1 +
 vendor/lowrisc_ibex/lint/verilator_waiver.vlt |   2 +-
 vendor/lowrisc_ibex/python-requirements.txt   |   2 +-
 vendor/lowrisc_ibex/rtl/ibex_controller.sv    |  85 +-
 vendor/lowrisc_ibex/rtl/ibex_core.f           |   4 +
 vendor/lowrisc_ibex/rtl/ibex_core.sv          | 178 +++--
 vendor/lowrisc_ibex/rtl/ibex_counter.sv       |  46 +-
 vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv  |  46 +-
 vendor/lowrisc_ibex/rtl/ibex_decoder.sv       |   8 +-
 vendor/lowrisc_ibex/rtl/ibex_ex_block.sv      |  18 +
 vendor/lowrisc_ibex/rtl/ibex_id_stage.sv      |  68 +-
 vendor/lowrisc_ibex/rtl/ibex_lockstep.sv      | 149 ++--
 vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv  |  23 +
 vendor/lowrisc_ibex/rtl/ibex_multdiv_slow.sv  |  12 +
 vendor/lowrisc_ibex/rtl/ibex_pkg.sv           |  53 +-
 vendor/lowrisc_ibex/rtl/ibex_pmp.sv           |  17 +-
 .../rtl/ibex_pmp_reset_default.svh            |  53 --
 .../rtl/ibex_register_file_fpga.sv            |  12 +-
 .../rtl/ibex_register_file_latch.sv           |   2 +-
 vendor/lowrisc_ibex/rtl/ibex_top.sv           | 176 +++--
 vendor/lowrisc_ibex/rtl/ibex_top_tracing.sv   |  16 +-
 vendor/lowrisc_ibex/rtl/ibex_tracer.sv        |  11 +-
 vendor/lowrisc_ibex/rtl/ibex_wb_stage.sv      |   3 +-
 vendor/lowrisc_ibex/shared/rtl/bus.sv         |  17 +-
 vendor/lowrisc_ibex/tool_requirements.py      |   2 +-
 vendor/lowrisc_ibex/util/Makefile             |   4 +
 .../lowrisc_ibex/vendor/lowrisc_ip.lock.hjson |   4 +-
 .../lowrisc_ip/dv/sv/common_ifs/clk_if.sv     |   2 +-
 .../lowrisc_ip/dv/sv/common_ifs/clk_rst_if.sv |   4 +-
 .../dv/sv/common_ifs/common_ifs.core          |   2 +-
 .../dv/sv/common_ifs/common_ifs_pkg.sv        |   2 +-
 .../entropy_subsys_fifo_exception_if.core     |   2 +-
 .../entropy_subsys_fifo_exception_if.sv       |   2 +-
 .../entropy_subsys_fifo_exception_pkg.sv      |   2 +-
 .../lowrisc_ip/dv/sv/common_ifs/pins_if.sv    |   2 +-
 .../lowrisc_ip/dv/sv/common_ifs/pins_ifs.core |   2 +-
 .../dv/sv/common_ifs/rst_shadowed_if.core     |   2 +-
 .../dv/sv/common_ifs/rst_shadowed_if.sv       |   2 +-
 .../lowrisc_ip/dv/sv/csr_utils/csr_seq_lib.sv |  26 +-
 .../lowrisc_ip/dv/sv/csr_utils/csr_utils.core |   2 +-
 .../dv/sv/csr_utils/csr_utils_pkg.sv          |  66 +-
 .../dv/sv/dv_base_reg/csr_excl_item.sv        |   2 +-
 .../dv_base_reg/dv_base_lockable_field_cov.sv |   2 +-
 .../dv/sv/dv_base_reg/dv_base_mem.sv          |   2 +-
 .../dv/sv/dv_base_reg/dv_base_mubi_cov.sv     |  33 +-
 .../dv/sv/dv_base_reg/dv_base_reg.core        |   2 +-
 .../dv/sv/dv_base_reg/dv_base_reg.sv          |  28 +-
 .../dv/sv/dv_base_reg/dv_base_reg_block.sv    |   2 +-
 .../dv/sv/dv_base_reg/dv_base_reg_field.sv    |  84 +-
 .../dv/sv/dv_base_reg/dv_base_reg_map.sv      |   2 +-
 .../dv/sv/dv_base_reg/dv_base_reg_pkg.sv      |   2 +-
 .../dv_base_reg/dv_base_shadowed_field_cov.sv |   2 +-
 .../lowrisc_ip/dv/sv/dv_lib/dv_base_agent.sv  |   3 +-
 .../dv/sv/dv_lib/dv_base_agent_cfg.sv         |   2 +-
 .../dv/sv/dv_lib/dv_base_agent_cov.sv         |   2 +-
 .../lowrisc_ip/dv/sv/dv_lib/dv_base_driver.sv |   3 +-
 .../lowrisc_ip/dv/sv/dv_lib/dv_base_env.sv    |   2 +-
 .../dv/sv/dv_lib/dv_base_env_cfg.sv           |  17 +-
 .../dv/sv/dv_lib/dv_base_env_cov.sv           |   2 +-
 .../dv/sv/dv_lib/dv_base_monitor.sv           |   6 +-
 .../dv/sv/dv_lib/dv_base_scoreboard.sv        |   3 +-
 .../lowrisc_ip/dv/sv/dv_lib/dv_base_seq.sv    |   2 +-
 .../dv/sv/dv_lib/dv_base_sequencer.sv         |   2 +-
 .../lowrisc_ip/dv/sv/dv_lib/dv_base_test.sv   |   2 +-
 .../dv/sv/dv_lib/dv_base_virtual_sequencer.sv |   2 +-
 .../lowrisc_ip/dv/sv/dv_lib/dv_base_vseq.sv   |   2 +-
 .../lowrisc_ip/dv/sv/dv_lib/dv_lib.core       |   2 +-
 .../lowrisc_ip/dv/sv/dv_lib/dv_lib_pkg.sv     |   2 +-
 .../dv/sv/dv_utils/dv_fcov_macros.core        |   2 +-
 .../dv/sv/dv_utils/dv_fcov_macros.svh         |   2 +-
 .../lowrisc_ip/dv/sv/dv_utils/dv_macros.core  |   2 +-
 .../lowrisc_ip/dv/sv/dv_utils/dv_macros.svh   |  19 +-
 .../dv/sv/dv_utils/dv_report_catcher.sv       |   2 +-
 .../dv/sv/dv_utils/dv_report_server.sv        |   2 +-
 .../dv/sv/dv_utils/dv_test_status.core        |   2 +-
 .../dv/sv/dv_utils/dv_test_status_pkg.sv      |   2 +-
 .../lowrisc_ip/dv/sv/dv_utils/dv_utils.core   |   2 +-
 .../lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv |   3 +-
 .../lowrisc_ip/dv/sv/dv_utils/dv_vif_wrap.sv  |   2 +-
 .../dv/sv/mem_bkdr_util/mem_bkdr_util.core    |   4 +-
 .../dv/sv/mem_bkdr_util/mem_bkdr_util.sv      |   2 +-
 .../sv/mem_bkdr_util/mem_bkdr_util__flash.sv  |   2 +-
 .../dv/sv/mem_bkdr_util/mem_bkdr_util__otp.sv |  45 +-
 .../dv/sv/mem_bkdr_util/mem_bkdr_util__rom.sv |   3 +-
 .../sv/mem_bkdr_util/mem_bkdr_util__sram.sv   |  39 +-
 .../dv/sv/mem_bkdr_util/mem_bkdr_util_pkg.sv  |   2 +-
 .../dv/sv/mem_bkdr_util/otp_scrambler_pkg.sv  |   2 +-
 .../dv/sv/mem_bkdr_util/sram_scrambler_pkg.sv | 138 ++--
 .../lowrisc_ip/dv/sv/mem_model/mem_model.core |   2 +-
 .../lowrisc_ip/dv/sv/mem_model/mem_model.sv   |   4 +-
 .../dv/sv/mem_model/mem_model_pkg.sv          |   2 +-
 .../sv/push_pull_agent/push_pull_agent.core   |   2 +-
 .../dv/sv/push_pull_agent/push_pull_agent.sv  |   2 +-
 .../sv/push_pull_agent/push_pull_agent_cfg.sv |   4 +-
 .../sv/push_pull_agent/push_pull_agent_cov.sv |   2 +-
 .../sv/push_pull_agent/push_pull_agent_pkg.sv |   2 +-
 .../push_pull_agent/push_pull_driver_lib.sv   |   2 +-
 .../dv/sv/push_pull_agent/push_pull_if.sv     |   2 +-
 .../dv/sv/push_pull_agent/push_pull_item.sv   |   2 +-
 .../sv/push_pull_agent/push_pull_monitor.sv   |   7 +-
 .../sv/push_pull_agent/push_pull_sequencer.sv |   2 +-
 .../seq_lib/push_pull_base_seq.sv             |   2 +-
 .../seq_lib/push_pull_device_seq.sv           |   2 +-
 .../seq_lib/push_pull_host_seq.sv             |   2 +-
 .../seq_lib/push_pull_indefinite_host_seq.sv  |   2 +-
 .../seq_lib/push_pull_seq_list.sv             |   2 +-
 .../lowrisc_ip/dv/sv/str_utils/str_utils.core |   2 +-
 .../dv/sv/str_utils/str_utils_pkg.sv          |   2 +-
 .../vendor/lowrisc_ip/dv/tools/common.tcl     |   2 +-
 .../lowrisc_ip/dv/tools/dvsim/bazel.hjson     |   2 +-
 .../dv/tools/dvsim/common_modes.hjson         |  16 +-
 .../dv/tools/dvsim/common_sim_cfg.hjson       |   2 +-
 .../lowrisc_ip/dv/tools/dvsim/dsim.hjson      |   2 +-
 .../lowrisc_ip/dv/tools/dvsim/fusesoc.hjson   |   2 +-
 .../lowrisc_ip/dv/tools/dvsim/questa.hjson    |   2 +-
 .../lowrisc_ip/dv/tools/dvsim/riviera.hjson   |   2 +-
 .../vendor/lowrisc_ip/dv/tools/dvsim/sim.mk   |  40 +-
 .../dvsim/testplans/alert_test_testplan.hjson |   2 +-
 .../tools/dvsim/testplans/csr_testplan.hjson  |   2 +-
 .../dvsim/testplans/fpv_csr_testplan.hjson    |   2 +-
 .../dvsim/testplans/intr_test_testplan.hjson  |   2 +-
 .../tools/dvsim/testplans/mem_testplan.hjson  |   2 +-
 .../passthru_mem_intg_testplan.hjson          |   2 +-
 .../testplans/sec_cm_count_testplan.hjson     |   2 +-
 .../sec_cm_double_lfsr_testplan.hjson         |   2 +-
 .../dvsim/testplans/sec_cm_fsm_testplan.hjson |   2 +-
 .../testplans/sec_cm_one_hot_testplan.hjson   |   2 +-
 .../shadow_reg_errors_testplan.hjson          |   2 +-
 .../stress_all_with_reset_testplan.hjson      |   2 +-
 .../tl_device_access_types_testplan.hjson     |   2 +-
 ...device_access_types_wo_intg_testplan.hjson |   4 +-
 .../dv/tools/dvsim/tests/alert_test.hjson     |   2 +-
 .../dv/tools/dvsim/tests/csr_tests.hjson      |   2 +-
 .../dv/tools/dvsim/tests/intr_test.hjson      |   2 +-
 .../dv/tools/dvsim/tests/mem_tests.hjson      |   2 +-
 .../dvsim/tests/passthru_mem_intg_tests.hjson |   2 +-
 .../dv/tools/dvsim/tests/sec_cm_tests.hjson   |   2 +-
 .../dvsim/tests/shadow_reg_errors_tests.hjson |   2 +-
 .../tools/dvsim/tests/stress_all_test.hjson   |   4 +-
 .../dv/tools/dvsim/tests/stress_tests.hjson   |   4 +-
 .../tools/dvsim/tests/tl_access_tests.hjson   |   2 +-
 .../lowrisc_ip/dv/tools/dvsim/vcs.hjson       |  16 +-
 .../lowrisc_ip/dv/tools/dvsim/verilator.hjson |   6 +-
 .../lowrisc_ip/dv/tools/dvsim/xcelium.hjson   |   6 +-
 .../vendor/lowrisc_ip/dv/tools/questa/sim.tcl |   2 +-
 .../lowrisc_ip/dv/tools/ralgen/ralgen.core    |   2 +-
 .../lowrisc_ip/dv/tools/ralgen/ralgen.py      |   2 +-
 .../dv/tools/riviera/riviera_run.do           |   2 +-
 .../vendor/lowrisc_ip/dv/tools/sim.tcl        |   2 +-
 .../dv/tools/vcs/common_cov_excl.cfg          |   2 +-
 .../vendor/lowrisc_ip/dv/tools/vcs/cover.cfg  |   2 +-
 .../lowrisc_ip/dv/tools/vcs/cover_reg_top.cfg |   2 +-
 .../lowrisc_ip/dv/tools/vcs/fsm_reset_cov.cfg |   2 +-
 .../vendor/lowrisc_ip/dv/tools/vcs/unr.cfg    |   2 +-
 .../vendor/lowrisc_ip/dv/tools/vcs/xprop.cfg  |   2 +-
 .../vendor/lowrisc_ip/dv/tools/waves.tcl      |   2 +-
 .../lowrisc_ip/dv/tools/xcelium/common.ccf    |   2 +-
 .../dv/tools/xcelium/common_cov_excl.tcl      |   2 +-
 .../lowrisc_ip/dv/tools/xcelium/cov_merge.tcl |   2 +-
 .../dv/tools/xcelium/cov_report.tcl           |   6 +-
 .../lowrisc_ip/dv/tools/xcelium/cover.ccf     |   2 +-
 .../dv/tools/xcelium/cover_reg_top.ccf        |   2 +-
 .../tools/xcelium/cover_reg_top_toggle_excl   |   2 +-
 .../lowrisc_ip/dv/tools/xcelium/unr.cfg       |   6 +-
 .../dv/verilator/cpp/dpi_memutil.cc           |   2 +-
 .../lowrisc_ip/dv/verilator/cpp/dpi_memutil.h |   2 +-
 .../dv/verilator/cpp/ecc32_mem_area.cc        |   2 +-
 .../dv/verilator/cpp/ecc32_mem_area.h         |   2 +-
 .../lowrisc_ip/dv/verilator/cpp/mem_area.cc   |   2 +-
 .../lowrisc_ip/dv/verilator/cpp/mem_area.h    |   2 +-
 .../lowrisc_ip/dv/verilator/cpp/ranged_map.h  |   2 +-
 .../verilator/cpp/scrambled_ecc32_mem_area.cc |  12 +-
 .../verilator/cpp/scrambled_ecc32_mem_area.h  |   2 +-
 .../lowrisc_ip/dv/verilator/cpp/sv_scoped.cc  |   2 +-
 .../lowrisc_ip/dv/verilator/cpp/sv_scoped.h   |   2 +-
 .../dv/verilator/cpp/verilator_memutil.cc     |   2 +-
 .../dv/verilator/cpp/verilator_memutil.h      |   2 +-
 .../lowrisc_ip/dv/verilator/memutil_dpi.core  |   2 +-
 .../dv/verilator/memutil_dpi_scrambled.core   |   2 +-
 .../memutil_dpi_scrambled_opts.hjson          |   2 +-
 .../dv/verilator/memutil_verilator.core       |   2 +-
 .../cpp/sim_ctrl_extension.h                  |   2 +-
 .../cpp/verilated_toplevel.cc                 |   2 +-
 .../cpp/verilated_toplevel.h                  |   2 +-
 .../cpp/verilator_sim_ctrl.cc                 |   2 +-
 .../cpp/verilator_sim_ctrl.h                  |   2 +-
 .../simutil_verilator/simutil_verilator.core  |   2 +-
 .../vendor/lowrisc_ip/lint/common.core        |   2 +-
 .../vendor/lowrisc_ip/lint/comportable.core   |   4 +-
 .../tools/ascentlint/ascentlint-config.tcl    |   5 +-
 .../lint/tools/ascentlint/common.waiver       |   4 +-
 .../lint/tools/ascentlint/comportable.waiver  |   2 +-
 .../lint/tools/dvsim/ascentlint.hjson         |   2 +-
 .../lint/tools/dvsim/common_lint_cfg.hjson    |   5 +-
 .../lowrisc_ip/lint/tools/dvsim/lint.mk       |   2 +-
 .../lint/tools/dvsim/veriblelint.hjson        |   2 +-
 .../lint/tools/dvsim/verilator.hjson          |   2 +-
 .../lowrisc-styleguide.rules.verible_lint     |   2 +-
 .../lint/tools/verilator/common.vlt           |   2 +-
 .../lint/tools/verilator/comportable.vlt      |   3 +-
 .../vendor/lowrisc_ip/util/dvsim/BUILD        |   8 +-
 .../vendor/lowrisc_ip/util/dvsim/CdcCfg.py    |   2 +-
 .../lowrisc_ip/util/dvsim/CfgFactory.py       |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/CfgJson.py   |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/Deploy.py    |   4 +-
 .../vendor/lowrisc_ip/util/dvsim/FlowCfg.py   |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/FormalCfg.py |  63 +-
 .../vendor/lowrisc_ip/util/dvsim/JobTime.py   |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/Launcher.py  |   2 +-
 .../lowrisc_ip/util/dvsim/LauncherFactory.py  |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/LintCfg.py   |   2 +-
 .../lowrisc_ip/util/dvsim/LintParser.py       |  28 +-
 .../lowrisc_ip/util/dvsim/LocalLauncher.py    |   5 +-
 .../lowrisc_ip/util/dvsim/LsfLauncher.py      |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/Makefile     |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/Modes.py     | 636 ---------------
 .../vendor/lowrisc_ip/util/dvsim/MsgBucket.py |   2 +-
 .../lowrisc_ip/util/dvsim/MsgBuckets.py       |   2 +-
 .../lowrisc_ip/util/dvsim/OneShotCfg.py       |  10 +-
 .../vendor/lowrisc_ip/util/dvsim/RdcCfg.py    |   2 +-
 .../lowrisc_ip/util/dvsim/Regression.py       | 182 +++++
 .../vendor/lowrisc_ip/util/dvsim/SGE.py       |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/Scheduler.py |   2 +-
 .../lowrisc_ip/util/dvsim/SgeLauncher.py      |   5 +-
 .../vendor/lowrisc_ip/util/dvsim/SimCfg.py    |  54 +-
 .../lowrisc_ip/util/dvsim/SimResults.py       |   2 +-
 .../lowrisc_ip/util/dvsim/StatusPrinter.py    |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/SynCfg.py    |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/Test.py      | 138 ++++
 .../vendor/lowrisc_ip/util/dvsim/Testplan.py  |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/Timer.py     |   2 +-
 .../util/dvsim/ascentlint-report-parser.py    |   3 +-
 .../vendor/lowrisc_ip/util/dvsim/dvsim.py     |   2 +-
 .../testplanner/common_testplan.hjson         |   2 +-
 .../testplanner/foo_sim_results.hjson         |   2 +-
 .../examples/testplanner/foo_testplan.hjson   |   2 +-
 .../util/dvsim/meridianrdc-report-parser.py   |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/modes.py     | 287 +++++++
 .../vendor/lowrisc_ip/util/dvsim/qsubopts.py  |   2 +-
 .../lowrisc_ip/util/dvsim/results_server.py   |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/sim_utils.py |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/style.css    |   2 +-
 .../lowrisc_ip/util/dvsim/testplanner.py      |   2 +-
 .../vendor/lowrisc_ip/util/dvsim/utils.py     |   2 +-
 .../lowrisc_ip/util/dvsim/utils_test.py       |   2 +-
 .../util/dvsim/veriblelint-report-parser.py   |   2 +-
 .../util/dvsim/verilator-report-parser.py     |   2 +-
 .../util/dvsim/verixcdc-report-parser.py      |  53 +-
 .../vendor/lowrisc_ip/util/uvmdvgen/README.md |   2 +-
 .../lowrisc_ip/util/uvmdvgen/agent.core.tpl   |   2 +-
 .../lowrisc_ip/util/uvmdvgen/agent.sv.tpl     |   2 +-
 .../lowrisc_ip/util/uvmdvgen/agent_cfg.sv.tpl |   2 +-
 .../lowrisc_ip/util/uvmdvgen/agent_cov.sv.tpl |   2 +-
 .../lowrisc_ip/util/uvmdvgen/agent_pkg.sv.tpl |   2 +-
 .../lowrisc_ip/util/uvmdvgen/base_seq.sv.tpl  |   2 +-
 .../lowrisc_ip/util/uvmdvgen/base_test.sv.tpl |   2 +-
 .../lowrisc_ip/util/uvmdvgen/base_vseq.sv.tpl |   2 +-
 .../lowrisc_ip/util/uvmdvgen/bind.sv.tpl      |   2 +-
 .../util/uvmdvgen/common_vseq.sv.tpl          |   2 +-
 .../lowrisc_ip/util/uvmdvgen/cov_excl.el.tpl  |   2 +-
 .../util/uvmdvgen/device_driver.sv.tpl        |   2 +-
 .../lowrisc_ip/util/uvmdvgen/driver.sv.tpl    |   2 +-
 .../lowrisc_ip/util/uvmdvgen/env.core.tpl     |   2 +-
 .../lowrisc_ip/util/uvmdvgen/env.sv.tpl       |   2 +-
 .../lowrisc_ip/util/uvmdvgen/env_cfg.sv.tpl   |   2 +-
 .../lowrisc_ip/util/uvmdvgen/env_cov.sv.tpl   |   2 +-
 .../lowrisc_ip/util/uvmdvgen/env_pkg.sv.tpl   |   2 +-
 .../lowrisc_ip/util/uvmdvgen/gen_agent.py     |   2 +-
 .../lowrisc_ip/util/uvmdvgen/gen_env.py       |   2 +-
 .../util/uvmdvgen/host_driver.sv.tpl          |   2 +-
 .../vendor/lowrisc_ip/util/uvmdvgen/if.sv.tpl |   2 +-
 .../lowrisc_ip/util/uvmdvgen/index.md.tpl     |   1 -
 .../lowrisc_ip/util/uvmdvgen/item.sv.tpl      |   2 +-
 .../lowrisc_ip/util/uvmdvgen/monitor.sv.tpl   |   4 +-
 .../util/uvmdvgen/scoreboard.sv.tpl           |   2 +-
 .../lowrisc_ip/util/uvmdvgen/seq_list.sv.tpl  |   2 +-
 .../lowrisc_ip/util/uvmdvgen/sim.core.tpl     |   2 +-
 .../util/uvmdvgen/sim_cfg.hjson.tpl           |   2 +-
 .../util/uvmdvgen/smoke_vseq.sv.tpl           |   2 +-
 .../lowrisc_ip/util/uvmdvgen/sva.core.tpl     |   2 +-
 .../vendor/lowrisc_ip/util/uvmdvgen/tb.sv.tpl |   5 +-
 .../lowrisc_ip/util/uvmdvgen/test.core.tpl    |   2 +-
 .../lowrisc_ip/util/uvmdvgen/test_pkg.sv.tpl  |   2 +-
 .../util/uvmdvgen/testplan.hjson.tpl          |   2 +-
 .../lowrisc_ip/util/uvmdvgen/uvmdvgen.py      |   2 +-
 .../util/uvmdvgen/virtual_sequencer.sv.tpl    |   2 +-
 .../lowrisc_ip/util/uvmdvgen/vseq_list.sv.tpl |   2 +-
 ...v_merge.tcl-to-pass-databases-in-ru.patch} |   0
 371 files changed, 3454 insertions(+), 2597 deletions(-)
 create mode 100644 vendor/lowrisc_ibex/NOTICE
 create mode 100644 vendor/lowrisc_ibex/SECURITY.md
 delete mode 100644 vendor/lowrisc_ibex/azure-pipelines.yml
 delete mode 100644 vendor/lowrisc_ibex/ci/azp-private.yml
 delete mode 100644 vendor/lowrisc_ibex/ci/ibex-rtl-ci-steps.yml
 delete mode 100644 vendor/lowrisc_ibex/ci/vars.yml
 delete mode 100755 vendor/lowrisc_ibex/ci/vars_to_logging_cmd.py
 delete mode 100644 vendor/lowrisc_ibex/rtl/ibex_pmp_reset_default.svh
 delete mode 100644 vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Modes.py
 create mode 100644 vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Regression.py
 create mode 100644 vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Test.py
 create mode 100644 vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/modes.py
 rename vendor/lowrisc_ibex/vendor/patches/lowrisc_ip/dv_tools/{0001-Change-xcelium-cov_merge.tcl-to-pass-databases-in-ru.patch => 0002-Change-xcelium-cov_merge.tcl-to-pass-databases-in-ru.patch} (100%)

diff --git a/vendor/lowrisc_ibex.lock.hjson b/vendor/lowrisc_ibex.lock.hjson
index 67af8588..0ef27f32 100644
--- a/vendor/lowrisc_ibex.lock.hjson
+++ b/vendor/lowrisc_ibex.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/lowRISC/ibex.git
-    rev: c9f4a329636e59acb10647333badbb31bc7512b8
+    rev: 594ea976c9dad793f87edf91ec1c4c1df447e6dc
   }
 }
diff --git a/vendor/lowrisc_ibex/.svlint.toml b/vendor/lowrisc_ibex/.svlint.toml
index 29bbeb09..50dd4fc4 100644
--- a/vendor/lowrisc_ibex/.svlint.toml
+++ b/vendor/lowrisc_ibex/.svlint.toml
@@ -5,7 +5,7 @@
 # Rules for svlint, a SystemVerilog linter commonly used in editors.
 # The configuration matches the lowRISC SystemVerilog style guide at
 # https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md.
-# See https://github.com/dalance/svlint/blob/master/RULES.md for a list of rules.
+# See https://github.com/dalance/svlint/blob/master/MANUAL.md for a list of rules.
 
 [option]
 exclude_paths = ["build.*", "sw/.*", ".sv.tpl$", "vendor/.*"]
diff --git a/vendor/lowrisc_ibex/NOTICE b/vendor/lowrisc_ibex/NOTICE
new file mode 100644
index 00000000..f6898e32
--- /dev/null
+++ b/vendor/lowrisc_ibex/NOTICE
@@ -0,0 +1,10 @@
+The Ibex Project
+Copyright 2024 lowRISC contributors.
+
+This product includes hardware and/or software developed as part of the
+Ibex(R) (https://github.com/lowRISC/ibex) and OpenTitan(R) projects.
+
+Ibex was originally developed by the PULP team at ETH Zurich and University of
+Bologna under the name zero-riscy. Ibex verification, performance enhancement
+and security hardening have been supported by the OpenTitan project
+(https://www.opentitan.org).
diff --git a/vendor/lowrisc_ibex/README.md b/vendor/lowrisc_ibex/README.md
index aca20e19..06c5603e 100644
--- a/vendor/lowrisc_ibex/README.md
+++ b/vendor/lowrisc_ibex/README.md
@@ -85,7 +85,7 @@ When contributing SystemVerilog source code, please try to be consistent and adh
 coding style guide](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md).
 
 When contributing C or C++ source code, please try to adhere to [the OpenTitan C++ coding style
-guide](https://docs.opentitan.org/doc/rm/c_cpp_coding_style/).
+guide](https://opentitan.org/book/doc/contributing/style_guides/c_cpp_coding_style.html).
 All C and C++ code should be formatted with clang-format before committing.
 Either run `clang-format -i filename.cc` or `git clang-format` on added files.
 
diff --git a/vendor/lowrisc_ibex/SECURITY.md b/vendor/lowrisc_ibex/SECURITY.md
new file mode 100644
index 00000000..ab79a39c
--- /dev/null
+++ b/vendor/lowrisc_ibex/SECURITY.md
@@ -0,0 +1,8 @@
+# Reporting Security Issues
+
+The lowRISC team and Ibex community (including the OpenTitan partnership) take security issues seriously.
+
+We appreciate all efforts to find security vulnerabilities in Ibex and ask that responsible disclosure is practiced should you discover a potential vulnerability.
+
+As Ibex and in particular its secure configuration was developed as part of [OpenTitan](https://www.github.com/lowrisc/opentitan) contact [security@opentitan.org](mailto:security@opentitan.org) to report any security issues and do not open a public issue.
+[security@opentitan.org](mailto:security@opentitan.org) will advise on the coordinated vulnerability disclosure (CVD) procedure.
diff --git a/vendor/lowrisc_ibex/azure-pipelines.yml b/vendor/lowrisc_ibex/azure-pipelines.yml
deleted file mode 100644
index 5f57fc11..00000000
--- a/vendor/lowrisc_ibex/azure-pipelines.yml
+++ /dev/null
@@ -1,129 +0,0 @@
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-
-# Azure Pipelines CI build configuration
-# Documentation at https://aka.ms/yaml
-
-variables:
-- template: ci/vars.yml
-
-trigger:
-  batch: true
-  branches:
-    include:
-    - '*'
-  tags:
-    include:
-    - '*'
-pr:
-  branches:
-    include:
-      - '*'
-
-# Note: All tests run as part of one job to avoid copying intermediate build
-# artifacts around (e.g. Verilator and toolchain builds). Once more builds/tests
-# are added, we need to re-evaluate this decision to parallelize jobs and
-# improve end-to-end CI times.
-
-jobs:
-- job: lint_dv
-  displayName: Run quality checks (Lint and DV)
-  pool:
-    vmImage: "ubuntu-20.04"
-  steps:
-  - bash: |
-      ci/install-build-deps.sh
-    displayName: Install build dependencies
-
-  - bash: |
-      echo $PATH
-      python3 --version
-      echo -n "fusesoc "
-      fusesoc --version
-      verilator --version
-      riscv32-unknown-elf-gcc --version
-      verible-verilog-lint --version
-    displayName: Display environment
-
-  # Verible format is experimental so only run on default config for now,
-  # will eventually become part of the per-config CI
-  - bash: |
-      fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_top_tracing
-      if [ $? != 0 ]; then
-        echo -n "##vso[task.logissue type=error]"
-        echo "Verilog format with Verible failed. Run 'fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_top_tracing' to check and fix all errors."
-        echo "This flow is currently experimental and failures can be ignored."
-      fi
-      # Show diff of what verilog_format would have changed, and then revert.
-      git diff
-      git reset --hard HEAD
-    continueOnError: true
-    displayName: Format all source code with Verible format (experimental)
-
-  - bash: |
-      fork_origin=$(git merge-base --fork-point origin/master)
-      changed_files=$(git diff --name-only $fork_origin | grep -v '^vendor' | grep -E '\.(cpp|cc|c|h)$')
-      test -z "$changed_files" || git diff -U0 $fork_origin $changed_files | clang-format-diff -p1 | tee clang-format-output
-      if [ -s clang-format-output ]; then
-        echo -n "##vso[task.logissue type=error]"
-        echo "C/C++ lint failed. Use 'git clang-format' with appropriate options to reformat the changed code."
-        exit 1
-      fi
-    # This check is not idempotent, but checks changes to a base branch.
-    # Run it only on pull requests.
-    condition: eq(variables['Build.Reason'], 'PullRequest')
-    displayName: 'Use clang-format to check C/C++ coding style'
-
-  - bash: |
-      # Build and run CSR testbench, chosen Ibex configuration does not effect
-      # this so doesn't need to be part of per-config CI
-      fusesoc --cores-root=. run --target=sim --tool=verilator lowrisc:ibex:tb_cs_registers
-    displayName: Build and run CSR testbench with Verilator
-
-  - bash: |
-      cd build
-      git clone https://github.com/riscv/riscv-compliance.git
-      cd riscv-compliance
-      git checkout "$RISCV_COMPLIANCE_GIT_VERSION"
-    displayName: Get RISC-V Compliance test suite
-
-  - bash: |
-      # Build CoreMark without performance counter dump for co-simulation testing
-      make -C ./examples/sw/benchmarks/coremark SUPPRESS_PCOUNT_DUMP=1
-      make -C ./examples/sw/simple_system/pmp_smoke_test
-      make -C ./examples/sw/simple_system/dit_test
-      make -C ./examples/sw/simple_system/dummy_instr_test
-    displayName: Build tests for verilator co-simulation
-
-  # Run Ibex RTL CI per supported configuration
-  - template : ci/ibex-rtl-ci-steps.yml
-    parameters:
-      ibex_configs:
-        # Note: Try to keep the list of configurations in sync with the one used
-        # in Private CI.
-        - small
-        - opentitan
-        - maxperf
-        - maxperf-pmp-bmbalanced
-        - maxperf-pmp-bmfull
-        - experimental-branch-predictor
-
-  # Run lint on simple system
-  - bash: |
-      fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_simple_system
-      if [ $? != 0 ]; then
-        echo -n "##vso[task.logissue type=error]"
-        echo "Verilog lint with Verilator failed. Run 'fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_simple_system' to check and fix all errors."
-        exit 1
-      fi
-    displayName: Run Verilator lint on simple system
-
-  - bash: |
-      fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_simple_system
-      if [ $? != 0 ]; then
-        echo -n "##vso[task.logissue type=error]"
-        echo "Verilog lint with Verible failed. Run 'fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_simple_system' to check and fix all errors."
-        exit 1
-      fi
-    displayName: Run Verible lint on simple system
diff --git a/vendor/lowrisc_ibex/ci/azp-private.yml b/vendor/lowrisc_ibex/ci/azp-private.yml
deleted file mode 100644
index 04df3f4b..00000000
--- a/vendor/lowrisc_ibex/ci/azp-private.yml
+++ /dev/null
@@ -1,31 +0,0 @@
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-#
-# Private CI trigger.  Used to run tooling that can't currently be shared
-# publicly.
-
-trigger:
-  batch: true
-  branches:
-    include:
-    - '*'
-  tags:
-    include:
-    - "*"
-pr:
-  branches:
-    include:
-    - '*'
-
-# The runner used for private CI enforces the use of the template below. All
-# build steps need to be placed into the template.
-resources:
-  repositories:
-  - repository: lowrisc-private-ci
-    type: github
-    endpoint: lowRISC
-    name: lowrisc/lowrisc-private-ci
-
-extends:
-  template: jobs-ibex.yml@lowrisc-private-ci
diff --git a/vendor/lowrisc_ibex/ci/ibex-rtl-ci-steps.yml b/vendor/lowrisc_ibex/ci/ibex-rtl-ci-steps.yml
deleted file mode 100644
index 55d0a2e0..00000000
--- a/vendor/lowrisc_ibex/ci/ibex-rtl-ci-steps.yml
+++ /dev/null
@@ -1,90 +0,0 @@
-parameters:
-  ibex_configs: []
-
-steps:
-  - ${{ each config in parameters.ibex_configs }}:
-    # ibex_config.py will exit with error code 1 on any error which will cause
-    # the CI to fail if there's an issue with the configuration file or an
-    # incorrect configuration name being used
-    - bash: |
-        set -e
-        IBEX_CONFIG_OPTS=`./util/ibex_config.py ${{ config }} fusesoc_opts`
-        echo $IBEX_CONFIG_OPTS
-        echo "##vso[task.setvariable variable=ibex_config_opts]" $IBEX_CONFIG_OPTS
-      displayName: Test and display fusesoc config for ${{ config }}
-
-    - bash: |
-        fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_top_tracing $IBEX_CONFIG_OPTS
-        if [ $? != 0 ]; then
-          echo -n "##vso[task.logissue type=error]"
-          echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_top_tracing $IBEX_CONFIG_OPTS' to check and fix all errors."
-          exit 1
-        fi
-      displayName: Lint Verilog source files with Verilator for ${{ config }}
-
-    - bash: |
-        fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_top_tracing $IBEX_CONFIG_OPTS
-        if [ $? != 0 ]; then
-          echo -n "##vso[task.logissue type=error]"
-          echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_top_tracing $IBEX_CONFIG_OPTS' to check and fix all errors."
-          exit 1
-        fi
-      displayName: Lint Verilog source files with Verible Verilog Lint for ${{ config }}
-
-    - bash: |
-        # Build simulation model of Ibex
-        fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_riscv_compliance $IBEX_CONFIG_OPTS
-        if [ $? != 0 ]; then
-          echo -n "##vso[task.logissue type=error]"
-          echo "Unable to build Verilator model of Ibex for compliance testing."
-          exit 1
-        fi
-
-        # Run compliance test suite
-        export TARGET_SIM=$PWD/build/lowrisc_ibex_ibex_riscv_compliance_0.1/sim-verilator/Vibex_riscv_compliance
-        export RISCV_PREFIX=riscv32-unknown-elf-
-        export RISCV_TARGET=ibex
-        export RISCV_DEVICE=rv32imc
-        fail=0
-        for isa in rv32i rv32im rv32imc rv32Zicsr rv32Zifencei; do
-          make -C build/riscv-compliance RISCV_ISA=$isa 2>&1 | tee run.log
-          if [ ${PIPESTATUS[0]} != 0 ]; then
-            echo -n "##vso[task.logissue type=error]"
-            echo "The RISC-V compliance test suite failed for $isa"
-
-            # There's no easy way to get the test results in machine-readable
-            # form to properly exclude known-failing tests. Going with an
-            # approximate solution for now.
-            if [ $isa == rv32i ] && grep -q 'FAIL: 4/48' run.log; then
-              echo -n "##vso[task.logissue type=error]"
-              echo "Expected failure for rv32i, see lowrisc/ibex#100 more more information."
-            else
-              fail=1
-            fi
-          fi
-        done
-        exit $fail
-      displayName: Run RISC-V Compliance test for Ibex RV32IMC for ${{ config }}
-
-    - bash: |
-        set -e
-        source ci/setup-cosim.sh
-        # Build simple system with co-simulation
-        fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system_cosim $IBEX_CONFIG_OPTS
-
-        # Run directed tests against simple system co-simulation
-        ./ci/run-cosim-test.sh --skip-pass-check CoreMark examples/sw/benchmarks/coremark/coremark.elf
-
-        if ./util/ibex_config.py ${{ config }} query_fields PMPEnable | grep -q 'PMPEnable=1'; then
-          ./ci/run-cosim-test.sh --skip-pass-check pmp_smoke examples/sw/simple_system/pmp_smoke_test/pmp_smoke_test.elf
-        else
-          echo "PMP not supported on ${{ config }}, skipping pmp_smoke_test"
-        fi
-
-        if ./util/ibex_config.py ${{ config }} query_fields SecureIbex | grep -q 'SecureIbex=1'; then
-          ./ci/run-cosim-test.sh dit_test examples/sw/simple_system/dit_test/dit_test.elf
-          ./ci/run-cosim-test.sh dummy_instr_test examples/sw/simple_system/dummy_instr_test/dummy_instr_test.elf
-        else
-          echo "Security features not supported on ${{ config }}, skipping security feature tests"
-        fi
-      displayName: Run Verilator co-sim tests for for ${{ config }}
diff --git a/vendor/lowrisc_ibex/ci/install-build-deps.sh b/vendor/lowrisc_ibex/ci/install-build-deps.sh
index 1da949ae..4dc913a8 100755
--- a/vendor/lowrisc_ibex/ci/install-build-deps.sh
+++ b/vendor/lowrisc_ibex/ci/install-build-deps.sh
@@ -26,7 +26,7 @@ if [ -z "$GITHUB_ACTIONS" ]; then
 fi
 
 case "$ID-$VERSION_ID" in
-  ubuntu-16.04|ubuntu-18.04|ubuntu-20.04)
+  ubuntu-20.04|ubuntu-22.04)
     # Curl must be available to get the repo key below.
     $SUDO_CMD apt-get update
     $SUDO_CMD apt-get install -y curl
@@ -60,14 +60,12 @@ case "$ID-$VERSION_ID" in
     $SUDO_CMD mkdir -p /tools/riscv-isa-sim
     $SUDO_CMD chmod 777 /tools/riscv-isa-sim
     $SUDO_CMD tar -C /tools/riscv-isa-sim -xvzf ibex-cosim-"$IBEX_COSIM_VERSION".tar.gz --strip-components=1
-    echo "##vso[task.prependpath]/tools/riscv-isa-sim/bin"
     echo "/tools/riscv-isa-sim/bin" >> $GITHUB_PATH
 
     wget https://storage.googleapis.com/verilator-builds/verilator-"$VERILATOR_VERSION".tar.gz
     $SUDO_CMD mkdir -p /tools/verilator
     $SUDO_CMD chmod 777 /tools/verilator
     $SUDO_CMD tar -C /tools/verilator -xvzf verilator-"$VERILATOR_VERSION".tar.gz
-    echo "##vso[task.prependpath]/tools/verilator/$VERILATOR_VERSION/bin"
     echo "/tools/verilator/$VERILATOR_VERSION/bin" >> $GITHUB_PATH
     # Python dependencies
     #
@@ -83,10 +81,11 @@ case "$ID-$VERSION_ID" in
     # Install Verible
     mkdir -p build/verible
     cd build/verible
-    curl -Ls -o verible.tar.gz "https://github.com/google/verible/releases/download/$VERIBLE_VERSION/verible-$VERIBLE_VERSION-Ubuntu-$VERSION_ID-$VERSION_CODENAME-x86_64.tar.gz"
-    $SUDO_CMD mkdir -p /tools/verible && $SUDO_CMD chmod 777 /tools/verible
-    tar -C /tools/verible -xf verible.tar.gz --strip-components=1
-    echo "##vso[task.prependpath]/tools/verible/bin"
+    VERIBLE_URL="https://github.com/chipsalliance/verible/releases/download/$VERIBLE_VERSION/verible-$VERIBLE_VERSION-linux-static-x86_64.tar.gz"
+    $SUDO_CMD mkdir -p /tools/verible
+    curl -sSfL "$VERIBLE_URL" | $SUDO_CMD tar -C /tools/verible -xvzf - --strip-components=1
+    # Fixup bin permission which is broken in tarball.
+    $SUDO_CMD chmod 755 /tools/verible/bin
     echo "/tools/verible/bin" >> $GITHUB_PATH
     ;;
 
@@ -101,6 +100,5 @@ TOOLCHAIN_URL="https://github.com/lowRISC/lowrisc-toolchains/releases/download/$
 mkdir -p build/toolchain
 curl -Ls -o build/toolchain/rv32-toolchain.tar.xz "$TOOLCHAIN_URL"
 $SUDO_CMD mkdir -p /tools/riscv && $SUDO_CMD chmod 777 /tools/riscv
-tar -C /tools/riscv -xf build/toolchain/rv32-toolchain.tar.xz --strip-components=1
-echo "##vso[task.prependpath]/tools/riscv/bin"
+$SUDO_CMD tar -C /tools/riscv -xf build/toolchain/rv32-toolchain.tar.xz --strip-components=1
 echo "/tools/riscv/bin" >> $GITHUB_PATH
diff --git a/vendor/lowrisc_ibex/ci/run-cosim-test.sh b/vendor/lowrisc_ibex/ci/run-cosim-test.sh
index 83e8b1d2..1165bf58 100755
--- a/vendor/lowrisc_ibex/ci/run-cosim-test.sh
+++ b/vendor/lowrisc_ibex/ci/run-cosim-test.sh
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 # Run an elf against simple system co-simulation and check the UART output for
-# reported pass/fail reporting as appropriate for use in Azure pipelines
+# reported pass/fail reporting as appropriate for use in GitHub Actions
 
 SKIP_PASS_CHECK=0
 
@@ -26,14 +26,12 @@ fi
 echo "Running $TEST_NAME with co-simulation"
 build/lowrisc_ibex_ibex_simple_system_cosim_0/sim-verilator/Vibex_simple_system --meminit=ram,$TEST_ELF
 if [ $? != 0 ]; then
-  echo "##vso[task.logissue type=error]Running % failed co-simulation testing"
   echo "::error::Running % failed co-simulation testing"
   exit 1
 fi
 
 grep 'FAILURE' ibex_simple_system.log
 if [ $? != 1 ]; then
-  echo "##vso[task.logissue type=error]Failure seen in $TEST_NAME log"
   echo "::error::Failure seen in $TEST_NAME log"
   echo "Log contents:"
   cat ibex_simple_system.log
@@ -43,7 +41,6 @@ fi
 if [ $SKIP_PASS_CHECK != 1 ]; then
   grep 'PASS' ibex_simple_system.log
   if [ $? != 0 ]; then
-    echo "##vso[task.logissue type=error]No pass seen in $TEST_NAME log"
     echo "::error::No pass seen in $TEST_NAME log"
     echo "Log contents:"
     cat ibex_simple_system.log
diff --git a/vendor/lowrisc_ibex/ci/vars.env b/vendor/lowrisc_ibex/ci/vars.env
index 38c8edeb..2e510087 100644
--- a/vendor/lowrisc_ibex/ci/vars.env
+++ b/vendor/lowrisc_ibex/ci/vars.env
@@ -5,11 +5,11 @@
 # Pipeline variables, used by the public and private CI pipelines
 # Quote values to ensure they are parsed as string (version numbers might
 # end up as float otherwise).
-VERILATOR_VERSION=v4.104
-IBEX_COSIM_VERSION=15fbd568
+VERILATOR_VERSION=v4.210
+IBEX_COSIM_VERSION=39612f9
 RISCV_TOOLCHAIN_TAR_VERSION=20220210-1
 RISCV_TOOLCHAIN_TAR_VARIANT=lowrisc-toolchain-gcc-rv32imcb
 RISCV_COMPLIANCE_GIT_VERSION=844c6660ef3f0d9b96957991109dfd80cc4938e2
-VERIBLE_VERSION=v0.0-2135-gb534c1fe
+VERIBLE_VERSION=v0.0-3622-g07b310a3
 # lowRISC-internal version numbers of Ibex-specific Spike builds.
 SPIKE_IBEX_VERSION=20220817-git-eccdcb15c3e51b4f7906c7b42fb824f24a4338a2
diff --git a/vendor/lowrisc_ibex/ci/vars.yml b/vendor/lowrisc_ibex/ci/vars.yml
deleted file mode 100644
index 91b16e3d..00000000
--- a/vendor/lowrisc_ibex/ci/vars.yml
+++ /dev/null
@@ -1,16 +0,0 @@
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-
-# Pipeline variables, used by the public and private CI pipelines
-# Quote values to ensure they are parsed as string (version numbers might
-# end up as float otherwise).
-variables:
-  VERILATOR_VERSION: "v4.104"
-  IBEX_COSIM_VERSION: "15fbd568"
-  RISCV_TOOLCHAIN_TAR_VERSION: "20220210-1"
-  RISCV_TOOLCHAIN_TAR_VARIANT: "lowrisc-toolchain-gcc-rv32imcb"
-  RISCV_COMPLIANCE_GIT_VERSION: "844c6660ef3f0d9b96957991109dfd80cc4938e2"
-  VERIBLE_VERSION: "v0.0-2135-gb534c1fe"
-  # lowRISC-internal version numbers of Ibex-specific Spike builds.
-  SPIKE_IBEX_VERSION: "20220817-git-eccdcb15c3e51b4f7906c7b42fb824f24a4338a2"
diff --git a/vendor/lowrisc_ibex/ci/vars_to_logging_cmd.py b/vendor/lowrisc_ibex/ci/vars_to_logging_cmd.py
deleted file mode 100755
index c719a0cb..00000000
--- a/vendor/lowrisc_ibex/ci/vars_to_logging_cmd.py
+++ /dev/null
@@ -1,43 +0,0 @@
-#!/usr/bin/env python3
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-
-# Read an Azure Pipelines-compatible variables file, and convert it into
-# logging commands that Azure Pipelines understands, effectively setting the
-# variables at runtime.
-#
-# This script can be used as a workaround if variables cannot be included in the
-# Pipeline definition directly.
-#
-# See https://docs.microsoft.com/en-us/azure/devops/pipelines/scripts/logging-commands
-# for more information on logging commands.
-
-import sys
-import yaml
-
-def vars_to_logging_cmd(vars_file):
-    data = {}
-    print(vars_file)
-    with open(vars_file, 'r', encoding="utf-8") as fp:
-        data = yaml.load(fp, Loader=yaml.SafeLoader)
-
-    if not (isinstance(data, dict) and 'variables' in data):
-        print("YAML file wasn't a dictionary with a 'variables' key. Got: {}"
-            .format(data))
-
-    print("Setting variables from {}".format(vars_file))
-    for key, value in data['variables'].items():
-        # Note: These lines won't show up in the Azure Pipelines output unless
-        # "System Diagnostics" are enabled (go to the Azure Pipelines web UI,
-        # click on "Run pipeline" to manually run a pipeline, and check "Enable
-        # system diagnostics".)
-        print("##vso[task.setvariable variable={}]{}".format(key, value))
-
-    return 0
-
-if __name__ == "__main__":
-    if len(sys.argv) < 2:
-        print("Usage: {} VARS_FILE".format(sys.argv[0]))
-        sys.exit(1)
-    sys.exit(vars_to_logging_cmd(sys.argv[1]))
diff --git a/vendor/lowrisc_ibex/doc/01_overview/verification_overview.rst b/vendor/lowrisc_ibex/doc/01_overview/verification_overview.rst
index 3f13bec5..77921b7f 100644
--- a/vendor/lowrisc_ibex/doc/01_overview/verification_overview.rst
+++ b/vendor/lowrisc_ibex/doc/01_overview/verification_overview.rst
@@ -14,7 +14,7 @@ The configuration space is too large to fully verify the design for all possible
 To manage this complexity regressions runs and verification closure target a number of :ref:`supported configurations<ibex-config>`.
 
 Current verification closure effort is focussed on the ``opentitan`` configuration and is the only configuration with nightly regression runs.
-Verification maturity is tracked via :ref:`verification_stages` that are `defined by the OpenTitan project <https://docs.opentitan.org/doc/project/development_stages/#hardware-verification-stages-v>`_.
+Verification maturity is tracked via :ref:`verification_stages` that are `defined by the OpenTitan project <https://opentitan.org/book/doc/project_governance/development_stages.html#hardware-verification-stages-v>`_.
 Ibex has achieved **V2S** for the `opentitan` configuration, broadly this means verification is almost complete (over 90% code and functional coverage hit with over 90% regression pass rate with test plan and coverage plan fully implemented) but not yet closed.
 
 Nightly regression results, including a coverage summary and details of test failures, for the ``opentitan`` Ibex configuration are published at https://ibex.reports.lowrisc.org/opentitan/latest/report.html. Below is a summary of these results:
diff --git a/vendor/lowrisc_ibex/doc/02_user/integration.rst b/vendor/lowrisc_ibex/doc/02_user/integration.rst
index 17e3652e..cc3c59c8 100644
--- a/vendor/lowrisc_ibex/doc/02_user/integration.rst
+++ b/vendor/lowrisc_ibex/doc/02_user/integration.rst
@@ -108,6 +108,8 @@ Instantiation Template
       .RndCnstLfsrSeed  ( ibex_pkg::RndCnstLfsrSeedDefault ),
       .RndCnstLfsrPerm  ( ibex_pkg::RndCnstLfsrPermDefault ),
       .DbgTriggerEn     ( 0                                ),
+      .DmBaseAddr       ( 32'h1A110000                     ),
+      .DmAddrMask       ( 32'h00000FFF                     ),
       .DmHaltAddr       ( 32'h1A110800                     ),
       .DmExceptionAddr  ( 32'h1A110808                     )
   ) u_top (
@@ -224,6 +226,10 @@ Parameters
 +------------------------------+---------------------+------------+-----------------------------------------------------------------------+
 | ``DbgTriggerEn``             | bit                 | 0          | Enable debug trigger support (one trigger only)                       |
 +------------------------------+---------------------+------------+-----------------------------------------------------------------------+
+| ``DmBaseAddr``               | int                 | 0x1A110000 | Base address of the Debug Module                                      |
++------------------------------+---------------------+------------+-----------------------------------------------------------------------+
+| ``DmAddrMask``               | int                 | 0x1A110000 | Address mask of the Debug Module                                      |
++------------------------------+---------------------+------------+-----------------------------------------------------------------------+
 | ``DmHaltAddr``               | int                 | 0x1A110800 | Address to jump to when entering Debug Mode                           |
 +------------------------------+---------------------+------------+-----------------------------------------------------------------------+
 | ``DmExceptionAddr``          | int                 | 0x1A110808 | Address to jump to when an exception occurs while in Debug Mode       |
diff --git a/vendor/lowrisc_ibex/doc/03_reference/coverage_plan.rst b/vendor/lowrisc_ibex/doc/03_reference/coverage_plan.rst
index ee95dd21..551aadea 100644
--- a/vendor/lowrisc_ibex/doc/03_reference/coverage_plan.rst
+++ b/vendor/lowrisc_ibex/doc/03_reference/coverage_plan.rst
@@ -60,12 +60,12 @@ Some categories are just a single instruction, which is named without further de
 * **CSRAccess** - Any instruction from Zicsr.
 * **EBreakDbg**/**EBreakExc** - An ``EBREAK`` instruction that either enters debug mode (Dbg) or causes an exception (Exc).
   Which occurs depends upon the setting of ``dcsr.ebreakm`` / ``dcsr.ebreaku`` combined with the privilege level of executed instruction.
-* ``ECALL``
-* ``MRET``
-* ``DRET``
-* ``WFI``
-* ``FENCE``
-* ``FENCE.I``
+* **ECall** - ``ECALL`` is an environment call used for escalation of privilege.
+* **MRet** - ``MRET`` return out of M-mode
+* **DRet** - ``DRET`` ruturn from debug mode.
+* **WFI** - wait for interrupt.
+* **Fence** - ``FENCE`` memory fence on the data side.
+* **FenceI** - ``FENCE.I`` instruction fence instruction.
 * **FetchError** - Any instruction that saw a fetch error.
 * **CompressedIllegal** - Any compressed instruction with an illegal encoding.
 * **UncompressedIllegal** - Any uncompressed instruction with an illegal encoding.
@@ -199,12 +199,13 @@ Each pipeline stage has some associated state.
 Exceptions/Interrupts/Debug
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 Exceptions, interrupts and debug entry can all cause control flow changes combined with CSR writes and privilege level changes and work quite similarly within the controller but not identically.
-Furthermore they can all occur together and must be appropriately prioritised (consider a instruction with hardware trigger point matching it, that causes some exception and an interrupt is raised the cycle it enters the ID/EX stage)
+Furthermore they can all occur together and must be appropriately prioritised (consider an instruction with hardware trigger point matching it, that causes some exception and an interrupt is raised the cycle it enters the ID/EX stage).
 
 * Exception from instruction fetch error (covered by the **FetchError** instruction category).
 * ``pmp_iside_mode_cross`` - Exception from instruction PMP violation.
 * Exception from illegal instruction (covered by the illegal instruction categories).
 * ``cp_ls_error_exception`` - Exception from memory fetch error.
+* ``cp_ls_pmp_exception`` - Load store unit exception from PMP.
 * ``pmp_dside_mode_cross`` - Exception from memory access PMP violation.
 * Unaligned memory access
 
@@ -223,6 +224,7 @@ Furthermore they can all occur together and must be appropriately prioritised (c
 * ``cp_single_step_exception`` - Single step over an instruction that takes an exception.
 * ``cp_insn_trigger_enter_debug`` - Instruction matches hardware trigger point.
 * ``cp_debug_mode`` - Ibex operating in debug mode.
+* ``cp_debug_wakeup`` - Ibex wakes up after being halted from debug request.
 * ``irq_wfi_cross``, ``debug_wfi_cross`` - Debug and Interrupt whilst sleeping with WFI
 
   * Cover with global interrupts enabled and disabled
@@ -262,11 +264,11 @@ PMP
   * ``cp_pmp_iside_region_override``, ``cp_pmp_iside2_region_override``, ``cp_pmp_dside_region_override`` - Higher priority entry allows access that lower priority entry prevents.
   * ``pmp_instr_edge_cross`` - Compressed instruction access (16-bit) passes PMP but 32-bit access at same address crosses PMP region boundary.
 
-* Each field of mssecfg enabled/disabled with relevant functionality tested.
+* Each field of mssecfg enabled/disabled, as well as written to using a CSR write, with relevant functionality tested.
 
   * RLB - rule locking bypass.
 
-    * ``cp_edit_locked_pmpcfg``,``cp_edit_locked_pmpaddr`` - Modify locked region with RLB set.
+    * ``cp_edit_locked_pmpcfg``, ``cp_edit_locked_pmpaddr`` - Modify locked region with RLB set.
     * ``rlb_csr_cross`` - Try to enable RLB when RLB is disabled and locked regions present.
 
   * MMWP - machine mode whitelist policy.
@@ -276,7 +278,7 @@ PMP
 
   * MML - machine mode lockdown policy.
 
-    * ``rlb_csr_cross`` - Try to disable when enabled.
+    * ``mml_sticky_cross`` - Try to disable when enabled.
 
 * Access close to PMP region modification that allows/disallows that access.
 
@@ -289,8 +291,8 @@ CSRs
 ^^^^
 Basic read/write functionality must be tested on all implemented CSRs.
 
-* ``cp_csr_read_only`` - Read from CSR.
-* ``cp_csr_write`` -  Write to CSR.
+* ``cp_csr_read_only`` - Read from CSR, there is also ``cp_csr_invalid_read_only`` for illegal CSRs.
+* ``cp_csr_write`` -  Write to CSR, there is also ``cp_csr_invalid_write`` for illegal CSRs.
 
   * Write to read only CSR.
     Covered by ensuring ``cp_csr_write`` is seen for read-only CSRs
@@ -340,7 +342,7 @@ For more detail about each security countermeasure in Ibex see :ref:`security`
 
 * ``cp_pc_mismatch_err`` - PC mismatch error seen.
 
-The :ref:`security features Ibex implements <security>` are given specific security countermeasure names in OpenTitan (see 'Security Countermeasures' in the `Hardware Interfaces <https://docs.opentitan.org/hw/ip/rv_core_ibex/doc/#hardware-interfaces>`_ documentation section).
+The :ref:`security features Ibex implements <security>` are given specific security countermeasure names in OpenTitan (see 'Security Countermeasures' in the `Comportability Definition and Specification <https://opentitan.org/book/doc/contributing/hw/comportability/index.html#security-countermeasures>`_ documentation section).
 The mapping between security countermeasures and coverpoints that demonstrate it being used is given below.
 
 +--------------------------------+-------------------------------------------------------+
@@ -373,6 +375,17 @@ The mapping between security countermeasures and coverpoints that demonstrate it
 | ICACHE.MEM.INTEGRITY           | ``cp_icache_ecc_err``                                 |
 +--------------------------------+-------------------------------------------------------+
 
+Memory Interface Behaviour
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+Covering different scenarios around timing of memory requests and responses and
+related behaviour
+
+* ``cp_dmem_response_latency``/``cp_imem_response_latency`` - Latency of response from request for dmem and imem.
+  Separated into two bins ``single_cycle`` (immediate response after request) and ``multi_cycle`` (all other latencies).
+* ``dmem_req_gnt_valid``/``imem_req_gnt_rvalid`` - Request, grant and rvalid all seen in the same cycle for dmem and imem.
+  This means a response is seen the same cycle a new request is being granted.
+
+
 Miscellaneous
 ^^^^^^^^^^^^^
 Various points of interest do not fit into the categories above.
diff --git a/vendor/lowrisc_ibex/doc/03_reference/cs_registers.rst b/vendor/lowrisc_ibex/doc/03_reference/cs_registers.rst
index 3b5c07ae..d334f0bd 100644
--- a/vendor/lowrisc_ibex/doc/03_reference/cs_registers.rst
+++ b/vendor/lowrisc_ibex/doc/03_reference/cs_registers.rst
@@ -72,7 +72,7 @@ Ibex implements all the Control and Status Registers (CSRs) listed in the follow
 +---------+--------------------+--------+-----------------------------------------------+
 |  0x7B3  | ``dscratch1``      | RW     | Debug Scratch Register 1                      |
 +---------+--------------------+--------+-----------------------------------------------+
-|  0x7C0  | ``cpuctrl``        | WARL   | CPU Control Register (Custom CSR)             |
+|  0x7C0  | ``cpuctrlsts``     | WARL   | CPU Control and Status Register (Custom CSR)  |
 +---------+--------------------+--------+-----------------------------------------------+
 |  0x7C1  | ``secureseed``     | WARL   | Security feature random seed (Custom CSR)     |
 +---------+--------------------+--------+-----------------------------------------------+
diff --git a/vendor/lowrisc_ibex/doc/03_reference/debug.rst b/vendor/lowrisc_ibex/doc/03_reference/debug.rst
index aef413a7..6b67db42 100644
--- a/vendor/lowrisc_ibex/doc/03_reference/debug.rst
+++ b/vendor/lowrisc_ibex/doc/03_reference/debug.rst
@@ -3,7 +3,7 @@
 Debug Support
 =============
 
-Ibex offers support for execution-based debug according to the `RISC-V Debug Specification <https://riscv.org/specifications/debug-specification/>`_, version 0.13.
+Ibex offers support for execution-based debug according to the `RISC-V Debug Specification <https://github.com/riscv/riscv-debug-spec/blob/0.13-test-release/riscv-debug-spec.pdf>`_, version 0.13.
 
 
 .. note::
@@ -32,6 +32,10 @@ Parameters
 +---------------------+-----------------------------------------------------------------+
 | Parameter           | Description                                                     |
 +=====================+=================================================================+
+| ``DmBaseAddr``      | Base address of the Debug Module                                |
++---------------------+-----------------------------------------------------------------+
+| ``DmAddrMask``      | Address mask of the Debug Module                                |
++---------------------+-----------------------------------------------------------------+
 | ``DmHaltAddr``      | Address to jump to when entering Debug Mode                     |
 +---------------------+-----------------------------------------------------------------+
 | ``DmExceptionAddr`` | Address to jump to when an exception occurs while in Debug Mode |
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diff --git a/vendor/lowrisc_ibex/doc/03_reference/instruction_decode_execute.rst b/vendor/lowrisc_ibex/doc/03_reference/instruction_decode_execute.rst
index 6fb037db..77340803 100644
--- a/vendor/lowrisc_ibex/doc/03_reference/instruction_decode_execute.rst
+++ b/vendor/lowrisc_ibex/doc/03_reference/instruction_decode_execute.rst
@@ -56,7 +56,7 @@ Arithmetic Logic Unit (ALU)
 ---------------------------
 Source File: :file:`rtl/ibex_alu.sv`
 
-The Arithmetic Logic Logic (ALU) is a purely combinational block that implements operations required for the Integer Computational Instructions and the comparison operations required for the Control Transfer Instructions in the RV32I RISC-V Specification.
+The Arithmetic Logic Unit (ALU) is a purely combinational block that implements operations required for the Integer Computational Instructions and the comparison operations required for the Control Transfer Instructions in the RV32I RISC-V Specification.
 Other blocks use the ALU for the following tasks:
 
 * Mult/Div uses it to perform addition as part of the multiplication and division algorithms
diff --git a/vendor/lowrisc_ibex/doc/03_reference/pmp.rst b/vendor/lowrisc_ibex/doc/03_reference/pmp.rst
index d418cadf..d4993020 100644
--- a/vendor/lowrisc_ibex/doc/03_reference/pmp.rst
+++ b/vendor/lowrisc_ibex/doc/03_reference/pmp.rst
@@ -50,5 +50,11 @@ Custom Reset Values
 
 By default all PMP CSRs (include ``mseccfg``) are reset to 0.
 Some applications may want other reset values.
-Default reset values are defined in :file:`ibex_pmp_reset_default.svh`.
-An implementation can either modify this file or define ``IBEX_CUSTOM_PMP_RESET_VALUES`` and place a copy of :file:`ibex_pmp_result_default.svh` in a new file, :file:`ibex_pmp_reset.svh`, changing the values as required and adding the new file to the include path of whatever build flow is being used.
+Default reset values are defined in :file:`ibex_pkg.sv`.
+An implementation can either modify this file or pass custom reset values as a module parameter.
+
+Debug Mode
+----------
+
+In debug mode, the PMP allows all accesses to addresses of the Debug Module, as defined by the `DmBaseAddr` and `DmAddrMask` module parameters.
+This is mandated by the RISC-V Debug Specification (v1.0.0).
diff --git a/vendor/lowrisc_ibex/doc/03_reference/verification.rst b/vendor/lowrisc_ibex/doc/03_reference/verification.rst
index 36159716..977cef0c 100644
--- a/vendor/lowrisc_ibex/doc/03_reference/verification.rst
+++ b/vendor/lowrisc_ibex/doc/03_reference/verification.rst
@@ -19,7 +19,7 @@ At a high level, this testbench uses the open source `RISCV-DV random instructio
 simple memory model, stimulates the Ibex core to run this program in memory, and then compares the
 core trace log against a golden model ISS trace log to check for correctness of execution.
 
-Verification maturity is tracked via :ref:`verification_stages` that are `defined by the OpenTitan project <https://docs.opentitan.org/doc/project/development_stages/#hardware-verification-stages-v>`_.
+Verification maturity is tracked via :ref:`verification_stages` that are `defined by the OpenTitan project <https://opentitan.org/book/doc/project_governance/development_stages.html#hardware-verification-stages-v>`_.
 
 Ibex has achieved **V2S** for the ``opentitan`` configuration, broadly this means verification almost complete (over 90% code and functional coverage hit with over 90% regression pass rate with test plan and coverage plan fully implemented) but not yet closed.
 
@@ -111,7 +111,7 @@ In order to run the co-simulation flow, you'll need:
   + Some custom CSRs
   + Custom NMI behavior
 
-  Ibex verification should work with the Spike version that is tagged as ``ibex-cosim-v0.5``.
+  Ibex verification should work with the Spike version that named ``ibex_cosim``.
 
   Spike must be built with the ``--enable-commitlog`` and ``--enable-misaligned`` options.
   ``--enable-commitlog`` is needed to produce log output to track the instructions that were executed.
@@ -140,7 +140,7 @@ to tell the RISCV-DV code where to find them:
 .. _LRSpike: https://github.com/lowRISC/riscv-isa-sim
 .. _riscv-toolchain-source: https://github.com/riscv/riscv-gnu-toolchain
 .. _riscv-toolchain-releases: https://github.com/lowRISC/lowrisc-toolchains/releases
-.. _bitmanip-patches: https://github.com/lowRISC/lowrisc-toolchains#how-to-generate-the-bitmanip-patches
+.. _bitmanip-patches: https://github.com/lowRISC/lowrisc-toolchains#how-to-generate-the-bitmanip-patch
 .. _bitmanip: https://github.com/riscv/riscv-bitmanip
 
 End-to-end RTL/ISS co-simulation flow
@@ -169,7 +169,7 @@ This mechanism is explained in detail at https://github.com/google/riscv-dv/blob
 As a sidenote, the signature address that this testbench uses for the handshaking is ``0x8ffffffc``.
 Additionally, as is mentioned in the RISCV-DV documentation of this handshake, a small set of API
 tasks are provided in `dv/uvm/core_ibex/tests/core_ibex_base_test.sv
-<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/tests/core_ibex_base_tests.sv>`_ to enable easy
+<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/tests/core_ibex_base_test.sv>`_ to enable easy
 and efficient integration and usage of this mechanism in this test environment.
 To see how this handshake is used during real simulations, look in
 `dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
diff --git a/vendor/lowrisc_ibex/doc/03_reference/verification_stages.rst b/vendor/lowrisc_ibex/doc/03_reference/verification_stages.rst
index a93fdb35..74f4c3e3 100644
--- a/vendor/lowrisc_ibex/doc/03_reference/verification_stages.rst
+++ b/vendor/lowrisc_ibex/doc/03_reference/verification_stages.rst
@@ -3,9 +3,9 @@
 Verification Stages
 ===================
 
-Ibex is being verified as part of the `OpenTitan <https://www.opentitan.org>`_ project and follows the `verification stages used in OpenTitan <https://docs.opentitan.org/doc/project/development_stages/#hardware-verification-stages-v>`_.
+Ibex is being verified as part of the `OpenTitan <https://www.opentitan.org>`_ project and follows the `verification stages used in OpenTitan <https://opentitan.org/book/doc/project_governance/development_stages.html#hardware-verification-stages-v>`_.
 The current verification stage of the 'opentitan' configuration of Ibex is **V2S**.
-The full definition of V2S can be found at the `OpenTitan V2 <https://docs.opentitan.org/doc/project/checklist/#v2>`_ and `OpenTitan V2S <https://docs.opentitan.org/doc/project/checklist/#v2s>`_ checklists.
+The full definition of V2S can be found at the `OpenTitan V2 <https://opentitan.org/book/doc/project_governance/checklist/index.html#v2>`_ and `OpenTitan V2S <https://opentitan.org/book/doc/project_governance/checklist/index.html#v2s>`_ checklists.
 Other Ibex configurations do not have a formal verification stage at present.
 
 V1 Checklist
@@ -84,7 +84,7 @@ V2 Checklist
 +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 | Tests         | SIM_FW_SIMULATED                    | N/A        | No ROM or firmware present.                                                                                                                                          |
 +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-| Regression    | SIM_NIGHTLY_REGRESSION_V2           | Complete   | Regression run in Azure pipeline only accessible to OpenTitan members.                                                                                               |
+| Regression    | SIM_NIGHTLY_REGRESSION_V2           | Complete   | Regression run in GitHub Actions only accessible to OpenTitan members.                                                                                               |
 |               |                                     |            | Publicly viewable reports on the `OpenTitan regression dashboard <https://reports.opentitan.org/hw/top_earlgrey/dv/summary/latest/report.html>`_ are planned for V3. |
 +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 | Coverage      | SIM_CODE_COVERAGE_V2                | Complete   | Coverage results available in nightly regression run.                                                                                                                |
@@ -136,7 +136,7 @@ V2S Checklist
 Ibex SEC_CM Test Mapping
 ------------------------
 
-The :ref:`security features Ibex implements <security>` are given specific security countermeasure names in OpenTitan (see 'Security Countermeasures' in the `Hardware Interfaces <https://docs.opentitan.org/hw/ip/rv_core_ibex/doc/#hardware-interfaces>`_ documentation section).
+The :ref:`security features Ibex implements <security>` are given specific security countermeasure names in OpenTitan (see 'Security Countermeasures' in the `Comportability Definition and Specification <https://opentitan.org/book/doc/contributing/hw/comportability/index.html#security-countermeasures>`_ documentation section).
 Each countermeasure has a test that exercises it.
 The mapping between countermeasures and tests is given below
 
diff --git a/vendor/lowrisc_ibex/doc/04_developer/concierge.rst b/vendor/lowrisc_ibex/doc/04_developer/concierge.rst
index 74efc594..497c1ec8 100644
--- a/vendor/lowrisc_ibex/doc/04_developer/concierge.rst
+++ b/vendor/lowrisc_ibex/doc/04_developer/concierge.rst
@@ -25,10 +25,8 @@ The concierge duties rotate between several core developers on a weekly basis.
 You can find today's concierge on duty in a `public calendar <https://calendar.google.com/calendar/embed?src=lowrisc.org_s0pdodkddnggdp40jusjij27h4%40group.calendar.google.com>`_.
 
 * Greg Chadwick (`@GregAC <https://github.com/gregac>`_)
-* Tom Roberts (`@tomroberts-lowrisc <https://github.com/tomroberts-lowrisc>`_)
 * Rupert Swarbrick (`@rswarbrick <https://github.com/rswarbrick>`_)
 * Pirmin Vogel (`@vogelpi <https://github.com/vogelpi>`_)
-* Philipp Wagner (`@imphil <https://github.com/imphil>`_)
 
 You can be Ibex Concierge, too.
 Please talk to any of the current concierges to discuss!
diff --git a/vendor/lowrisc_ibex/doc/requirements.txt b/vendor/lowrisc_ibex/doc/requirements.txt
index 8a199df0..d376d330 100644
--- a/vendor/lowrisc_ibex/doc/requirements.txt
+++ b/vendor/lowrisc_ibex/doc/requirements.txt
@@ -1,5 +1,5 @@
 setuptools_scm
-sphinx~=4.2
+sphinx>=7.0
 sphinx_rtd_theme
 sphinxcontrib-wavedrom
 wavedrom>=1.9.0rc1
diff --git a/vendor/lowrisc_ibex/dv/cosim/cosim.h b/vendor/lowrisc_ibex/dv/cosim/cosim.h
index 28c6805b..4a5c63c7 100644
--- a/vendor/lowrisc_ibex/dv/cosim/cosim.h
+++ b/vendor/lowrisc_ibex/dv/cosim/cosim.h
@@ -35,6 +35,10 @@ struct DSideAccessInfo {
   // `misaligned_first` set to true, there is no second half.
   bool misaligned_first;
   bool misaligned_second;
+
+  bool misaligned_first_saw_error;
+
+  bool m_mode_access;
 };
 
 class Cosim {
@@ -81,9 +85,17 @@ class Cosim {
 
   // Set the value of MIP.
   //
-  // At the next call of `step`, the MIP value will take effect (i.e. if it's a
+  // Two versions of MIP must be supplied the `pre_mip` and the `post_mip`. The
+  // `pre_mip` is the value of MIP that is used to determine if an interrupt is
+  // pending. The `post_mip` is the value of MIP that the next instruction
+  // executed (which will be the first instruction of the interrupt vector when
+  // an interrupt ir triggered) observes. These will be different in the case
+  // where an interrupt is raised triggering an interrupt handler but then
+  // drops before the first instruction of the handler has executed.
+  //
+  // At the next call of `step`, the MIP values will take effect (i.e. if it's a
   // new interrupt that is enabled it will step straight to that handler).
-  virtual void set_mip(uint32_t mip) = 0;
+  virtual void set_mip(uint32_t pre_mip, uint32_t post_mip) = 0;
 
   // Set the state of the NMI (non-maskable interrupt) line.
   //
diff --git a/vendor/lowrisc_ibex/dv/cosim/cosim_dpi.cc b/vendor/lowrisc_ibex/dv/cosim/cosim_dpi.cc
index 37862629..30a3da74 100644
--- a/vendor/lowrisc_ibex/dv/cosim/cosim_dpi.cc
+++ b/vendor/lowrisc_ibex/dv/cosim/cosim_dpi.cc
@@ -2,11 +2,13 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#include "cosim_dpi.h"
+
 #include <svdpi.h>
+
 #include <cassert>
 
 #include "cosim.h"
-#include "cosim_dpi.h"
 
 int riscv_cosim_step(Cosim *cosim, const svBitVecVal *write_reg,
                      const svBitVecVal *write_reg_data, const svBitVecVal *pc,
@@ -19,10 +21,11 @@ int riscv_cosim_step(Cosim *cosim, const svBitVecVal *write_reg,
              : 0;
 }
 
-void riscv_cosim_set_mip(Cosim *cosim, const svBitVecVal *mip) {
+void riscv_cosim_set_mip(Cosim *cosim, const svBitVecVal *pre_mip,
+                         const svBitVecVal *post_mip) {
   assert(cosim);
 
-  cosim->set_mip(mip[0]);
+  cosim->set_mip(pre_mip[0], post_mip[0]);
 }
 
 void riscv_cosim_set_nmi(Cosim *cosim, svBit nmi) {
@@ -66,17 +69,21 @@ void riscv_cosim_notify_dside_access(Cosim *cosim, svBit store,
                                      svBitVecVal *addr, svBitVecVal *data,
                                      svBitVecVal *be, svBit error,
                                      svBit misaligned_first,
-                                     svBit misaligned_second) {
+                                     svBit misaligned_second,
+                                     svBit misaligned_first_saw_error,
+                                     svBit m_mode_access) {
   assert(cosim);
 
-  cosim->notify_dside_access(
-      DSideAccessInfo{.store = store != 0,
-                      .data = data[0],
-                      .addr = addr[0],
-                      .be = be[0],
-                      .error = error != 0,
-                      .misaligned_first = misaligned_first != 0,
-                      .misaligned_second = misaligned_second != 0});
+  cosim->notify_dside_access(DSideAccessInfo{
+      .store = store != 0,
+      .data = data[0],
+      .addr = addr[0],
+      .be = be[0],
+      .error = error != 0,
+      .misaligned_first = misaligned_first != 0,
+      .misaligned_second = misaligned_second != 0,
+      .misaligned_first_saw_error = misaligned_first_saw_error != 0,
+      .m_mode_access = m_mode_access != 0});
 }
 
 void riscv_cosim_set_iside_error(Cosim *cosim, svBitVecVal *addr) {
diff --git a/vendor/lowrisc_ibex/dv/cosim/cosim_dpi.h b/vendor/lowrisc_ibex/dv/cosim/cosim_dpi.h
index e57bc942..bbadbc5e 100644
--- a/vendor/lowrisc_ibex/dv/cosim/cosim_dpi.h
+++ b/vendor/lowrisc_ibex/dv/cosim/cosim_dpi.h
@@ -8,6 +8,8 @@
 #include <stdint.h>
 #include <svdpi.h>
 
+#include "cosim.h"
+
 // This adapts the C++ interface of the `Cosim` class to be used via DPI. See
 // the documentation in cosim.h for further details
 
@@ -15,7 +17,8 @@ extern "C" {
 int riscv_cosim_step(Cosim *cosim, const svBitVecVal *write_reg,
                      const svBitVecVal *write_reg_data, const svBitVecVal *pc,
                      svBit sync_trap, svBit suppress_reg_write);
-void riscv_cosim_set_mip(Cosim *cosim, const svBitVecVal *mip);
+void riscv_cosim_set_mip(Cosim *cosim, const svBitVecVal *pre_mip,
+                         const svBitVecVal *post_mip);
 void riscv_cosim_set_nmi(Cosim *cosim, svBit nmi);
 void riscv_cosim_set_nmi_int(Cosim *cosim, svBit nmi_int);
 void riscv_cosim_set_debug_req(Cosim *cosim, svBit debug_req);
@@ -27,7 +30,9 @@ void riscv_cosim_notify_dside_access(Cosim *cosim, svBit store,
                                      svBitVecVal *addr, svBitVecVal *data,
                                      svBitVecVal *be, svBit error,
                                      svBit misaligned_first,
-                                     svBit misaligned_second);
+                                     svBit misaligned_second,
+                                     svBit misaligned_first_saw_error,
+                                     svBit m_mode_access);
 void riscv_cosim_set_iside_error(Cosim *cosim, svBitVecVal *addr);
 int riscv_cosim_get_num_errors(Cosim *cosim);
 const char *riscv_cosim_get_error(Cosim *cosim, int index);
diff --git a/vendor/lowrisc_ibex/dv/cosim/cosim_dpi.svh b/vendor/lowrisc_ibex/dv/cosim/cosim_dpi.svh
index 4e2b98de..35ecd3b8 100644
--- a/vendor/lowrisc_ibex/dv/cosim/cosim_dpi.svh
+++ b/vendor/lowrisc_ibex/dv/cosim/cosim_dpi.svh
@@ -12,7 +12,8 @@
 
 import "DPI-C" function int riscv_cosim_step(chandle cosim_handle, bit [4:0] write_reg,
   bit [31:0] write_reg_data, bit [31:0] pc, bit sync_trap, bit suppress_reg_write);
-import "DPI-C" function void riscv_cosim_set_mip(chandle cosim_handle, bit [31:0] mip);
+import "DPI-C" function void riscv_cosim_set_mip(chandle cosim_handle, bit [31:0] pre_mip,
+  bit [31:0] post_mip);
 import "DPI-C" function void riscv_cosim_set_nmi(chandle cosim_handle, bit nmi);
 import "DPI-C" function void riscv_cosim_set_nmi_int(chandle cosim_handle, bit nmi_int);
 import "DPI-C" function void riscv_cosim_set_debug_req(chandle cosim_handle, bit debug_req);
@@ -22,7 +23,7 @@ import "DPI-C" function void riscv_cosim_set_csr(chandle cosim_handle, int csr_i
 import "DPI-C" function void riscv_cosim_set_ic_scr_key_valid(chandle cosim_handle, bit valid);
 import "DPI-C" function void riscv_cosim_notify_dside_access(chandle cosim_handle, bit store,
   bit [31:0] addr, bit [31:0] data, bit [3:0] be, bit error, bit misaligned_first,
-  bit misaligned_second);
+  bit misaligned_second, bit misaligned_first_saw_error, bit m_mode_access);
 import "DPI-C" function int riscv_cosim_set_iside_error(chandle cosim_handle, bit [31:0] addr);
 import "DPI-C" function int riscv_cosim_get_num_errors(chandle cosim_handle);
 import "DPI-C" function string riscv_cosim_get_error(chandle cosim_handle, int index);
diff --git a/vendor/lowrisc_ibex/dv/cosim/spike_cosim.cc b/vendor/lowrisc_ibex/dv/cosim/spike_cosim.cc
index 9a581e4f..336d5209 100644
--- a/vendor/lowrisc_ibex/dv/cosim/spike_cosim.cc
+++ b/vendor/lowrisc_ibex/dv/cosim/spike_cosim.cc
@@ -3,17 +3,19 @@
 // SPDX-License-Identifier: Apache-2.0
 
 #include "spike_cosim.h"
+
+#include <cassert>
+#include <iostream>
+#include <sstream>
+
 #include "riscv/config.h"
 #include "riscv/decode.h"
 #include "riscv/devices.h"
 #include "riscv/log_file.h"
+#include "riscv/mmu.h"
 #include "riscv/processor.h"
 #include "riscv/simif.h"
 
-#include <cassert>
-#include <iostream>
-#include <sstream>
-
 // For a short time, we're going to support building against version
 // ibex-cosim-v0.2 (20a886c) and also ibex-cosim-v0.3 (9af9730). Unfortunately,
 // they've got different APIs and spike doesn't expose a version string.
@@ -48,10 +50,17 @@ SpikeCosim::SpikeCosim(const std::string &isa_string, uint32_t start_pc,
       std::make_unique<processor_t>(isa_string.c_str(), "MU", DEFAULT_VARCH,
                                     this, 0, false, log_file, std::cerr);
 #else
-  isa_parser = std::make_unique<isa_parser_t>(isa_string.c_str(), "MU");
 
+#ifdef COSIM_SIGSEGV_WORKAROUND
+  isa_parser = new isa_parser_t(isa_string.c_str(), "MU");
+  processor = std::make_unique<processor_t>(isa_parser, DEFAULT_VARCH, this, 0,
+                                            false, log_file, std::cerr);
+#else
+  isa_parser = std::make_unique<isa_parser_t>(isa_string.c_str(), "MU");
   processor = std::make_unique<processor_t>(
       isa_parser.get(), DEFAULT_VARCH, this, 0, false, log_file, std::cerr);
+#endif
+
 #endif
 
   processor->set_pmp_num(pmp_num_regions);
@@ -76,8 +85,9 @@ bool SpikeCosim::mmio_load(reg_t addr, size_t len, uint8_t *bytes) {
   bool dut_error = false;
 
   // Incoming access may be an iside or dside access. Use PC to help determine
-  // which.
-  uint32_t pc = processor->get_state()->pc;
+  // which. PC is 64 bits in spike, we only care about the bottom 32-bit so mask
+  // off the top bits.
+  uint64_t pc = processor->get_state()->pc & 0xffffffff;
   uint32_t aligned_addr = addr & 0xfffffffc;
 
   if (pending_iside_error && (aligned_addr == pending_iside_err_addr)) {
@@ -85,17 +95,14 @@ bool SpikeCosim::mmio_load(reg_t addr, size_t len, uint8_t *bytes) {
     // assume it's an iside access and produce an error.
     pending_iside_error = false;
     dut_error = true;
-  } else if (addr < pc || addr >= (pc + 8)) {
+  } else {
     // Spike may attempt to access up to 8-bytes from the PC when fetching, so
-    // only check as a dside access when it falls outside that range.
-
-    // Otherwise check if the aligned PC matches with the aligned address or an
-    // incremented aligned PC (to capture the unaligned 4-byte instruction
-    // case). Assume a successful iside access if either of these checks are
-    // true, otherwise assume a dside access and check against DUT dside
-    // accesses.  If the RTL produced a bus error for the access, or the
-    // checking failed produce a memory fault in spike.
-    dut_error = (check_mem_access(false, addr, len, bytes) != kCheckMemOk);
+    // only check as a dside access when it falls outside that range
+    bool in_iside_range = (addr >= pc && addr < pc + 8);
+
+    if (!in_iside_range) {
+      dut_error = (check_mem_access(false, addr, len, bytes) != kCheckMemOk);
+    }
   }
 
   return !(bus_error || dut_error);
@@ -254,8 +261,8 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
     if (pending_sync_exception) {
       if (!sync_trap) {
         std::stringstream err_str;
-        err_str << "Synchronous trap was expected at ISS PC: "
-                << std::hex << processor->get_state()->pc
+        err_str << "Synchronous trap was expected at ISS PC: " << std::hex
+                << processor->get_state()->pc
                 << " but the DUT didn't report one at PC " << pc;
         errors.emplace_back(err_str.str());
         return false;
@@ -287,9 +294,8 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
 
   if (pending_iside_error) {
     std::stringstream err_str;
-    err_str << "DUT generated an iside error for address: "
-            << std::hex << pending_iside_err_addr
-            << " but the ISS didn't produce one";
+    err_str << "DUT generated an iside error for address: " << std::hex
+            << pending_iside_err_addr << " but the ISS didn't produce one";
     errors.emplace_back(err_str.str());
     return false;
   }
@@ -322,8 +328,8 @@ bool SpikeCosim::check_retired_instr(uint32_t write_reg,
   if ((processor->get_state()->last_inst_pc & 0xffffffff) != dut_pc) {
     std::stringstream err_str;
     err_str << "PC mismatch, DUT retired : " << std::hex << dut_pc
-            << " , but the ISS retired: "
-            << std::hex << processor->get_state()->last_inst_pc;
+            << " , but the ISS retired: " << std::hex
+            << processor->get_state()->last_inst_pc;
     errors.emplace_back(err_str.str());
     return false;
   }
@@ -378,18 +384,17 @@ bool SpikeCosim::check_retired_instr(uint32_t write_reg,
   return true;
 }
 
-bool SpikeCosim::check_sync_trap(uint32_t write_reg,
-                                 uint32_t dut_pc, uint32_t initial_spike_pc) {
+bool SpikeCosim::check_sync_trap(uint32_t write_reg, uint32_t dut_pc,
+                                 uint32_t initial_spike_pc) {
   // Check if an synchronously-trapping instruction matches
   // between Spike and the DUT.
 
   // Check that both spike and DUT trapped on the same pc
   if (initial_spike_pc != dut_pc) {
     std::stringstream err_str;
-    err_str << "PC mismatch at synchronous trap, DUT at pc: "
-            << std::hex << dut_pc
-            << "while ISS pc is at : "
-            << std::hex << initial_spike_pc;
+    err_str << "PC mismatch at synchronous trap, DUT at pc: " << std::hex
+            << dut_pc << "while ISS pc is at : " << std::hex
+            << initial_spike_pc;
     errors.emplace_back(err_str.str());
     return false;
   }
@@ -404,6 +409,12 @@ bool SpikeCosim::check_sync_trap(uint32_t write_reg,
     return false;
   }
 
+  if ((processor->get_state()->mcause->read() == 0x5) ||
+      (processor->get_state()->mcause->read() == 0x7)) {
+    // We have a load or store access fault, apply fixup for misaligned accesses
+    misaligned_pmp_fixup();
+  }
+
   // If we see an internal NMI, that means we receive an extra memory intf item.
   // Deleting that is necessary since next Load/Store would fail otherwise.
   if (processor->get_state()->mcause->read() == 0xFFFFFFE0) {
@@ -570,11 +581,12 @@ void SpikeCosim::initial_proc_setup(uint32_t start_pc, uint32_t start_mtvec,
   }
 }
 
-void SpikeCosim::set_mip(uint32_t mip) {
-  uint32_t new_mip = mip;
+void SpikeCosim::set_mip(uint32_t pre_mip, uint32_t post_mip) {
+  uint32_t new_mip = pre_mip;
   uint32_t old_mip = processor->get_state()->mip->read();
 
-  processor->get_state()->mip->write_with_mask(0xffffffff, mip);
+  processor->get_state()->mip->write_with_mask(0xffffffff, post_mip);
+  processor->get_state()->mip->write_pre_val(pre_mip);
 
   if (processor->get_state()->debug_mode ||
       (processor->halt_request == processor_t::HR_REGULAR) ||
@@ -612,6 +624,62 @@ void SpikeCosim::early_interrupt_handle() {
   }
 }
 
+// Ibex splits misaligned accesses into two separate requests. They
+// independently undergo PMP access checks. It is possible for one to fail (so
+// no request produced for that half of the access) whilst the other successed
+// (producing a request for that half of the access).
+//
+// Spike splits misaligned accesses up into bytes and will apply PMP access
+// checks byte by byte in a linear order. As soon as a byte sees a PMP
+// permission failure the rest of the misaligned access is aborted.
+//
+// This results in mismatches as in some misaligned access cases Ibex will
+// produce a request and spike will not.
+//
+// This fixup detects this condition and removes the Ibex access from
+// pending_dside_accesses to avoid a mismatch. This removed access is checked
+// against PMP using the spike MMU to check spike agrees it passes PMP checks.
+//
+// There may be a better way to handle this (e.g. altering spike behaviour to
+// match Ibex) so for now a warning is generated in fixup cases so they can be
+// easily identified.
+void SpikeCosim::misaligned_pmp_fixup() {
+  if (pending_dside_accesses.size() != 0) {
+    auto &top_pending_access = pending_dside_accesses.front();
+    auto &top_pending_access_info = top_pending_access.dut_access_info;
+
+    // If top access is the second half of a misaligned access where the first
+    // half saw an error we have the PMP fixup case
+    if (top_pending_access_info.misaligned_second &&
+        top_pending_access_info.misaligned_first_saw_error) {
+      mmu_t *mmu = processor->get_mmu();
+
+      // Check if the second half of the access (which Ibex produces a request
+      // for and spike does not) passes PMP
+      if (!mmu->pmp_ok(top_pending_access_info.addr, 4,
+                       top_pending_access_info.store ? STORE : LOAD,
+                       top_pending_access_info.m_mode_access ? PRV_M : PRV_U)) {
+        // Raise an error if the second half shouldn't have passed PMP
+        std::stringstream err_str;
+        err_str << "Saw second half of a misaligned access which not have "
+                << "generated a memory request as it does not pass a PMP check,"
+                << " address: " << std::hex << top_pending_access_info.addr;
+        errors.emplace_back(err_str.str());
+      } else {
+        // Output warning on stdout so we're aware which tests this is happening
+        // in
+        std::cout << "WARNING: Cosim dropping second half of misaligned access "
+                  << "as first half saw an error and second half passed PMP "
+                  << "check, address: " << std::hex
+                  << top_pending_access_info.addr << std::endl;
+        std::cout << std::dec;
+
+        pending_dside_accesses.erase(pending_dside_accesses.begin());
+      }
+    }
+  }
+}
+
 void SpikeCosim::set_nmi(bool nmi) {
   if (nmi && !nmi_mode && !processor->get_state()->debug_mode &&
       processor->halt_request != processor_t::HR_REGULAR) {
diff --git a/vendor/lowrisc_ibex/dv/cosim/spike_cosim.h b/vendor/lowrisc_ibex/dv/cosim/spike_cosim.h
index 369afa7f..a4baad5d 100644
--- a/vendor/lowrisc_ibex/dv/cosim/spike_cosim.h
+++ b/vendor/lowrisc_ibex/dv/cosim/spike_cosim.h
@@ -22,7 +22,17 @@
 
 class SpikeCosim : public simif_t, public Cosim {
  private:
+  // A sigsegv has been observed when deleting isa_parser_t instances under
+  // Xcelium on CentOS 7. The root cause is unknown so for a workaround simply
+  // use a raw pointer for isa_parser that never gets deleted. This produces a
+  // minor memory leak but it is of little consequence as when SpikeCosim is
+  // being deleted it is the end of simulation and the process will be
+  // terminated shortly anyway.
+#ifdef COSIM_SIGSEGV_WORKAROUND
+  isa_parser_t *isa_parser;
+#else
   std::unique_ptr<isa_parser_t> isa_parser;
+#endif
   std::unique_ptr<processor_t> processor;
   std::unique_ptr<log_file_t> log;
   bus_t bus;
@@ -85,6 +95,8 @@ class SpikeCosim : public simif_t, public Cosim {
 
   void early_interrupt_handle();
 
+  void misaligned_pmp_fixup();
+
   unsigned int insn_cnt;
 
  public:
@@ -113,7 +125,7 @@ class SpikeCosim : public simif_t, public Cosim {
                            uint32_t dut_pc, bool suppress_reg_write);
   bool check_sync_trap(uint32_t write_reg, uint32_t pc,
                        uint32_t initial_spike_pc);
-  void set_mip(uint32_t mip) override;
+  void set_mip(uint32_t pre_mip, uint32_t post_mip) override;
   void set_nmi(bool nmi) override;
   void set_nmi_int(bool nmi_int) override;
   void set_debug_req(bool debug_req) override;
diff --git a/vendor/lowrisc_ibex/dv/cs_registers/lint/verilator_waiver.vlt b/vendor/lowrisc_ibex/dv/cs_registers/lint/verilator_waiver.vlt
index 14f01fab..911700c5 100644
--- a/vendor/lowrisc_ibex/dv/cs_registers/lint/verilator_waiver.vlt
+++ b/vendor/lowrisc_ibex/dv/cs_registers/lint/verilator_waiver.vlt
@@ -9,7 +9,7 @@
 // 'rtl' directory), see verilator_waiver_rtl.vlt in the same
 // directory.
 //
-// See https://www.veripool.org/projects/verilator/wiki/Manual-verilator#CONFIGURATION-FILES
+// See https://verilator.org/guide/latest/exe_verilator.html#configuration-files
 // for documentation.
 //
 // Important: This file must included *before* any other Verilog file is read.
diff --git a/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core b/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core
index 6f53ee3f..9e45809f 100644
--- a/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core
+++ b/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core
@@ -161,6 +161,6 @@ targets:
           - '--trace-structs'
           - '--trace-params'
           - '--trace-max-array 1024'
-          - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_riscv_compliance -g"'
+          - '-CFLAGS "-std=c++14 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_riscv_compliance -g"'
           - '-LDFLAGS "-pthread -lutil -lelf"'
           - "-Wall"
diff --git a/vendor/lowrisc_ibex/dv/riscv_compliance/lint/verilator_waiver.vlt b/vendor/lowrisc_ibex/dv/riscv_compliance/lint/verilator_waiver.vlt
index fc9e0973..287b8406 100644
--- a/vendor/lowrisc_ibex/dv/riscv_compliance/lint/verilator_waiver.vlt
+++ b/vendor/lowrisc_ibex/dv/riscv_compliance/lint/verilator_waiver.vlt
@@ -9,7 +9,7 @@
 // 'rtl' directory), see verilator_waiver_rtl.vlt in the same
 // directory.
 //
-// See https://www.veripool.org/projects/verilator/wiki/Manual-verilator#CONFIGURATION-FILES
+// See https://verilator.org/guide/latest/exe_verilator.html#configuration-files
 // for documentation.
 //
 // Important: This file must included *before* any other Verilog file is read.
diff --git a/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv b/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
index 8d3669ef..10d0bb05 100644
--- a/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
+++ b/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
@@ -155,6 +155,8 @@ module ibex_riscv_compliance (
       .DbgTriggerEn     (DbgTriggerEn      ),
       .SecureIbex       (SecureIbex        ),
       .ICacheScramble   (ICacheScramble    ),
+      .DmBaseAddr       (32'h00000000      ),
+      .DmAddrMask       (32'h00000003      ),
       .DmHaltAddr       (32'h00000000      ),
       .DmExceptionAddr  (32'h00000000      )
     ) u_top (
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/Makefile b/vendor/lowrisc_ibex/dv/uvm/core_ibex/Makefile
index c36e1703..69909cac 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/Makefile
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/Makefile
@@ -52,6 +52,12 @@ IBEX_CONFIG         := opentitan
 # Path to DUT used for coverage reports
 DUT_COV_RTL_PATH    := "ibex_top"
 
+export EXTRA_COSIM_CFLAGS ?=
+
+ifeq ($(COSIM_SIGSEGV_WORKAROUND), 1)
+	EXTRA_COSIM_CFLAGS += -DCOSIM_SIGSEGV_WORKAROUND
+endif
+
 ###############################################################################
 
 # Setup the necessary paths for all python scripts to find all other relevant modules.
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv
index 7dca9682..5fd0685e 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv
@@ -120,7 +120,7 @@ class ibex_cosim_scoreboard extends uvm_scoreboard;
         // cosim with interrupt information and loop back to await the next item.
         riscv_cosim_set_nmi(cosim_handle, rvfi_instr.nmi);
         riscv_cosim_set_nmi_int(cosim_handle, rvfi_instr.nmi_int);
-        riscv_cosim_set_mip(cosim_handle, rvfi_instr.mip);
+        riscv_cosim_set_mip(cosim_handle, rvfi_instr.pre_mip, rvfi_instr.pre_mip);
 
         continue;
       end
@@ -145,7 +145,7 @@ class ibex_cosim_scoreboard extends uvm_scoreboard;
       riscv_cosim_set_debug_req(cosim_handle, rvfi_instr.debug_req);
       riscv_cosim_set_nmi(cosim_handle, rvfi_instr.nmi);
       riscv_cosim_set_nmi_int(cosim_handle, rvfi_instr.nmi_int);
-      riscv_cosim_set_mip(cosim_handle, rvfi_instr.mip);
+      riscv_cosim_set_mip(cosim_handle, rvfi_instr.pre_mip, rvfi_instr.post_mip);
       riscv_cosim_set_mcycle(cosim_handle, rvfi_instr.mcycle);
 
       // Set performance counters through a pseudo-backdoor write
@@ -178,7 +178,8 @@ class ibex_cosim_scoreboard extends uvm_scoreboard;
       dmem_port.get(mem_op);
       // Notify the cosim of all dside accesses emitted by the RTL
       riscv_cosim_notify_dside_access(cosim_handle, mem_op.read_write == WRITE, mem_op.addr,
-        mem_op.data, mem_op.be, mem_op.error, mem_op.misaligned_first, mem_op.misaligned_second);
+        mem_op.data, mem_op.be, mem_op.error, mem_op.misaligned_first, mem_op.misaligned_second,
+        mem_op.misaligned_first_saw_error, mem_op.m_mode_access);
     end
   endtask: run_cosim_dmem
 
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_monitor.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_monitor.sv
index c3fb29a2..0bf50116 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_monitor.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_monitor.sv
@@ -37,7 +37,8 @@ class ibex_rvfi_monitor extends uvm_monitor;
       trans_collected.rd_addr          = vif.monitor_cb.rd_addr;
       trans_collected.rd_wdata         = vif.monitor_cb.rd_wdata;
       trans_collected.order            = vif.monitor_cb.order;
-      trans_collected.mip              = vif.monitor_cb.ext_mip;
+      trans_collected.pre_mip          = vif.monitor_cb.ext_pre_mip;
+      trans_collected.post_mip         = vif.monitor_cb.ext_post_mip;
       trans_collected.nmi              = vif.monitor_cb.ext_nmi;
       trans_collected.nmi_int          = vif.monitor_cb.ext_nmi_int;
       trans_collected.debug_req        = vif.monitor_cb.ext_debug_req;
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_seq_item.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_seq_item.sv
index 55e11f9d..dceba31c 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_seq_item.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_seq_item.sv
@@ -9,7 +9,8 @@ class ibex_rvfi_seq_item extends uvm_sequence_item;
   bit [4:0]  rd_addr;
   bit [31:0] rd_wdata;
   bit [63:0] order;
-  bit [31:0] mip;
+  bit [31:0] pre_mip;
+  bit [31:0] post_mip;
   bit        nmi;
   bit        nmi_int;
   bit        debug_req;
@@ -26,7 +27,8 @@ class ibex_rvfi_seq_item extends uvm_sequence_item;
     `uvm_field_int (rd_addr, UVM_DEFAULT)
     `uvm_field_int (rd_wdata, UVM_DEFAULT)
     `uvm_field_int (order, UVM_DEFAULT)
-    `uvm_field_int (mip, UVM_DEFAULT)
+    `uvm_field_int (pre_mip, UVM_DEFAULT)
+    `uvm_field_int (post_mip, UVM_DEFAULT)
     `uvm_field_int (nmi, UVM_DEFAULT)
     `uvm_field_int (nmi_int, UVM_DEFAULT)
     `uvm_field_int (debug_req, UVM_DEFAULT)
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf.sv
index 02390905..e170e4dd 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf.sv
@@ -24,6 +24,9 @@ interface ibex_mem_intf#(
   wire                     error;
   wire                     misaligned_first;
   wire                     misaligned_second;
+  wire                     misaligned_first_saw_error;
+  wire                     m_mode_access;
+  wire                     spurious_response;
 
   clocking request_driver_cb @(posedge clk);
     input   reset;
@@ -38,6 +41,7 @@ interface ibex_mem_intf#(
     input   rdata;
     input   rintg;
     input   error;
+    input   spurious_response;
   endclocking
 
   clocking response_driver_cb @(posedge clk);
@@ -53,6 +57,7 @@ interface ibex_mem_intf#(
     output  rdata;
     output  rintg;
     output  error;
+    output  spurious_response;
   endclocking
 
   clocking monitor_cb @(posedge clk);
@@ -70,6 +75,9 @@ interface ibex_mem_intf#(
     input error;
     input misaligned_first;
     input misaligned_second;
+    input misaligned_first_saw_error;
+    input m_mode_access;
+    input spurious_response;
   endclocking
 
   task automatic wait_clks(input int num);
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_monitor.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_monitor.sv
index e8c48f8f..c37fb499 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_monitor.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_monitor.sv
@@ -10,18 +10,28 @@ class ibex_mem_intf_monitor extends uvm_monitor;
 
   protected virtual ibex_mem_intf vif;
 
+  // The monitor tick event fires every clock cycle once any writes to
+  // outstanding_access_port and addr_ph_ports have occurred.
+  event monitor_tick;
+
   mailbox #(ibex_mem_intf_seq_item)          collect_response_queue;
   uvm_analysis_port#(ibex_mem_intf_seq_item) item_collected_port;
   uvm_analysis_port#(ibex_mem_intf_seq_item) addr_ph_port;
+  // The number of outstanding accesses is written to this port every clock cycle
+  uvm_analysis_port#(int)                    outstanding_accesses_port;
 
   `uvm_component_utils(ibex_mem_intf_monitor)
   `uvm_component_new
 
+  int outstanding_accesses = 0;
+
   function void build_phase(uvm_phase phase);
     super.build_phase(phase);
     item_collected_port = new("item_collected_port", this);
     addr_ph_port = new("addr_ph_port_monitor", this);
     collect_response_queue = new();
+    outstanding_accesses_port = new("outstanding_accesses_port", this);
+
     if(!uvm_config_db#(virtual ibex_mem_intf)::get(this, "", "vif", vif)) begin
        `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"});
     end
@@ -52,16 +62,32 @@ class ibex_mem_intf_monitor extends uvm_monitor;
 
   virtual protected task collect_address_phase();
     ibex_mem_intf_seq_item trans_collected;
+
+
     forever begin
+      @(vif.monitor_cb);
+
       trans_collected = ibex_mem_intf_seq_item::type_id::create("trans_collected");
-      while(!(vif.monitor_cb.request && vif.monitor_cb.grant)) vif.wait_clks(1);
-      trans_collected.addr              = vif.monitor_cb.addr;
-      trans_collected.be                = vif.monitor_cb.be;
-      trans_collected.misaligned_first  = vif.monitor_cb.misaligned_first;
-      trans_collected.misaligned_second = vif.monitor_cb.misaligned_second;
+
+      while (!(vif.monitor_cb.request && vif.monitor_cb.grant)) begin
+        if (vif.monitor_cb.rvalid && !vif.monitor_cb.spurious_response) begin
+          outstanding_accesses--;
+        end
+        outstanding_accesses_port.write(outstanding_accesses);
+
+        -> monitor_tick;
+        @(vif.monitor_cb);
+      end
+
+      trans_collected.addr                       = vif.monitor_cb.addr;
+      trans_collected.be                         = vif.monitor_cb.be;
+      trans_collected.misaligned_first           = vif.monitor_cb.misaligned_first;
+      trans_collected.misaligned_second          = vif.monitor_cb.misaligned_second;
+      trans_collected.misaligned_first_saw_error = vif.monitor_cb.misaligned_first_saw_error;
+      trans_collected.m_mode_access              = vif.monitor_cb.m_mode_access;
       `uvm_info(get_full_name(), $sformatf("Detect request with address: %0x",
                 trans_collected.addr), UVM_HIGH)
-      if(vif.monitor_cb.we) begin
+      if (vif.monitor_cb.we) begin
         trans_collected.read_write = WRITE;
         trans_collected.data = vif.monitor_cb.wdata;
         trans_collected.intg = vif.monitor_cb.wintg;
@@ -71,7 +97,14 @@ class ibex_mem_intf_monitor extends uvm_monitor;
       addr_ph_port.write(trans_collected);
       `uvm_info(get_full_name(),"Send through addr_ph_port", UVM_HIGH)
       collect_response_queue.put(trans_collected);
-      vif.wait_clks(1);
+
+      outstanding_accesses++;
+      if (vif.monitor_cb.rvalid && !vif.monitor_cb.spurious_response) begin
+        outstanding_accesses--;
+      end
+      outstanding_accesses_port.write(outstanding_accesses);
+
+      -> monitor_tick;
     end
   endtask : collect_address_phase
 
@@ -80,8 +113,8 @@ class ibex_mem_intf_monitor extends uvm_monitor;
     forever begin
       collect_response_queue.get(trans_collected);
       do
-        vif.wait_clks(1);
-      while(vif.monitor_cb.rvalid === 0);
+        @(vif.monitor_cb);
+      while(vif.monitor_cb.rvalid === 0 || vif.monitor_cb.spurious_response === 1);
 
       if (trans_collected.read_write == READ) begin
         trans_collected.data = vif.monitor_cb.rdata;
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv
index f4c70754..6ad0a267 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_request_driver.sv
@@ -81,7 +81,7 @@ class ibex_mem_intf_request_driver extends uvm_driver #(ibex_mem_intf_seq_item);
     forever begin
       rdata_queue.get(tr);
       vif.wait_clks(1);
-      while(vif.rvalid !== 1'b1) vif.wait_clks(1);
+      while((vif.rvalid !== 1'b1 || vif.spurious_response === 1'b1)) vif.wait_clks(1);
       if(tr.read_write == READ)
         tr.data = vif.request_driver_cb.rdata;
         tr.intg = vif.request_driver_cb.rintg;
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_agent.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_agent.sv
index 7bb60e48..c6326389 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_agent.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_agent.sv
@@ -44,9 +44,12 @@ class ibex_mem_intf_response_agent extends uvm_agent;
     if(get_is_active() == UVM_ACTIVE) begin
       driver.seq_item_port.connect(sequencer.seq_item_export);
       monitor.addr_ph_port.connect(sequencer.addr_ph_port.analysis_export);
+      monitor.outstanding_accesses_port.connect(sequencer.outstanding_accesses_imp);
     end
     driver.cfg = cfg;
     sequencer.cfg = cfg;
+
+    sequencer.monitor_tick = monitor.monitor_tick;
   endfunction : connect_phase
 
   function void reset();
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_agent_cfg.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_agent_cfg.sv
index d1b1c4a1..04c2575a 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_agent_cfg.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_agent_cfg.sv
@@ -39,19 +39,25 @@ class ibex_mem_intf_response_agent_cfg extends uvm_object;
   // CONTROL_KNOB : enable/disable to generation of bad integrity upon uninit accesses
   bit enable_bad_intg_on_uninit_access = 0;
 
+  int unsigned spurious_response_delay_min = 0;
+  int unsigned spurious_response_delay_max = 100;
+
   constraint zero_delays_c {
     zero_delays dist {1 :/ zero_delay_pct,
                       0 :/ 100 - zero_delay_pct};
   }
 
   `uvm_object_utils_begin(ibex_mem_intf_response_agent_cfg)
-    `uvm_field_int(fixed_data_write_response, UVM_DEFAULT)
-    `uvm_field_int(gnt_delay_min,             UVM_DEFAULT)
-    `uvm_field_int(gnt_delay_max,             UVM_DEFAULT)
-    `uvm_field_int(valid_delay_min,           UVM_DEFAULT)
-    `uvm_field_int(valid_delay_max,           UVM_DEFAULT)
-    `uvm_field_int(zero_delays,               UVM_DEFAULT)
-    `uvm_field_int(zero_delay_pct,            UVM_DEFAULT)
+    `uvm_field_int(fixed_data_write_response,   UVM_DEFAULT)
+    `uvm_field_int(gnt_delay_min,               UVM_DEFAULT)
+    `uvm_field_int(gnt_delay_max,               UVM_DEFAULT)
+    `uvm_field_int(valid_delay_min,             UVM_DEFAULT)
+    `uvm_field_int(valid_delay_max,             UVM_DEFAULT)
+    `uvm_field_int(zero_delays,                 UVM_DEFAULT)
+    `uvm_field_int(zero_delay_pct,              UVM_DEFAULT)
+    `uvm_field_int(spurious_response_delay_min, UVM_DEFAULT)
+    `uvm_field_int(spurious_response_delay_max, UVM_DEFAULT)
+
   `uvm_object_utils_end
 
   function new(string name = "");
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_driver.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_driver.sv
index b907a744..e136c2f9 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_driver.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_driver.sv
@@ -62,11 +62,12 @@ class ibex_mem_intf_response_driver extends uvm_driver #(ibex_mem_intf_seq_item)
 
   virtual protected task get_and_drive();
     wait (cfg.vif.response_driver_cb.reset === 1'b0);
+
     fork
       begin
         forever begin
           ibex_mem_intf_seq_item req, req_c;
-          cfg.vif.wait_clks(1);
+          @(cfg.vif.response_driver_cb);
           seq_item_port.get_next_item(req);
           $cast(req_c, req.clone());
           if(~cfg.vif.response_driver_cb.reset) begin
@@ -112,17 +113,34 @@ class ibex_mem_intf_response_driver extends uvm_driver #(ibex_mem_intf_seq_item)
   virtual protected task send_read_data();
     ibex_mem_intf_seq_item tr;
     forever begin
-      cfg.vif.wait_clks(1);
-      cfg.vif.response_driver_cb.rvalid <=  1'b0;
-      cfg.vif.response_driver_cb.rdata  <= 'x;
-      cfg.vif.response_driver_cb.rintg  <= 'x;
-      cfg.vif.response_driver_cb.error  <= 'x;
+      @(cfg.vif.response_driver_cb);
+      cfg.vif.response_driver_cb.rvalid            <= 1'b0;
+      cfg.vif.response_driver_cb.spurious_response <= 1'b0;
+      cfg.vif.response_driver_cb.rdata             <= 'x;
+      cfg.vif.response_driver_cb.rintg             <= 'x;
+      cfg.vif.response_driver_cb.error             <= 'x;
+
       rdata_queue.get(tr);
+
+      `uvm_info(`gfn, $sformatf("Got response for addr %x", tr.addr), UVM_HIGH)
+
       if(cfg.vif.response_driver_cb.reset) continue;
-      cfg.vif.wait_clks(tr.rvalid_delay);
+
+      repeat (tr.rvalid_delay) @(cfg.vif.response_driver_cb);
+
       if(~cfg.vif.response_driver_cb.reset) begin
+        if (tr.spurious_response) begin
+          `uvm_info(`gfn, $sformatf("Driving spurious response"), UVM_HIGH)
+        end else begin
+          `uvm_info(`gfn, $sformatf("Driving response for addr %x", tr.addr), UVM_HIGH)
+        end
+
         cfg.vif.response_driver_cb.rvalid <= 1'b1;
         cfg.vif.response_driver_cb.error  <= tr.error;
+        // A spurious response is not associated with any request. This is flagged in the vif
+        // signals so other components in the testbench can ignore them if needed.
+        cfg.vif.response_driver_cb.spurious_response <= tr.spurious_response;
+
         if (tr.read_write == READ) begin
           cfg.vif.response_driver_cb.rdata <= tr.data;
           cfg.vif.response_driver_cb.rintg <= tr.intg;
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv
index c73a53c0..614216f6 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv
@@ -18,11 +18,20 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item);
   bit                    error_synch = 1'b1;
   bit                    is_dmem_seq = 1'b0;
   bit                    suppress_error_on_exc = 1'b0;
+  bit                    enable_spurious_response = 1'b0;
+
 
   `uvm_object_utils(ibex_mem_intf_response_seq)
   `uvm_declare_p_sequencer(ibex_mem_intf_response_sequencer)
   `uvm_object_new
 
+  rand int unsigned spurious_response_delay_cycles;
+
+  constraint spurious_response_delay_cycles_c {
+    spurious_response_delay_cycles inside {[p_sequencer.cfg.spurious_response_delay_min :
+                                            p_sequencer.cfg.spurious_response_delay_max]};
+  }
+
   virtual task body();
     virtual core_ibex_dut_probe_if ibex_dut_vif;
 
@@ -33,6 +42,9 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item);
 
     if (m_mem == null) `uvm_fatal(get_full_name(), "Cannot get memory model")
     `uvm_info(`gfn, $sformatf("is_dmem_seq: 0x%0x", is_dmem_seq), UVM_LOW)
+
+    `DV_CHECK_MEMBER_RANDOMIZE_FATAL(spurious_response_delay_cycles)
+
     forever
     begin
       bit [ADDR_WIDTH-1:0] aligned_addr;
@@ -41,12 +53,48 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item);
       bit [INTG_WIDTH-1:0] read_intg;
       bit                  data_was_uninitialized = 1'b0;
 
-      p_sequencer.addr_ph_port.get(item);
+      if (enable_spurious_response) begin
+        // When spurious responses are enabled we wake every monitor tick to decide whether to
+        // insert a spurious response.
+        while (1) begin
+          @p_sequencer.monitor_tick;
+
+          if (p_sequencer.addr_ph_port.try_get(item)) begin
+            // If we have a new request proceed as normal.
+            break;
+          end
+
+          if ((spurious_response_delay_cycles == 0)
+            && (p_sequencer.outstanding_accesses == 0)) begin
+
+            // If we've hit the time generate a new spurious responses and there's no outstanding
+            // responses (we must only generate a spurious response when the interface is idle)
+            // send one to the driver.
+            req = ibex_mem_intf_seq_item::type_id::create("req");
+
+            `DV_CHECK_RANDOMIZE_WITH_FATAL(req, rvalid_delay == 0;)
+
+            req.spurious_response = 1'b1;
+            {req.intg, req.data} = prim_secded_pkg::prim_secded_inv_39_32_enc(req.data);
+
+            `uvm_info(`gfn, $sformatf("Generated spurious response:\n%0s", req.sprint()), UVM_HIGH)
+            start_item(req);
+            finish_item(req);
+
+            `DV_CHECK_MEMBER_RANDOMIZE_FATAL(spurious_response_delay_cycles)
+          end else if (spurious_response_delay_cycles > 0) begin
+            spurious_response_delay_cycles = spurious_response_delay_cycles - 1;
+          end
+        end
+      end else begin
+        // Without spurious responses just wait for the monitor to report a new request
+        p_sequencer.addr_ph_port.get(item);
+      end
+
       aligned_addr = {item.addr[DATA_WIDTH-1:2], 2'b0};
 
       req = ibex_mem_intf_seq_item::type_id::create("req");
       error_synch = 1'b0;
-
       if (suppress_error_on_exc &&
             (ibex_dut_vif.dut_cb.sync_exc_seen || ibex_dut_vif.dut_cb.irq_exc_seen)) begin
         enable_error = 1'b0;
@@ -75,6 +123,7 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item);
       }) begin
         `uvm_fatal(`gfn, "Cannot randomize response request")
       end
+
       error_synch = 1'b1;
       enable_error = 1'b0; // Disable after single inserted error.
       aligned_addr = {req.addr[DATA_WIDTH-1:2], 2'b0};
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_sequencer.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_sequencer.sv
index 77a66643..71b17aa3 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_sequencer.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_sequencer.sv
@@ -10,13 +10,18 @@ class ibex_mem_intf_response_sequencer extends uvm_sequencer #(ibex_mem_intf_seq
 
   // TLM port to peek the address phase from the response monitor
   uvm_tlm_analysis_fifo #(ibex_mem_intf_seq_item) addr_ph_port;
+  uvm_analysis_imp #(int, ibex_mem_intf_response_sequencer) outstanding_accesses_imp;
   ibex_mem_intf_response_agent_cfg cfg;
 
+  event monitor_tick = null;
+  int outstanding_accesses = 0;
+
   `uvm_component_utils(ibex_mem_intf_response_sequencer)
 
   function new (string name, uvm_component parent);
     super.new(name, parent);
     addr_ph_port = new("addr_ph_port_sequencer", this);
+    outstanding_accesses_imp = new("outstanding_access_imp", this);
   endfunction : new
 
   // On reset, empty the tlm fifo
@@ -24,4 +29,8 @@ class ibex_mem_intf_response_sequencer extends uvm_sequencer #(ibex_mem_intf_seq
     addr_ph_port.flush();
   endfunction
 
+  function void write(int x);
+    outstanding_accesses = x;
+  endfunction
+
 endclass : ibex_mem_intf_response_sequencer
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_seq_item.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_seq_item.sv
index d8b502ed..55633abb 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_seq_item.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_seq_item.sv
@@ -17,20 +17,26 @@ class ibex_mem_intf_seq_item extends uvm_sequence_item;
   rand bit [3:0]                req_delay;
   rand bit [5:0]                rvalid_delay;
   rand bit                      error;
+       bit                      spurious_response;
        bit                      misaligned_first;
        bit                      misaligned_second;
+       bit                      misaligned_first_saw_error;
+       bit                      m_mode_access;
 
   `uvm_object_utils_begin(ibex_mem_intf_seq_item)
-    `uvm_field_int      (addr,              UVM_DEFAULT)
-    `uvm_field_enum     (rw_e, read_write,  UVM_DEFAULT)
-    `uvm_field_int      (be,                UVM_DEFAULT)
-    `uvm_field_int      (data,             UVM_DEFAULT)
-    `uvm_field_int      (intg,             UVM_DEFAULT)
-    `uvm_field_int      (gnt_delay,         UVM_DEFAULT)
-    `uvm_field_int      (rvalid_delay,      UVM_DEFAULT)
-    `uvm_field_int      (error,             UVM_DEFAULT)
-    `uvm_field_int      (misaligned_first,  UVM_DEFAULT)
-    `uvm_field_int      (misaligned_second, UVM_DEFAULT)
+    `uvm_field_int      (addr,                       UVM_DEFAULT)
+    `uvm_field_enum     (rw_e, read_write,           UVM_DEFAULT)
+    `uvm_field_int      (be,                         UVM_DEFAULT)
+    `uvm_field_int      (data,                       UVM_DEFAULT)
+    `uvm_field_int      (intg,                       UVM_DEFAULT)
+    `uvm_field_int      (gnt_delay,                  UVM_DEFAULT)
+    `uvm_field_int      (rvalid_delay,               UVM_DEFAULT)
+    `uvm_field_int      (error,                      UVM_DEFAULT)
+    `uvm_field_int      (misaligned_first,           UVM_DEFAULT)
+    `uvm_field_int      (misaligned_second,          UVM_DEFAULT)
+    `uvm_field_int      (misaligned_first_saw_error, UVM_DEFAULT)
+    `uvm_field_int      (m_mode_access,              UVM_DEFAULT)
+    `uvm_field_int      (spurious_response,          UVM_DEFAULT)
   `uvm_object_utils_end
 
   `uvm_object_new
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv
index 380d1f3b..b63065f5 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv
@@ -34,6 +34,7 @@ interface core_ibex_dut_probe_if(input logic clk);
   logic                              rf_ren_b;
   logic                              rf_rd_a_wb_match;
   logic                              rf_rd_b_wb_match;
+  logic                              rf_write_wb;
   logic                              sync_exc_seen;
   logic                              irq_exc_seen;
   logic                              csr_save_cause;
@@ -80,6 +81,7 @@ interface core_ibex_dut_probe_if(input logic clk);
     input rf_ren_b;
     input rf_rd_a_wb_match;
     input rf_rd_b_wb_match;
+    input rf_write_wb;
     input sync_exc_seen;
     input irq_exc_seen;
     input wb_exception;
@@ -93,6 +95,7 @@ interface core_ibex_dut_probe_if(input logic clk);
   `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_ren_b, rf_ren_b)
   `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_rd_a_wb_match, rf_rd_a_wb_match)
   `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_rd_b_wb_match, rf_rd_b_wb_match)
+  `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_write_wb, rf_write_wb)
   `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_alert_minor, alert_minor)
   `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_ic_tag_req, ic_tag_req)
   `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_ic_tag_write, ic_tag_write)
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_env_cfg.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_env_cfg.sv
index 6231af86..1d59338b 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_env_cfg.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_env_cfg.sv
@@ -31,6 +31,14 @@ class core_ibex_env_cfg extends uvm_object;
   // If '1', reaching the timeout in seconds fatally ends the test.
   // If '0', we end the test with a pass.
   bit                          is_timeout_s_fatal = 1;
+  // If '1' core_ibex_vseq will randomly choose to enable spurious responses in the data side memory
+  // agent. This will also disable assertions that check the memory interface protocol as spurious
+  // responses violate them.
+  bit                          enable_spurious_dside_responses = 1;
+
+  // If spurious responses are enabled what percentage of tests will enable them
+  int unsigned spurious_response_pct = 20;
+
 
   `uvm_object_utils_begin(core_ibex_env_cfg)
     `uvm_field_int(enable_double_fault_detector, UVM_DEFAULT)
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_rvfi_if.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_rvfi_if.sv
index 641e8152..0199b87f 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_rvfi_if.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/env/core_ibex_rvfi_if.sv
@@ -26,7 +26,8 @@ interface core_ibex_rvfi_if(input logic clk);
   logic [3:0]  mem_wmask;
   logic [31:0] mem_rdata;
   logic [31:0] mem_wdata;
-  logic [31:0] ext_mip;
+  logic [31:0] ext_pre_mip;
+  logic [31:0] ext_post_mip;
   logic        ext_nmi;
   logic        ext_nmi_int;
   logic [31:0] ext_debug_req;
@@ -62,7 +63,8 @@ interface core_ibex_rvfi_if(input logic clk);
     input mem_wmask;
     input mem_rdata;
     input mem_wdata;
-    input ext_mip;
+    input ext_pre_mip;
+    input ext_post_mip;
     input ext_nmi;
     input ext_nmi_int;
     input ext_debug_req;
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
index 1ef6a5e0..3c844da7 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
@@ -20,7 +20,15 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
   input fcov_rf_ecc_err_a_id,
   input fcov_rf_ecc_err_b_id,
 
-  input ibex_mubi_t fetch_enable_i
+  input ibex_mubi_t fetch_enable_i,
+
+  input instr_req_o,
+  input instr_gnt_i,
+  input instr_rvalid_i,
+
+  input data_req_o,
+  input data_gnt_i,
+  input data_rvalid_i
 );
   `include "dv_fcov_macros.svh"
   import uvm_pkg::*;
@@ -390,6 +398,28 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
   logic rf_we_glitch_err;
   logic lockstep_glitch_err;
 
+  logic imem_single_cycle_response, dmem_single_cycle_response;
+
+  mem_monitor_if iside_mem_monitor(
+    .clk_i,
+    .rst_ni,
+    .req_i(instr_req_o),
+    .gnt_i(instr_gnt_i),
+    .rvalid_i(instr_rvalid_i),
+    .outstanding_requests_o(),
+    .single_cycle_response_o(imem_single_cycle_response)
+  );
+
+  mem_monitor_if dside_mem_monitor(
+    .clk_i,
+    .rst_ni,
+    .req_i(data_req_o),
+    .gnt_i(data_gnt_i),
+    .rvalid_i(data_rvalid_i),
+    .outstanding_requests_o(),
+    .single_cycle_response_o(dmem_single_cycle_response)
+  );
+
   covergroup uarch_cg @(posedge clk_i);
     option.per_instance = 1;
     option.name = "uarch_cg";
@@ -613,6 +643,20 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
     cp_misaligned_second_data_bus_err: coverpoint load_store_unit_i.data_bus_err_i iff
       (load_store_unit_i.fcov_mis_rvalid_2);
 
+    cp_imem_response_latency: coverpoint imem_single_cycle_response iff (instr_rvalid_i) {
+      bins single_cycle = {1'b1};
+      bins multi_cycle = {1'b0};
+    }
+
+    `DV_FCOV_EXPR_SEEN(imem_req_gnt_rvalid, instr_rvalid_i & instr_req_o & instr_gnt_i)
+
+    cp_dmem_response_latency: coverpoint dmem_single_cycle_response iff (data_rvalid_i) {
+      bins single_cycle = {1'b1};
+      bins multi_cycle = {1'b0};
+    }
+
+    `DV_FCOV_EXPR_SEEN(dmem_req_gnt_rvalid, data_rvalid_i & data_req_o & data_gnt_i)
+
     misaligned_data_bus_err_cross: cross cp_misaligned_first_data_bus_err,
                                          cp_misaligned_second_data_bus_err {
       // Cannot see both bus errors together as they're signalled at different states of the load
@@ -656,7 +700,8 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
       illegal_bins illegal =
         // Only Div, Mul, Branch and Jump instructions can see an instruction stall
         (!binsof(cp_id_instr_category) intersect {InstrCategoryDiv, InstrCategoryMul,
-                                                 InstrCategoryBranch, InstrCategoryJump} &&
+                                                 InstrCategoryBranch, InstrCategoryJump,
+                                                 InstrCategoryFenceI} &&
          binsof(cp_stall_type_id) intersect {IdStallTypeInstr})
     ||
         // Only ALU, Mul, Div, Branch, Jump, Load, Store and CSR Access can see a load hazard stall
@@ -701,7 +746,8 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
       illegal_bins illegal =
         // Only Div, Mul, Branch and Jump instructions can see an instruction stall
         (!binsof(cp_id_instr_category) intersect {InstrCategoryDiv, InstrCategoryMul,
-                                                 InstrCategoryBranch, InstrCategoryJump} &&
+                                                 InstrCategoryBranch, InstrCategoryJump,
+                                                 InstrCategoryFenceI} &&
          binsof(cp_stall_type_id) intersect {IdStallTypeInstr})
     ||
         // Only ALU, Mul, Div, Branch, Jump, Load, Store and CSR Access can see a load hazard stall
@@ -712,9 +758,12 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
          binsof(cp_stall_type_id) intersect {IdStallTypeLdHz});
 
       // Cannot have a memory stall when we see an LS exception unless it is a load or store
-      // instruction
+      // instruction or a fetch error (the raw instruction decode can still indicate a load or store
+      // which produces a stall, though won't cause any load or store to occur due to the fetch
+      // error).
       illegal_bins mem_stall_illegal =
-        (!binsof(cp_id_instr_category) intersect {InstrCategoryLoad, InstrCategoryStore} &&
+        (!binsof(cp_id_instr_category) intersect {InstrCategoryLoad, InstrCategoryStore,
+                                                  InstrCategoryFetchError} &&
          binsof(cp_stall_type_id) intersect {IdStallTypeMem}) with
         (cp_ls_pmp_exception == 1'b1 || cp_ls_error_exception == 1'b1);
 
@@ -764,3 +813,42 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
 
   `DV_FCOV_INSTANTIATE_CG(uarch_cg, en_uarch_cov)
 endinterface
+
+interface mem_monitor_if (
+  input clk_i,
+  input rst_ni,
+
+  input req_i,
+  input gnt_i,
+  input rvalid_i,
+
+  output int   outstanding_requests_o,
+  output logic single_cycle_response_o
+);
+
+  int outstanding_requests;
+  logic outstanding_requests_inc, outstanding_requests_dec;
+  logic no_outstanding_requests_last_cycle;
+
+  assign outstanding_requests_inc = req_i & gnt_i;
+  assign outstanding_requests_dec = rvalid_i;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (~rst_ni) begin
+      outstanding_requests               <= 0;
+      no_outstanding_requests_last_cycle <= 1'b0;
+    end else begin
+      if (outstanding_requests_inc && !outstanding_requests_dec) begin
+        outstanding_requests <= outstanding_requests + 1;
+      end else if (!outstanding_requests_inc && outstanding_requests_dec) begin
+        outstanding_requests <= outstanding_requests - 1;
+      end
+
+      no_outstanding_requests_last_cycle <= (outstanding_requests == 0) ||
+        ((outstanding_requests == 1) && outstanding_requests_dec);
+    end
+  end
+
+  assign outstanding_requests_o = outstanding_requests;
+  assign single_cycle_response_o = no_outstanding_requests_last_cycle & rvalid_i;
+endinterface
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv
index 0c024d82..4bd469eb 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv
@@ -178,7 +178,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #(
         // This coverpoint converts pmp_add_napot_valid into 32 bins. The onehot call makes sure
         // that when the entry is not in NAPOT mode, then no bin is selected. The clog2 call
         // converts the value 0...010...0 to the index of the one bit that is set.
-        cp_napot_addr_modes: coverpoint $clog2(pmp_addr_napot_valid[i_region])
+        cp_napot_addr_modes : coverpoint $clog2(pmp_addr_napot_valid[i_region])
           iff ($onehot(pmp_addr_napot_valid[i_region])) {
           bins napot_addr[] = { [0:31] };
         }
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f b/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f
index f6c54794..c8ec489e 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/ibex_dv.f
@@ -21,6 +21,8 @@
 ${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_pkg.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_assert.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_util_pkg.sv
+${LOWRISC_IP_DIR}/ip/prim/rtl/prim_count_pkg.sv
+${LOWRISC_IP_DIR}/ip/prim/rtl/prim_count.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_pkg.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_22_16_dec.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_22_16_enc.sv
@@ -32,6 +34,7 @@
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_hamming_39_32_enc.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_hamming_72_64_dec.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_hamming_72_64_enc.sv
+${LOWRISC_IP_DIR}/ip/prim/rtl/prim_mubi_pkg.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_ram_1p_pkg.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_ram_1p_adv.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_ram_1p_scr.sv
@@ -68,7 +71,6 @@
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_onehot_check.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_onehot_enc.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_onehot_mux.sv
-${LOWRISC_IP_DIR}/ip/prim/rtl/prim_mubi_pkg.sv
 
 // ibex CORE RTL files
 +incdir+${PRJ_DIR}/rtl
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv
index 23fbe8b6..244d80fa 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv
@@ -153,6 +153,13 @@ class ibex_asm_program_gen extends riscv_asm_program_gen;
 
     super.gen_init_section(hart);
 
+    // RISCV-DV assumes main is immediately after init when riscv_instr_pkg::support_pmp isn't set.
+    // This override of gen_init_section breaks that assumption so add a jump to main here so the
+    // test starts correctly for configurations that don't support PMP.
+    if (!riscv_instr_pkg::support_pmp) begin
+      instr_stream.push_back({indent, "j main"});
+    end
+
     gen_test_end(.result(TEST_PASS), .instr(instr));
     instr_stream = {instr_stream,
                     {format_string("test_done:", LABEL_STR_LEN)},
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_directed_instr_lib.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_directed_instr_lib.sv
index 607a62c2..36a13df4 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_directed_instr_lib.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/ibex_directed_instr_lib.sv
@@ -114,15 +114,15 @@ class ibex_rand_cpuctrlsts_stream extends riscv_directed_instr_stream;
     end
 
     // DIT is Data Independent Timing
-    if (!$value$plusargs("toggle_dit", toggle_dit)) begin
+    if (!$value$plusargs("toggle_dit=%d", toggle_dit)) begin
       toggle_dit = 1'b0;
     end
 
-    if (!$value$plusargs("toggle_dummy_instr", toggle_dummy_instr)) begin
+    if (!$value$plusargs("toggle_dummy_instr=%d", toggle_dummy_instr)) begin
       toggle_dummy_instr = 1'b0;
     end
 
-    if (!$value$plusargs("toggle_icache", toggle_icache)) begin
+    if (!$value$plusargs("toggle_icache=%d", toggle_icache)) begin
       toggle_icache = 1'b0;
     end
 
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
index 824ba7ff..8c651665 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
@@ -278,6 +278,20 @@
     compare_final_value_only: 1
     verbose: 1
 
+# TODO(#2233): Implement the following test (also note the priorities in the issue).
+#- test: riscv_debug_mode_pmp_test
+#  description: >
+#    When debug mode is enabled, any access to the Debug Module address space should be allowed.
+#    This holds regardless of PMP settings. Thus, this test performs a series of random accesses
+#    (reads, writes, and instruction fetch) in debug mode with a random PMP configuration, and it
+#    checks that all accesses to the Debug Module address space get allowed and that all accesses
+#    outside the Debug Module address space get allowed if and only if the PMP configuration permits
+#    them.
+#    When debug mode is not enabled, accesses to the Debug Module address space are governed by the
+#    PMP configuration. Verifying PMP is the focus of other tests. This test verifies a simple case:
+#    when debug mode is disabled and the PMP does not allow accesses to the Debug Module address
+#    space, a random access to that address space fails.
+
 - test: riscv_dret_test
   description: >
     Dret instructions will be inserted into generated code, ibex should treat these
@@ -677,13 +691,53 @@
   iterations: 15
   gen_test: riscv_rand_instr_test
   rtl_test: core_ibex_pc_intg_test
+  rtl_params:
+    SecureIbex: 1
 
 - test: riscv_rf_intg_test
   description: >
     Randomly corrupt the register file read port once in the middle of program execution
-  iterations: 15
+  iterations: 100
   gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +instr_cnt=10000
+    +num_of_sub_program=5
+    +gen_all_csrs_by_default=1
+    +add_csr_write=MSTATUS,MEPC,MCAUSE,MTVAL,0x7c0,0x7c1
+    +no_csr_instr=0
   rtl_test: core_ibex_rf_intg_test
+  rtl_params:
+    SecureIbex: 1
+
+- test: riscv_rf_ctrl_intg_test
+  description: >
+    Randomly corrupt one of the register file write and read enables signals in the middle of program execution
+  iterations: 15
+  gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +instr_cnt=10000
+    +num_of_sub_program=5
+    +gen_all_csrs_by_default=1
+    +add_csr_write=MSTATUS,MEPC,MCAUSE,MTVAL,0x7c0,0x7c1
+    +no_csr_instr=0
+  rtl_test: core_ibex_rf_ctrl_intg_test
+  rtl_params:
+    SecureIbex: 1
+
+- test: riscv_ram_intg_test
+  description: >
+    Randomly corrupt one of the RAM MUBI values in the middle of program execution
+  iterations: 15
+  gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +instr_cnt=10000
+    +num_of_sub_program=5
+    +gen_all_csrs_by_default=1
+    +add_csr_write=MSTATUS,MEPC,MCAUSE,MTVAL,0x7c0,0x7c1
+    +no_csr_instr=0
+  rtl_test: core_ibex_ram_intg_test
+  rtl_params:
+    SecureIbex: 1
 
 - test: riscv_icache_intg_test
   description: >
@@ -691,6 +745,8 @@
   iterations: 15
   gen_test: riscv_rand_instr_test
   rtl_test: core_ibex_icache_intg_test
+  rtl_params:
+    SecureIbex: 1
 
 - test: riscv_rv32im_instr_test
   description: >
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/collect_results.py b/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/collect_results.py
index 0c1b8fa6..151f6ae2 100755
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/collect_results.py
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/collect_results.py
@@ -18,7 +18,16 @@
 from report_lib.html import output_results_html
 from report_lib.junit_xml import output_run_results_junit_xml
 from report_lib.dvsim_json import output_results_dvsim_json
-from report_lib.svg import output_results_svg
+
+try:
+    # SVG requires python 3.7 and above, for environments that don't have python
+    # 3.7 (e.g. CentOS 7) detect failure to import and just skip any svg
+    # generation.
+    import svg
+    from report_lib.svg import output_results_svg
+    SVG_MODULE_PRESENT = True
+except ImportError:
+    SVG_MODULE_PRESENT = False
 
 def main() -> int:
     """Collect all test results into summary files.
@@ -93,10 +102,13 @@ def main() -> int:
             output_results_dvsim_json(md, test_summary_dict, cov_summary_dict,
                                       json_report_file)
 
-        svg_summary_filename = md.dir_run/'summary.svg'
-        with open(svg_summary_filename, 'w') as svg_summary_file:
-            output_results_svg(test_summary_dict, cov_summary_dict,
-                    svg_summary_file)
+        if SVG_MODULE_PRESENT:
+            svg_summary_filename = md.dir_run/'summary.svg'
+            with open(svg_summary_filename, 'w') as svg_summary_file:
+                output_results_svg(test_summary_dict, cov_summary_dict,
+                        svg_summary_file)
+        else:
+            print('WARNING: svg module not available, skipping SVG results output')
 
         # Print a summary line to the terminal
         print(gen_summary_line(passing_tests, failing_tests))
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/compile_tb.py b/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/compile_tb.py
index 6ea6be32..2adcfa4a 100755
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/compile_tb.py
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/compile_tb.py
@@ -5,7 +5,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 import argparse
+from typing import List
 import os
+import shlex
 import sys
 import subprocess
 import pathlib3x as pathlib
@@ -19,20 +21,51 @@
 logger = logging.getLogger(__name__)
 
 
-def _get_iss_pkgconfig_flags(specifiers, iss_pc, simulator):
-    _flags = subprocess.check_output(
-        args=(['pkg-config'] + specifiers + iss_pc),
-        universal_newlines=True,
-        ).strip()
-    if simulator == 'xlm':
-        # See xcelium documentation for the -Wld syntax for passing
-        # flags to the linker. Passing -rpath,<path> options is tricky
-        # because commas are parsed strangely between xrun and the xmsc
-        # tool, and its easy for the options to arrive malformed. Use
-        # the following hack to get it through.
-        if '-Wl' in _flags:  # This should be in LDFLAGS only
-            _flags = "'-Xlinker {}'".format(_flags.replace('-Wl,', ''))
-    return _flags
+def _get_iss_pkgconfig_flags(specifiers: List[str], iss_pc: List[str], simulator: str) -> str:
+    all_tokens = []
+
+    # Seperate pkg-config calls for each specifier as combining them has been
+    # observed misbehaving on CentOS 7
+    # Generate a list of tokens for each call, and append it to the all_tokens variable
+    for s in specifiers:
+        cmd = ['pkg-config', s] + iss_pc
+        stdout = subprocess.check_output(cmd, universal_newlines=True).strip()
+        tokens = shlex.split(stdout)
+        logger.debug(f"pkgconfig_tokens = {tokens}")
+
+        rpath_prefix = '-Wl,-rpath,'
+        def fixup_xcelium_rpath_token(t: str) -> str:
+            """Re-format rpath flags to ensure reliable passing to Xcelium.
+
+            When passing rpath flags to xcelium through the xrun tool, we need to re-format the string
+            output from pkg-config to ensure reliability.
+            This routine detects rpath flags and reformats them according to the Cadence support site
+            article.
+            """
+            if simulator == 'xlm' and t.startswith(rpath_prefix):
+                logger.debug(f"rpath token => {t}")
+                # https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000sdF8EAI
+                # See xcelium documentation for the -Wld syntax for passing
+                # user specified arguments to the C++ linker.
+                # Passing -rpath,<path> options is tricky, so use the following workaround as
+                # suggested in the support article.
+                # INPUT:  '-Wl,-rpath,/opt/spike/lib'
+                # OUTPUT: '-Wld,-Xlinker,-rpath,-Xlinker,/opt/spike/lib',
+                rpaths = (t[len(rpath_prefix):]).split(',')
+                xlinker_rpaths_str = ','.join((f"-Xlinker,{p}" for p in rpaths))
+                rpath_token = f"-Wld,-Xlinker,-rpath,{xlinker_rpaths_str}"
+                logger.debug(f"new rpath token => {rpath_token}")
+                return rpath_token
+            else:
+                return t
+
+        tokens = map(fixup_xcelium_rpath_token, tokens)
+
+        all_tokens += tokens
+
+    flags_str = shlex.join(all_tokens)
+    logger.debug(f"flags = {flags_str}")
+    return flags_str
 
 
 def _main() -> int:
@@ -52,6 +85,31 @@ def _main() -> int:
         md.dir_tb.mkdir(exist_ok=True, parents=True)
         md.tb_build_log = md.dir_tb/'compile_tb.log'
 
+        # Locate the spike .pc files to allow us to link against it when
+        # building, riscv-fesvr isn't strictly required but the DV flow has been
+        # observed to see build failures where it isn't present with CentOS 7.
+        spike_iss_pc = ['riscv-riscv', 'riscv-disasm', 'riscv-fdt',
+            'riscv-fesvr']
+        try:
+            subprocess.check_output(['pkg-config', '--exists'] + spike_iss_pc)
+        except subprocess.CalledProcessError as err:
+            raise RuntimeError(
+                f'Failed to find {spike_iss_pc} pkg-config packages. '
+                f'Did you set the PKG_CONFIG_PATH correctly?') from err
+
+        # Now call out to pkg-config to return the appropriate flags for compilation
+        # (The keys here are the substitution placeholders in rtl_simulation.yaml)
+        iss_pkgconfig_dict = {
+            'ISS_CFLAGS'  : ['--cflags'],
+            'ISS_LDFLAGS' : ['--libs-only-other'],
+            'ISS_LIBS'    : ['--libs-only-l', '--libs-only-L'],
+        }
+        iss_cc_subst_vars_dict = \
+            {k: _get_iss_pkgconfig_flags(v, spike_iss_pc, md.simulator)
+             for k, v in iss_pkgconfig_dict.items()}
+
+        # Populate the entire set of variables to substitute in the templated
+        # compilation command, including the compiler flags for the ISS.
         subst_vars_dict = {
             'core_ibex': md.ibex_dv_root,
             'tb_dir': md.dir_tb,
@@ -62,26 +120,7 @@ def _main() -> int:
             'xlm_cov_cfg_file': f"{md.ot_xcelium_cov_scripts}/cover.ccf",
             'dut_cov_rtl_path': md.dut_cov_rtl_path
         }
-
-        # Locate the spike .pc files to allow us to link against it when building
-        spike_iss_pc = ['riscv-riscv', 'riscv-disasm', 'riscv-fdt']
-        iss_pkgconfig_dict = {
-            'ISS_CFLAGS'  : ['--cflags'],
-            'ISS_LDFLAGS' : ['--libs-only-other'],
-            'ISS_LIBS'    : ['--libs-only-l', '--libs-only-L'],
-        }
-        md.envvar_PKG_CONFIG_PATH = dict(os.environ).get('PKG_CONFIG_PATH')
-        try:
-            subprocess.check_output(['pkg-config', '--exists'] + spike_iss_pc)
-        except subprocess.CalledProcessError as err:
-            raise RuntimeError(
-                f'Failed to find {spike_iss_pc} pkg-config packages. '
-                f'Did you set the PKG_CONFIG_PATH correctly?') from err
-        subst_vars_dict.update(
-            {k: _get_iss_pkgconfig_flags(v,
-                                         spike_iss_pc,
-                                         md.simulator)
-             for k, v in iss_pkgconfig_dict.items()})
+        subst_vars_dict.update(iss_cc_subst_vars_dict)
 
         md.tb_build_stdout = md.dir_tb/'compile_tb_stdstreams.log'
         md.tb_build_cmds = riscvdv_interface.get_tool_cmds(
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/merge_cov.py b/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/merge_cov.py
index 35e26fed..a9a84e7a 100755
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/merge_cov.py
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/merge_cov.py
@@ -39,16 +39,22 @@ def find_cov_dbs(start_dir: pathlib.Path, simulator: str) -> Set[pathlib.Path]:
 
 
 def merge_cov_vcs(md: RegressionMetadata, cov_dirs: Set[pathlib.Path]) -> int:
-    logging.info("Generating merged coverage directory")
     cmd = (['urg', '-full64',
             '-format', 'both',
-            '-dbname', str(md.cov_dir/'merged.vdb'),
-            '-report', str(md.cov_dir/'report'),
-            '-log', str(md.cov_dir/'merge.log'),
+            '-dbname', str(md.dir_cov/'merged.vdb'),
+            '-report', str(md.dir_cov/'report'),
+            '-log', str(md.dir_cov/'merge.log'),
             '-dir'] +
-           list(cov_dirs))
-    return run_one(md.verbose, cmd, redirect_stdstreams='/dev/null')
+           [str(cov_dir) for cov_dir in list(cov_dirs)])
 
+    with LockedMetadata(md.dir_metadata, __file__) as md:
+        md.cov_merge_log = md.dir_cov / 'merge.log'
+        md.cov_merge_stdout = md.dir_cov / 'merge.log.stdout'
+        md.cov_merge_cmds = [cmd]
+
+    with open(md.cov_merge_stdout, 'wb') as fd:
+        logging.info("Generating merged coverage directory")
+        return run_one(md.verbose, cmd, redirect_stdstreams=fd)
 
 def merge_cov_xlm(md: RegressionMetadata, cov_dbs: Set[pathlib.Path]) -> int:
     """Merge xcelium-generated coverage using the OT scripts.
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/report_lib/util.py b/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/report_lib/util.py
index f6a00756..55cb1d74 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/report_lib/util.py
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/report_lib/util.py
@@ -38,10 +38,12 @@ def gen_test_run_result_text(trr: TestRunResult) -> str:
     test_underline = '-' * len(test_name_idx)
     info_lines: List[str] = [test_name_idx, test_underline]
 
-    #  Filter out relevant fields, and print as relative to the dir_test for readability
-    lesskeys = {k: str(v.relative_to(trr.dir_test))  # Improve readability
-                for k, v in dataclasses.asdict(trr).items()
-                if k in ['binary', 'rtl_log', 'rtl_trace', 'iss_cosim_trace']}
+    # Filter out relevant fields, and print as relative to the dir_test for
+    # readability.
+    lesskeys = \
+            {k: str(v.relative_to(trr.dir_test) if v is not None else 'MISSING')
+             for k, v in dataclasses.asdict(trr).items()
+             if k in ['binary', 'rtl_log', 'rtl_trace', 'iss_cosim_trace']}
     strdict = ibex_lib.format_dict_to_printable_dict(lesskeys)
 
     trr_yaml = io.StringIO()
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/run_rtl.py b/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/run_rtl.py
index 8334a941..cc5d9de3 100755
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/run_rtl.py
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/scripts/run_rtl.py
@@ -67,6 +67,7 @@ def _main() -> int:
         'rtl_sim_log': trr.rtl_log,
         'rtl_trace': trr.rtl_trace.parent/'trace_core',
         'iss_cosim_trace': trr.iss_cosim_trace,
+        'core_ibex': md.ibex_dv_root,
         'sim_opts': (f"+signature_addr={md.signature_addr}\n" +
                      f"+test_timeout_s={trr.timeout_s}\n" +
                      f"{get_sim_opts(md.ibex_config, md.simulator)}\n" +
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
index 4e758489..5ca14c06 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
@@ -84,6 +84,8 @@ module core_ibex_tb_top;
   assign {scramble_key, scramble_nonce} = scrambling_key_if.d_data;
 
   ibex_top_tracing #(
+    .DmBaseAddr       (32'h`BOOT_ADDR       ),
+    .DmAddrMask       (32'h0000_0007        ),
     .DmHaltAddr       (32'h`BOOT_ADDR + 'h0 ),
     .DmExceptionAddr  (32'h`BOOT_ADDR + 'h4 ),
     .PMPEnable        (PMPEnable        ),
@@ -157,10 +159,29 @@ module core_ibex_tb_top;
     .core_sleep_o           (dut_if.core_sleep          )
   );
 
+  `define IBEX_RF_PATH core_ibex_tb_top.dut.u_ibex_top.gen_regfile_ff.register_file_i
+
   // We should never see any alerts triggered in normal testing
   `ASSERT(NoAlertsTriggered,
     !dut_if.alert_minor && !dut_if.alert_major_internal && !dut_if.alert_major_bus, clk, !rst_n)
   `DV_ASSERT_CTRL("tb_no_alerts_triggered", core_ibex_tb_top.NoAlertsTriggered)
+  `DV_ASSERT_CTRL("tb_rf_rd_mux_a_onehot",
+    `IBEX_RF_PATH.gen_rdata_mux_check.u_rdata_a_mux.SelIsOnehot_A)
+  `DV_ASSERT_CTRL("tb_rf_rd_mux_b_onehot",
+    `IBEX_RF_PATH.gen_rdata_mux_check.u_rdata_b_mux.SelIsOnehot_A)
+
+  `DV_ASSERT_CTRL("tb_no_spurious_response",
+    core_ibex_tb_top.dut.u_ibex_top.u_ibex_core.NoMemResponseWithoutPendingAccess)
+  `DV_ASSERT_CTRL("tb_no_spurious_response",
+    core_ibex_tb_top.dut.u_ibex_top.MaxOutstandingDSideAccessesCorrect)
+  `DV_ASSERT_CTRL("tb_no_spurious_response",
+    core_ibex_tb_top.dut.u_ibex_top.PendingAccessTrackingCorrect)
+
+  if (SecureIbex) begin : g_lockstep_assert_ctrl
+    `define IBEX_LOCKSTEP_PATH core_ibex_tb_top.dut.u_ibex_top.gen_lockstep.u_ibex_lockstep
+    `DV_ASSERT_CTRL("tb_no_spurious_response",
+      `IBEX_LOCKSTEP_PATH.u_shadow_core.NoMemResponseWithoutPendingAccess)
+  end
 
   assign dut.u_ibex_top.u_ibex_core.u_fcov_bind.rf_we_glitch_err =
     dut.u_ibex_top.rf_alert_major_internal;
@@ -196,7 +217,8 @@ module core_ibex_tb_top;
   assign rvfi_if.mem_rmask            = dut.rvfi_mem_rmask;
   assign rvfi_if.mem_rdata            = dut.rvfi_mem_rdata;
   assign rvfi_if.mem_wdata            = dut.rvfi_mem_wdata;
-  assign rvfi_if.ext_mip              = dut.rvfi_ext_mip;
+  assign rvfi_if.ext_pre_mip          = dut.rvfi_ext_pre_mip;
+  assign rvfi_if.ext_post_mip         = dut.rvfi_ext_post_mip;
   assign rvfi_if.ext_nmi              = dut.rvfi_ext_nmi;
   assign rvfi_if.ext_nmi_int          = dut.rvfi_ext_nmi_int;
   assign rvfi_if.ext_debug_req        = dut.rvfi_ext_debug_req;
@@ -230,6 +252,7 @@ module core_ibex_tb_top;
   assign dut_if.rf_ren_b         = dut.u_ibex_top.u_ibex_core.rf_ren_b;
   assign dut_if.rf_rd_a_wb_match = dut.u_ibex_top.u_ibex_core.rf_rd_a_wb_match;
   assign dut_if.rf_rd_b_wb_match = dut.u_ibex_top.u_ibex_core.rf_rd_b_wb_match;
+  assign dut_if.rf_write_wb      = dut.u_ibex_top.u_ibex_core.rf_write_wb;
   assign dut_if.sync_exc_seen    = dut.u_ibex_top.u_ibex_core.cs_registers_i.cpuctrlsts_part_q.sync_exc_seen;
   assign dut_if.csr_save_cause   = dut.u_ibex_top.u_ibex_core.csr_save_cause;
   assign dut_if.exc_cause        = dut.u_ibex_top.u_ibex_core.exc_cause;
@@ -286,6 +309,13 @@ module core_ibex_tb_top;
   assign data_mem_vif.misaligned_second =
     dut.u_ibex_top.u_ibex_core.load_store_unit_i.addr_incr_req_o;
 
+  assign data_mem_vif.misaligned_first_saw_error =
+    dut.u_ibex_top.u_ibex_core.load_store_unit_i.addr_incr_req_o &
+    dut.u_ibex_top.u_ibex_core.load_store_unit_i.lsu_err_d;
+
+  assign data_mem_vif.m_mode_access =
+    dut.u_ibex_top.u_ibex_core.priv_mode_lsu == ibex_pkg::PRIV_LVL_M;
+
   initial begin
     // Drive the clock and reset lines. Reset everything and start the clock at the beginning of
     // time
@@ -331,6 +361,13 @@ module core_ibex_tb_top;
     run_test();
   end
 
+  // Manually set unused_assert_connected = 1 to disable the AssertConnected_A assertion for
+  // prim_count in case lockstep (set by SecureIbex) is enabled. If not disabled, DV fails.
+  if (SecureIbex) begin : gen_disable_count_check
+    assign dut.u_ibex_top.gen_lockstep.u_ibex_lockstep.u_rst_shadow_cnt.
+          unused_assert_connected = 1;
+  end
+
   // Disable the assertion for onhot check in case WrenCheck (set by SecureIbex) is enabled.
   if (SecureIbex) begin : gen_disable_onehot_check
     assign dut.u_ibex_top.gen_regfile_ff.register_file_i.gen_wren_check.u_prim_onehot_check.
@@ -344,4 +381,32 @@ module core_ibex_tb_top;
     assign dut.u_ibex_top.gen_regfile_ff.register_file_i.gen_rdata_mux_check.
           u_prim_onehot_check_raddr_b.unused_assert_connected = 1;
   end
+
+  ibex_pkg::ctrl_fsm_e controller_state;
+  logic                controller_handle_irq;
+  ibex_pkg::irqs_t     ibex_irqs, last_ibex_irqs;
+
+  assign controller_state      = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.ctrl_fsm_cs;
+  assign controller_handle_irq = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.handle_irq;
+  assign ibex_irqs             = dut.u_ibex_top.u_ibex_core.irqs;
+
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      last_ibex_irqs <= '0;
+    end else begin
+      last_ibex_irqs <= ibex_irqs;
+    end
+  end
+
+  always_ff @(posedge clk) begin
+    if (controller_state == ibex_pkg::IRQ_TAKEN) begin
+      if (!controller_handle_irq) begin
+        $display("WARNING: Controller in IRQ_TAKEN but no IRQ to handle, returning to DECODE");
+        $display("IRQs last cycle: %x, IRQs this cycle: %x", last_ibex_irqs, ibex_irqs);
+      end else if (last_ibex_irqs != ibex_irqs) begin
+        $display("WARNING: Controller in IRQ_TAKEN and IRQs have just changed");
+        $display("IRQs last cycle: %x, IRQs this cycle: %x", last_ibex_irqs, ibex_irqs);
+      end
+    end
+  end
 endmodule
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv
index 5fe4a23c..d9fc99f9 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_base_test.sv
@@ -90,6 +90,7 @@ class core_ibex_base_test extends uvm_test;
     bit [31:0] mhpm_counter_num;
     bit        secure_ibex;
     bit        icache;
+    bit        disable_spurious_dside_responses;
 
     super.build_phase(phase);
     $value$plusargs("timeout_in_cycles=%0d", timeout_in_cycles);
@@ -165,6 +166,16 @@ class core_ibex_base_test extends uvm_test;
 
     uvm_config_db#(core_ibex_env_cfg)::set(this, "*", "cfg", cfg);
     mem = mem_model_pkg::mem_model#()::type_id::create("mem");
+
+    disable_spurious_dside_responses = 0;
+    void'($value$plusargs("disable_spurious_dside_responses=%0d",
+      disable_spurious_dside_responses));
+
+    // Disable spurious reponses for non secure configs or when disabled through plusarg
+    if ((secure_ibex == 0) || disable_spurious_dside_responses) begin
+      cfg.enable_spurious_dside_responses = 0;
+    end
+
     // Create virtual sequence and assign memory handle
     vseq = core_ibex_vseq::type_id::create("vseq");
     vseq.mem = mem;
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
index 40a17f30..bf4181af 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
@@ -129,7 +129,8 @@ class core_ibex_rf_intg_test extends core_ibex_base_test;
   endfunction
 
   virtual task send_stimulus();
-    bit port_idx;
+    int    rnd_delay;
+    bit    port_idx;
     string port_name;
 
     vseq.start(env.vseqr);
@@ -138,14 +139,19 @@ class core_ibex_rf_intg_test extends core_ibex_base_test;
     port_idx = $urandom_range(1);
     port_name = port_idx ? "rf_rdata_b_ecc" : "rf_rdata_a_ecc";
 
+    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(rnd_delay, rnd_delay > 1000; rnd_delay < 10_000;)
+    clk_vif.wait_n_clks(rnd_delay);
+
     forever begin
-      logic rf_ren, rf_rd_wb_match;
+      logic rf_ren, rf_rd_wb_match, rf_write_wb;
       int unsigned bit_idx;
       uvm_hdl_data_t data, mask;
       logic exp_alert, alert_major_internal;
 
       clk_vif.wait_n_clks(1);
 
+      rf_write_wb = dut_vif.signal_probe_rf_write_wb(dv_utils_pkg::SignalProbeSample);
+
       // Check if port is being read.
       if (port_idx) begin
         rf_ren = dut_vif.signal_probe_rf_ren_b(dv_utils_pkg::SignalProbeSample);
@@ -156,7 +162,7 @@ class core_ibex_rf_intg_test extends core_ibex_base_test;
       end
 
       // Only corrupt port if it is read.
-      if (!(rf_ren == 1'b1 && rf_rd_wb_match == 1'b0)) continue;
+      if (!(rf_ren == 1'b1 && (rf_rd_wb_match == 1'b0 || rf_write_wb == 1'b0))) continue;
 
       data = read_data(port_name);
       `uvm_info(`gfn, $sformatf("Corrupting %s; original value: 'h%0x", port_name, data), UVM_LOW)
@@ -199,6 +205,195 @@ class core_ibex_rf_intg_test extends core_ibex_base_test;
 
 endclass
 
+class core_ibex_rf_ctrl_intg_test extends core_ibex_base_test;
+  `uvm_component_utils(core_ibex_rf_ctrl_intg_test)
+  `uvm_component_new
+
+  uvm_report_server rs;
+
+  virtual task send_stimulus();
+    int          rnd_delay;
+    int unsigned bit_idx;
+    logic [31:0] orig_val, glitch_val;
+    logic        alert_major_internal;
+    string       glitch_path, alert_major_internal_path;
+    string       ctrl_signals[];
+    int unsigned ctrl_signal_idx;
+    string       top_path = "core_ibex_tb_top.dut.u_ibex_top";
+    string       ibex_rf_path = {top_path, ".gen_regfile_ff.register_file_i"};
+
+    ctrl_signals = {
+      "we_a_dec",
+      "gen_rdata_mux_check.raddr_onehot_a",
+      "gen_rdata_mux_check.raddr_onehot_b"
+    };
+
+    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(ctrl_signal_idx, ctrl_signal_idx < ctrl_signals.size();)
+    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(rnd_delay, rnd_delay > 1000; rnd_delay < 10_000;)
+
+    glitch_path = $sformatf("%s.%s", ibex_rf_path, ctrl_signals[ctrl_signal_idx]);
+
+    vseq.start(env.vseqr);
+    clk_vif.wait_n_clks(rnd_delay);
+
+    `uvm_info(`gfn, $sformatf("Reading value of %s", glitch_path), UVM_LOW)
+    `DV_CHECK_FATAL(uvm_hdl_read(glitch_path, orig_val));
+    `uvm_info(`gfn, $sformatf("Read %x", orig_val), UVM_LOW)
+
+    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(bit_idx, bit_idx < 32;)
+
+    glitch_val = orig_val;
+    glitch_val[bit_idx] = ~glitch_val[bit_idx];
+
+    // Disable TB assertion for alerts.
+    `DV_ASSERT_CTRL_REQ("tb_no_alerts_triggered", 1'b0)
+    // Disable one-hot check assertions for RF muxes
+    `DV_ASSERT_CTRL_REQ("tb_rf_rd_mux_a_onehot", 1'b0)
+    `DV_ASSERT_CTRL_REQ("tb_rf_rd_mux_b_onehot", 1'b0)
+
+    `uvm_info(`gfn, $sformatf("Forcing %s to value 'h%0x", glitch_path, glitch_val), UVM_LOW)
+    `DV_CHECK_FATAL(uvm_hdl_force(glitch_path, glitch_val));
+
+    // Leave glitch applied for one clock cycle.
+    clk_vif.wait_n_clks(1);
+
+    // Check that the alert matches our expectation.
+    alert_major_internal_path = $sformatf("%s.alert_major_internal_o", top_path);
+    `DV_CHECK_FATAL(uvm_hdl_read(alert_major_internal_path, alert_major_internal))
+    `DV_CHECK_FATAL(alert_major_internal, "Major alert did not fire!")
+
+    // Release glitch.
+    `DV_CHECK_FATAL(uvm_hdl_release(glitch_path))
+    `uvm_info(`gfn, $sformatf("Releasing force of %s", glitch_path), UVM_LOW)
+
+    // Re-enable TB assertion for alerts.
+    `DV_ASSERT_CTRL_REQ("tb_no_alerts_triggered", 1'b1)
+
+    // Complete the test at this point because cosimulation does not model faults so will cause
+    // a mis-match and a test failure.
+    rs = uvm_report_server::get_server();
+    rs.report_summarize();
+    $finish();
+  endtask
+endclass
+
+class core_ibex_ram_intg_test extends core_ibex_base_test;
+  `uvm_component_utils(core_ibex_ram_intg_test)
+  `uvm_component_new
+
+  uvm_report_server rs;
+
+  virtual task send_stimulus();
+    int          rnd_delay;
+    int unsigned bit_idx;
+    logic [31:0] orig_val, glitch_val;
+    logic        alert_major_internal;
+    string       glitch_path, alert_major_internal_path;
+    string       glitch_paths[];
+    string       signals[];
+    string       scr_signals[];
+    int unsigned scr_signals_idx;
+    string       adv_signals[];
+    int unsigned adv_signals_idx;
+    string       ram_path;
+    int unsigned bank_idx, ram_idx, glitch_idx;
+    string       top_path = "core_ibex_tb_top.dut.u_ibex_top";
+    string       bank_paths[];
+
+    // Hard coded paths for the data and tag bank.
+    bank_paths = {
+      "gen_rams.gen_rams_inner[0].gen_scramble_rams.tag_bank",
+      "gen_rams.gen_rams_inner[1].gen_scramble_rams.tag_bank",
+      "gen_rams.gen_rams_inner[0].gen_scramble_rams.data_bank",
+      "gen_rams.gen_rams_inner[1].gen_scramble_rams.data_bank"
+    };
+
+    // All banks contain a single prim_ram_1p_adv instance.
+    ram_path = "u_prim_ram_1p_adv";
+
+    scr_signals = {
+      "write_en_d",
+      "write_en_q",
+      "addr_collision_d",
+      "addr_collision_q",
+      "write_scr_pending_d",
+      "write_pending_q",
+      "rvalid_q",
+      "read_en_buf"
+    };
+
+    adv_signals = {
+      "req_q",
+      "req_d",
+      "write_q",
+      "write_d",
+      "rvalid_q",
+      "rvalid_d",
+      "rvalid_sram_q",
+      "rvalid_sram_d"
+    };
+
+    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(scr_signals_idx, scr_signals_idx < scr_signals.size();)
+    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(adv_signals_idx, adv_signals_idx < adv_signals.size();)
+    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(bank_idx, bank_idx < bank_paths.size();)
+    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(rnd_delay, rnd_delay > 1000; rnd_delay < 10_000;)
+
+    signals = {
+      scr_signals[scr_signals_idx],
+      adv_signals[adv_signals_idx]
+    };
+
+    // Assemble paths and do the final muxing of the target glitch path below.
+    glitch_paths = {
+      $sformatf("%s.%s.%s", top_path, bank_paths[bank_idx], signals[0]),
+      $sformatf("%s.%s.%s.%s", top_path, bank_paths[bank_idx], ram_path, signals[1])
+    };
+
+    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(glitch_idx, glitch_idx < glitch_paths.size();)
+
+    glitch_path = glitch_paths[glitch_idx];
+
+    vseq.start(env.vseqr);
+    clk_vif.wait_n_clks(rnd_delay);
+
+    `uvm_info(`gfn, $sformatf("Reading value of %s", glitch_path), UVM_LOW)
+    `DV_CHECK_FATAL(uvm_hdl_read(glitch_path, orig_val));
+    `uvm_info(`gfn, $sformatf("Read %x", orig_val), UVM_LOW)
+
+    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(bit_idx, bit_idx < 4;)
+
+    glitch_val = orig_val;
+    glitch_val ^= 1 << bit_idx;
+
+    // Disable TB assertion for alerts.
+    `DV_ASSERT_CTRL_REQ("tb_no_alerts_triggered", 1'b0)
+
+    `uvm_info(`gfn, $sformatf("Forcing %s to value 'h%0x", glitch_path, glitch_val), UVM_LOW)
+    `DV_CHECK_FATAL(uvm_hdl_force(glitch_path, glitch_val));
+
+    // Leave glitch applied for one clock cycle.
+    clk_vif.wait_n_clks(1);
+
+    // Check that the alert matches our expectation.
+    alert_major_internal_path = $sformatf("%s.alert_major_internal_o", top_path);
+    `DV_CHECK_FATAL(uvm_hdl_read(alert_major_internal_path, alert_major_internal))
+    `DV_CHECK_FATAL(alert_major_internal, "Major alert did not fire!")
+
+    // Release glitch.
+    `DV_CHECK_FATAL(uvm_hdl_release(glitch_path))
+    `uvm_info(`gfn, $sformatf("Releasing force of %s", glitch_path), UVM_LOW)
+
+    // Re-enable TB assertion for alerts.
+    `DV_ASSERT_CTRL_REQ("tb_no_alerts_triggered", 1'b1)
+
+    // Complete the test at this point because cosimulation does not model faults so will cause
+    // a mis-match and a test failure.
+    rs = uvm_report_server::get_server();
+    rs.report_summarize();
+    $finish();
+  endtask
+endclass
+
 // Test that corrupts the instruction cache and checks that an appropriate alert occurs.
 class core_ibex_icache_intg_test extends core_ibex_base_test;
 
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_vseq.sv b/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_vseq.sv
index cfb156d3..0e54aa1c 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_vseq.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/tests/core_ibex_vseq.sv
@@ -34,7 +34,27 @@ class core_ibex_vseq extends uvm_sequence;
   // Start the memory-model sequences, which run forever() loops to respond to bus events
   virtual task pre_body();
     instr_intf_seq.m_mem = mem;
+    instr_intf_seq.enable_spurious_response = 1'b0;
+
     data_intf_seq.m_mem  = mem;
+    if (cfg.enable_spurious_dside_responses) begin
+      bit enable_spurious_response;
+
+      `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(enable_spurious_response,
+        enable_spurious_response dist {1 :/ cfg.spurious_response_pct,
+                                       0 :/ 100 - cfg.spurious_response_pct};)
+
+      data_intf_seq.enable_spurious_response = enable_spurious_response;
+
+      if (enable_spurious_response) begin
+        `uvm_info(`gfn, "Enabling spurious responses for this test", UVM_LOW)
+        // Disable protocol checking assertions that will fire when we see a spurious response
+        `DV_ASSERT_CTRL_REQ("tb_no_spurious_response", 1'b0)
+      end
+    end else begin
+      data_intf_seq.enable_spurious_response = 1'b0;
+    end
+
     fork
       instr_intf_seq.start(p_sequencer.instr_if_seqr);
       data_intf_seq.start(p_sequencer.data_if_seqr);
diff --git a/vendor/lowrisc_ibex/dv/uvm/core_ibex/yaml/rtl_simulation.yaml b/vendor/lowrisc_ibex/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
index a973e7ad..965ad333 100644
--- a/vendor/lowrisc_ibex/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
+++ b/vendor/lowrisc_ibex/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
@@ -18,7 +18,7 @@
 # As a result, passing -fno-extended-identifiers tells G++ to pretend that
 # everything is ASCII, preventing strange compilation errors.
 - tool: vcs
-  env_var: IBEX_ROOT
+  env_var: IBEX_ROOT, EXTRA_COSIM_CFLAGS
   compile:
     cmd:
       - >-
@@ -39,6 +39,7 @@
           -xlrm uniq_prior_final
           -CFLAGS '--std=c99 -fno-extended-identifiers'
           -lca -kdb
+          -debug_access+f
           <cmp_opts> <wave_opts> <cov_opts> <cosim_opts>
     cov_opts: >-
       -cm line+tgl+assert+fsm+branch
@@ -51,11 +52,10 @@
     wave_opts: >-
       -debug_access+all
       -ucli
-      -do vcs.tcl
     cosim_opts: >-
       -f <core_ibex>/ibex_dv_cosim_dpi.f
       -LDFLAGS '<ISS_LDFLAGS>'
-      -CFLAGS '<ISS_CFLAGS>'
+      -CFLAGS '<ISS_CFLAGS> <EXTRA_COSIM_CFLAGS>'
       -CFLAGS '-I<IBEX_ROOT>/dv/cosim'
       <ISS_LIBS>
       -lstdc++
@@ -71,6 +71,7 @@
             +bin=<binary>
             +ibex_tracer_file_base=<rtl_trace>
             +cosim_log_file=<iss_cosim_trace>
+            -l <rtl_sim_log>
             <sim_opts> <wave_opts> <cov_opts>
     cov_opts: >
       -cm line+tgl+assert+fsm+branch
@@ -81,7 +82,7 @@
       +enable_ibex_fcov=1
     wave_opts: >
       -ucli
-      -do <cwd>/vcs.tcl
+      -do <core_ibex>/vcs.tcl
 
 
 ############################################################
@@ -99,9 +100,9 @@
           -mfcu -cuname design_cuname
           +define+UVM_REGEX_NO_DPI
           +define+UVM
-          -timescale \"1 ns / 1 ps \"
+          -timescale 1ns/1ps
           -writetoplevels <tb_dir>/top.list
-          -l <tb_dir>/<rtl_log>
+          -l <tb_build_log>
           <cmp_opts>
   sim:
     cmd:
@@ -118,7 +119,7 @@
           +UVM_VERBOSITY=UVM_LOW
           +bin=<binary>
           +ibex_tracer_file_base=<rtl_trace>
-          -l <test_dir>/sim.log
+          -l <rtl_sim_log>
           <cov_opts>
     cov_opts: >-
       -do "coverage save -onexit <tb_dir>/cov.ucdb;"
@@ -224,7 +225,7 @@
 
 ############################################################
 - tool: xlm
-  env_var: dv_root, DUT_TOP, IBEX_ROOT
+  env_var: dv_root, DUT_TOP, IBEX_ROOT, EXTRA_COSIM_CFLAGS
   compile:
     cmd:
       - >-
@@ -254,7 +255,8 @@
       -I<IBEX_ROOT>/dv/cosim
       <ISS_LIBS>
       <ISS_CFLAGS>
-      -Wld,<ISS_LDFLAGS>
+      <EXTRA_COSIM_CFLAGS>
+      <ISS_LDFLAGS>
       -lstdc++
   sim:
     cmd:
diff --git a/vendor/lowrisc_ibex/dv/uvm/icache/doc/ibex_icache_dv_plan.md b/vendor/lowrisc_ibex/dv/uvm/icache/doc/ibex_icache_dv_plan.md
index 865268ff..cd112ef8 100644
--- a/vendor/lowrisc_ibex/dv/uvm/icache/doc/ibex_icache_dv_plan.md
+++ b/vendor/lowrisc_ibex/dv/uvm/icache/doc/ibex_icache_dv_plan.md
@@ -11,12 +11,12 @@ title: "Ibex ICache DV Plan"
 
 ## Current status
 
-* Design & verification stage (TODO: Create HW dashboard & add link) (see [HW development stages](https://docs.opentitan.org/doc/project/hw_stages) for what this means)
+* Design & verification stage (TODO: Create HW dashboard & add link) (see [HW development stages](https://opentitan.org/book/doc/project_governance/development_stages.html) for what this means)
 * Simulation results (TODO: Generate nightly simulation results & add link)
 
 ## Design features
 
-The ICache design is documented in the [Instruction Cache](https://ibex-core.readthedocs.io/en/latest/icache.html) section of the Ibex User Manual.
+The ICache design is documented in the [Instruction Cache](https://ibex-core.readthedocs.io/en/latest/03_reference/icache.html) section of the Ibex User Manual.
 
 ## Testbench architecture
 
@@ -155,7 +155,7 @@ Coverpoints will be created at two levels, ICache top level and individual fill
   * `FBAwaitingOutput` - Waiting for fill buffer data to be consumed by output before releasing
 * `cp_fb_done_reason` - Why the fill buffer has finished
   * `FBNotDone` - Fill buffer not yet done
-  * `FBDoneHitNoExtReqs` - Fill buffer hit against cache and sent no external requests 
+  * `FBDoneHitNoExtReqs` - Fill buffer hit against cache and sent no external requests
   * `FBDoneHitExtReqs` - Fill buffer hit against cache and sent external requests (which must be completed before fill buffer can release)
   * `FBDoneMiss` - Fill buffer missed in cache and has fetched data to satisfy request
   * `FBDoneBranchNoExtReqs` - Fill buffer became stale due to branch and sent no external requests and so released
diff --git a/vendor/lowrisc_ibex/dv/uvm/icache/dv/fcov/ibex_icache_fcov_if.sv b/vendor/lowrisc_ibex/dv/uvm/icache/dv/fcov/ibex_icache_fcov_if.sv
index 2cdb23b4..aa01b7be 100644
--- a/vendor/lowrisc_ibex/dv/uvm/icache/dv/fcov/ibex_icache_fcov_if.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/icache/dv/fcov/ibex_icache_fcov_if.sv
@@ -1,3 +1,7 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
 interface ibex_icache_fcov_if import ibex_pkg::*; #(
   parameter int NUM_FB = 4
 ) (
@@ -261,10 +265,10 @@ interface ibex_icache_fcov_if import ibex_pkg::*; #(
       }
       cp_state: coverpoint fill_buffer_state;
       cp_fill_buffer_done_reason : coverpoint fill_buffer_done_reason;
-      cp_state_when_disabling: coverpoint fill_buffer_state iff icache_just_disabled;
-      cp_state_when_enabling: coverpoint fill_buffer_state iff icache_just_enabled;
-      cp_state_when_inval_start: coverpoint fill_buffer_state iff icache_inval_start;
-      cp_starting_beat: coverpoint starting_beat iff fill_alloc[i_fb];
+      cp_state_when_disabling: coverpoint fill_buffer_state iff (icache_just_disabled);
+      cp_state_when_enabling: coverpoint fill_buffer_state iff (icache_just_enabled);
+      cp_state_when_inval_start: coverpoint fill_buffer_state iff (icache_inval_start);
+      cp_starting_beat: coverpoint starting_beat iff (fill_alloc[i_fb]);
     endgroup
 
     `DV_FCOV_INSTANTIATE_CG(icache_fillbuf_cg, en_icache_fcov)
diff --git a/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_monitor.sv b/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_monitor.sv
index deef3418..8b66823c 100644
--- a/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_monitor.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_monitor.sv
@@ -35,7 +35,7 @@ class ibex_icache_core_monitor extends dv_base_monitor #(
   endtask
 
   // collect transactions forever - already forked in dv_base_moditor::run_phase
-  virtual protected task collect_trans(uvm_phase phase);
+  virtual protected task collect_trans();
     ibex_icache_core_bus_item trans;
     logic                     last_inval = 0;
     logic                     last_enable = 0;
diff --git a/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_monitor.sv b/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_monitor.sv
index b9e5c14d..6778cd5a 100644
--- a/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_monitor.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_monitor.sv
@@ -30,7 +30,7 @@ class ibex_icache_mem_monitor
   endtask
 
   // Collect transactions forever. Forked in dv_base_moditor::run_phase
-  protected task automatic collect_trans(uvm_phase phase);
+  protected task automatic collect_trans();
     fork
       collect_grants();
       collect_responses();
diff --git a/vendor/lowrisc_ibex/dv/uvm/icache/dv/tb/tb.sv b/vendor/lowrisc_ibex/dv/uvm/icache/dv/tb/tb.sv
index dcf99e19..0b1d0e00 100644
--- a/vendor/lowrisc_ibex/dv/uvm/icache/dv/tb/tb.sv
+++ b/vendor/lowrisc_ibex/dv/uvm/icache/dv/tb/tb.sv
@@ -32,7 +32,6 @@ module tb #(
   localparam int unsigned LineSizeECC = BusSizeECC * IC_LINE_BEATS;
   localparam int unsigned TagSizeECC  = ICacheECC ? (IC_TAG_SIZE + 6) : IC_TAG_SIZE;
   localparam int unsigned NumAddrScrRounds  = 2;
-  localparam int unsigned NumDiffRounds     = NumAddrScrRounds;
 
   ibex_icache_ram_if #(
     .TagSizeECC(TagSizeECC),
@@ -137,31 +136,32 @@ module tb #(
       .Depth            (IC_NUM_LINES),
       .DataBitsPerMask  (TagSizeECC),
       .EnableParity     (0),
-      .DiffWidth        (TagSizeECC),
-      .NumAddrScrRounds (NumAddrScrRounds),
-      .NumDiffRounds    (NumDiffRounds)
+      .NumAddrScrRounds (NumAddrScrRounds)
     ) tag_bank (
-      .clk_i       (clk),
-      .rst_ni      (rst_n),
-
-      .key_valid_i (scramble_key_valid_q),
-      .key_i       (scramble_key_q),
-      .nonce_i     (scramble_nonce_q),
-
-      .req_i       (ram_if.ic_tag_req[way]),
-
-      .gnt_o       (),
-      .write_i     (ram_if.ic_tag_write),
-      .addr_i      (ram_if.ic_tag_addr),
-      .wdata_i     (ram_if.ic_tag_wdata),
-      .wmask_i     ({TagSizeECC{1'b1}}),
-      .intg_error_i(1'b0),
-
-      .rdata_o     (ram_if.ic_tag_rdata_in[way]),
-      .rvalid_o    (ram_if.ic_tag_rvalid[way]),
-      .raddr_o     (),
-      .rerror_o    (),
-      .cfg_i       ('0)
+      .clk_i            (clk),
+      .rst_ni           (rst_n),
+
+      .key_valid_i      (scramble_key_valid_q),
+      .key_i            (scramble_key_q),
+      .nonce_i          (scramble_nonce_q),
+
+      .req_i            (ram_if.ic_tag_req[way]),
+
+      .gnt_o            (),
+      .write_i          (ram_if.ic_tag_write),
+      .addr_i           (ram_if.ic_tag_addr),
+      .wdata_i          (ram_if.ic_tag_wdata),
+      .wmask_i          ({TagSizeECC{1'b1}}),
+      .intg_error_i     (1'b0),
+
+      .rdata_o          (ram_if.ic_tag_rdata_in[way]),
+      .rvalid_o         (ram_if.ic_tag_rvalid[way]),
+      .raddr_o          (),
+      .rerror_o         (),
+      .cfg_i            ('0),
+      .wr_collision_o   (),
+      .write_pending_o  (),
+      .alert_o          ()
     );
 
     // Data RAM instantiation
@@ -171,31 +171,32 @@ module tb #(
       .DataBitsPerMask    (LineSizeECC),
       .EnableParity       (0),
       .ReplicateKeyStream (1),
-      .DiffWidth          (LineSizeECC),
-      .NumAddrScrRounds   (NumAddrScrRounds),
-      .NumDiffRounds      (NumDiffRounds)
+      .NumAddrScrRounds   (NumAddrScrRounds)
     ) data_bank (
-      .clk_i       (clk),
-      .rst_ni      (rst_n),
-
-      .key_valid_i (scramble_key_valid_q),
-      .key_i       (scramble_key_q),
-      .nonce_i     (scramble_nonce_q),
-
-      .req_i       (ram_if.ic_data_req[way]),
-
-      .gnt_o       (),
-      .write_i     (ram_if.ic_data_write),
-      .addr_i      (ram_if.ic_data_addr),
-      .wdata_i     (ram_if.ic_data_wdata),
-      .wmask_i     ({LineSizeECC{1'b1}}),
-      .intg_error_i(1'b0),
-
-      .rdata_o     (ram_if.ic_data_rdata_in[way]),
-      .rvalid_o    (ram_if.ic_data_rvalid[way]),
-      .raddr_o     (),
-      .rerror_o    (),
-      .cfg_i       ('0)
+      .clk_i            (clk),
+      .rst_ni           (rst_n),
+
+      .key_valid_i      (scramble_key_valid_q),
+      .key_i            (scramble_key_q),
+      .nonce_i          (scramble_nonce_q),
+
+      .req_i            (ram_if.ic_data_req[way]),
+
+      .gnt_o            (),
+      .write_i          (ram_if.ic_data_write),
+      .addr_i           (ram_if.ic_data_addr),
+      .wdata_i          (ram_if.ic_data_wdata),
+      .wmask_i          ({LineSizeECC{1'b1}}),
+      .intg_error_i     (1'b0),
+
+      .rdata_o          (ram_if.ic_data_rdata_in[way]),
+      .rvalid_o         (ram_if.ic_data_rvalid[way]),
+      .raddr_o          (),
+      .rerror_o         (),
+      .cfg_i            ('0),
+      .wr_collision_o   (),
+      .write_pending_o  (),
+      .alert_o          ()
     );
   end
 
diff --git a/vendor/lowrisc_ibex/dv/verilator/pcount/cpp/ibex_pcounts.cc b/vendor/lowrisc_ibex/dv/verilator/pcount/cpp/ibex_pcounts.cc
index 6924ee52..b3f1bd38 100644
--- a/vendor/lowrisc_ibex/dv/verilator/pcount/cpp/ibex_pcounts.cc
+++ b/vendor/lowrisc_ibex/dv/verilator/pcount/cpp/ibex_pcounts.cc
@@ -53,10 +53,9 @@ static bool has_hpm_counter(int index) {
 
 std::string ibex_pcount_string(bool csv) {
   char separator = csv ? ',' : ':';
-  std::string::size_type longest_name_length;
+  std::string::size_type longest_name_length = 0;
 
   if (!csv) {
-    longest_name_length = 0;
     for (int i = 0; i < ibex_counter_names.size(); ++i) {
       if (has_hpm_counter(i)) {
         longest_name_length =
diff --git a/vendor/lowrisc_ibex/dv/verilator/simple_system_cosim/ibex_simple_system_cosim.core b/vendor/lowrisc_ibex/dv/verilator/simple_system_cosim/ibex_simple_system_cosim.core
index 958540e7..fd19ef68 100644
--- a/vendor/lowrisc_ibex/dv/verilator/simple_system_cosim/ibex_simple_system_cosim.core
+++ b/vendor/lowrisc_ibex/dv/verilator/simple_system_cosim/ibex_simple_system_cosim.core
@@ -179,7 +179,7 @@ targets:
           - '--trace-structs'
           - '--trace-params'
           - '--trace-max-array 1024'
-          - '-CFLAGS "-std=c++11 -Wall -DVL_USER_STOP -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_simple_system -g `pkg-config --cflags riscv-riscv riscv-disasm riscv-fdt`"'
+          - '-CFLAGS "-std=c++14 -Wall -DVL_USER_STOP -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_simple_system -g `pkg-config --cflags riscv-riscv riscv-disasm riscv-fdt`"'
           - '-LDFLAGS "-pthread -lutil -lelf `pkg-config --libs riscv-riscv riscv-disasm riscv-fdt`"'
           - "-Wall"
           - "-Wwarn-IMPERFECTSCH"
diff --git a/vendor/lowrisc_ibex/dv/verilator/simple_system_cosim/ibex_simple_system_cosim_checker.sv b/vendor/lowrisc_ibex/dv/verilator/simple_system_cosim/ibex_simple_system_cosim_checker.sv
index 6ff2d2c1..0f7ebded 100644
--- a/vendor/lowrisc_ibex/dv/verilator/simple_system_cosim/ibex_simple_system_cosim_checker.sv
+++ b/vendor/lowrisc_ibex/dv/verilator/simple_system_cosim/ibex_simple_system_cosim_checker.sv
@@ -44,7 +44,7 @@ module ibex_simple_system_cosim_checker #(
     if (u_top.rvfi_valid) begin
       riscv_cosim_set_nmi(cosim_handle, u_top.rvfi_ext_nmi);
       riscv_cosim_set_nmi_int(cosim_handle, u_top.rvfi_ext_nmi_int);
-      riscv_cosim_set_mip(cosim_handle, u_top.rvfi_ext_mip);
+      riscv_cosim_set_mip(cosim_handle, u_top.rvfi_ext_pre_mip, u_top.rvfi_ext_post_mip);
       riscv_cosim_set_debug_req(cosim_handle, u_top.rvfi_ext_debug_req);
       riscv_cosim_set_mcycle(cosim_handle, u_top.rvfi_ext_mcycle);
       for (int i=0; i < 10; i++) begin
@@ -76,6 +76,8 @@ module ibex_simple_system_cosim_checker #(
   logic [31:0] outstanding_store_data;
   logic outstanding_misaligned_first;
   logic outstanding_misaligned_second;
+  logic outstanding_misaligned_first_saw_error;
+  logic outstanding_m_mode_access;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -93,12 +95,20 @@ module ibex_simple_system_cosim_checker #(
 
         outstanding_misaligned_second <=
           u_top.u_ibex_top.u_ibex_core.load_store_unit_i.addr_incr_req_o;
+
+        outstanding_misaligned_first_saw_error <=
+          u_top.u_ibex_top.u_ibex_core.load_store_unit_i.addr_incr_req_o &
+          u_top.u_ibex_top.u_ibex_core.load_store_unit_i.lsu_err_d;
+
+        outstanding_m_mode_access <=
+          u_top.u_ibex_top.u_ibex_core.priv_mode_lsu == ibex_pkg::PRIV_LVL_M;
       end
 
       if (host_dmem_rvalid) begin
         riscv_cosim_notify_dside_access(cosim_handle, outstanding_store, outstanding_addr,
           outstanding_store ? outstanding_store_data : host_dmem_rdata, outstanding_be,
-          host_dmem_err, outstanding_misaligned_first, outstanding_misaligned_second);
+          host_dmem_err, outstanding_misaligned_first, outstanding_misaligned_second,
+          outstanding_misaligned_first_saw_error, outstanding_m_mode_access);
       end
     end
   end
diff --git a/vendor/lowrisc_ibex/examples/simple_system/README.md b/vendor/lowrisc_ibex/examples/simple_system/README.md
index 12ab72df..026bbb7c 100644
--- a/vendor/lowrisc_ibex/examples/simple_system/README.md
+++ b/vendor/lowrisc_ibex/examples/simple_system/README.md
@@ -11,7 +11,7 @@ run stand-alone binaries. It contains:
 
 ## Prerequisites
 
-* [Verilator](https://www.veripool.org/wiki/verilator)
+* [Verilator](https://www.veripool.org/verilator/)
   Note Linux package managers may have Verilator but often a very old version
   that is not suitable. It is recommended Verilator is built from source.
 * The Python dependencies of this repository.
diff --git a/vendor/lowrisc_ibex/examples/simple_system/ibex_simple_system.core b/vendor/lowrisc_ibex/examples/simple_system/ibex_simple_system.core
index 0e3e723f..bfede16a 100644
--- a/vendor/lowrisc_ibex/examples/simple_system/ibex_simple_system.core
+++ b/vendor/lowrisc_ibex/examples/simple_system/ibex_simple_system.core
@@ -175,7 +175,7 @@ targets:
           - '--trace-structs'
           - '--trace-params'
           - '--trace-max-array 1024'
-          - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_simple_system -g"'
+          - '-CFLAGS "-std=c++14 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_simple_system -g"'
           - '-LDFLAGS "-pthread -lutil -lelf"'
           - "-Wall"
           - "-Wwarn-IMPERFECTSCH"
diff --git a/vendor/lowrisc_ibex/examples/simple_system/lint/verilator_waiver.vlt b/vendor/lowrisc_ibex/examples/simple_system/lint/verilator_waiver.vlt
index b454d0c5..44a1c286 100644
--- a/vendor/lowrisc_ibex/examples/simple_system/lint/verilator_waiver.vlt
+++ b/vendor/lowrisc_ibex/examples/simple_system/lint/verilator_waiver.vlt
@@ -9,7 +9,7 @@
 // 'rtl' directory), see verilator_waiver_rtl.vlt in the same
 // directory.
 //
-// See https://www.veripool.org/projects/verilator/wiki/Manual-verilator#CONFIGURATION-FILES
+// See https://verilator.org/guide/latest/exe_verilator.html#configuration-files
 // for documentation.
 //
 // Important: This file must included *before* any other Verilog file is read.
diff --git a/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv b/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv
index ac74691d..e466ac28 100644
--- a/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv
+++ b/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv
@@ -204,6 +204,8 @@ module ibex_simple_system (
       .WritebackStage  ( WritebackStage   ),
       .BranchPredictor ( BranchPredictor  ),
       .DbgTriggerEn    ( DbgTriggerEn     ),
+      .DmBaseAddr      ( 32'h00100000     ),
+      .DmAddrMask      ( 32'h00000003     ),
       .DmHaltAddr      ( 32'h00100000     ),
       .DmExceptionAddr ( 32'h00100000     )
     ) u_top (
diff --git a/vendor/lowrisc_ibex/examples/sw/benchmarks/README.md b/vendor/lowrisc_ibex/examples/sw/benchmarks/README.md
index 49bebb6a..05294b80 100644
--- a/vendor/lowrisc_ibex/examples/sw/benchmarks/README.md
+++ b/vendor/lowrisc_ibex/examples/sw/benchmarks/README.md
@@ -11,9 +11,13 @@ All of these benchmarks run on Simple System. A verilator simulation suitable
 for running them can be built with:
 
 ```
-fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system --RV32E=0 --RV32M=ibex_pkg::RV32MFast
+fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system `./util/ibex_config.py maxperf fusesoc_opts`
 ```
 
+This will build a simulation of Ibex in the 'maxperf' configuration.
+It is one of several pre-defined ibex configurations, others can be used.
+These are specified in the `ibex_configs.yaml` file.
+
 See examples/simple_system/README.md for full details.
 
 ## CoreMark
diff --git a/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.c b/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.c
index d3945157..704665ce 100644
--- a/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.c
+++ b/vendor/lowrisc_ibex/examples/sw/benchmarks/coremark/ibex/core_portme.c
@@ -169,6 +169,7 @@ void portable_init(core_portable *p, int *argc, char *argv[]) {
     ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n");
   }
   p->portable_id = 1;
+  icache_enable(1);
 }
 /* Function : portable_fini
         Target specific final code
diff --git a/vendor/lowrisc_ibex/examples/sw/simple_system/common/simple_system_common.h b/vendor/lowrisc_ibex/examples/sw/simple_system/common/simple_system_common.h
index 949df9db..e0caf6d4 100644
--- a/vendor/lowrisc_ibex/examples/sw/simple_system/common/simple_system_common.h
+++ b/vendor/lowrisc_ibex/examples/sw/simple_system/common/simple_system_common.h
@@ -95,4 +95,21 @@ void timer_disable(void);
  */
 uint64_t get_elapsed_time(void);
 
+/**
+ * Enables/disables the instruction cache. This has no effect on Ibex
+ * configurations that do not have an instruction cache and in particular is
+ * safe to execute on those configurations.
+ *
+ * @param enable if non-zero enables, otherwise disables
+ */
+static inline void icache_enable(int enable) {
+  if (enable) {
+    // Set icache enable bit in CPUCTRLSTS
+    asm volatile("csrs 0x7c0, 1");
+  } else {
+    // Clear icache enable bit in CPUCTRLSTS
+    asm volatile("csrc 0x7c0, 1");
+  }
+}
+
 #endif
diff --git a/vendor/lowrisc_ibex/ibex_core.core b/vendor/lowrisc_ibex/ibex_core.core
index a9fd400b..15fb3278 100644
--- a/vendor/lowrisc_ibex/ibex_core.core
+++ b/vendor/lowrisc_ibex/ibex_core.core
@@ -11,6 +11,7 @@ filesets:
       - lowrisc:prim:assert
       - lowrisc:prim:clock_gating
       - lowrisc:prim:lfsr
+      - lowrisc:prim:mubi
       - lowrisc:ibex:ibex_pkg
       - lowrisc:ibex:ibex_icache
       - lowrisc:dv:dv_fcov_macros
@@ -35,7 +36,6 @@ filesets:
       - rtl/ibex_wb_stage.sv
       - rtl/ibex_dummy_instr.sv
       - rtl/ibex_core.sv
-      - rtl/ibex_pmp_reset_default.svh: {is_include_file: true}
     file_type: systemVerilogSource
 
   files_lint_verilator:
diff --git a/vendor/lowrisc_ibex/ibex_top.core b/vendor/lowrisc_ibex/ibex_top.core
index e8e5d011..38a279df 100644
--- a/vendor/lowrisc_ibex/ibex_top.core
+++ b/vendor/lowrisc_ibex/ibex_top.core
@@ -13,6 +13,7 @@ filesets:
       - lowrisc:prim:and2
       - lowrisc:prim:buf
       - lowrisc:prim:clock_mux2
+      - lowrisc:prim:count
       - lowrisc:prim:flop
       - lowrisc:prim:ram_1p_scr
       - lowrisc:prim:onehot_check
diff --git a/vendor/lowrisc_ibex/lint/verilator_waiver.vlt b/vendor/lowrisc_ibex/lint/verilator_waiver.vlt
index d03f9bcb..939bb3fb 100644
--- a/vendor/lowrisc_ibex/lint/verilator_waiver.vlt
+++ b/vendor/lowrisc_ibex/lint/verilator_waiver.vlt
@@ -3,7 +3,7 @@
 // SPDX-License-Identifier: Apache-2.0
 
 // Lint waivers for Verilator
-// See https://www.veripool.org/projects/verilator/wiki/Manual-verilator#CONFIGURATION-FILES
+// See https://verilator.org/guide/latest/exe_verilator.html#configuration-files
 // for documentation.
 //
 // Important: This file must included *before* any other Verilog file is read.
diff --git a/vendor/lowrisc_ibex/python-requirements.txt b/vendor/lowrisc_ibex/python-requirements.txt
index d6b7fe13..e631f29e 100644
--- a/vendor/lowrisc_ibex/python-requirements.txt
+++ b/vendor/lowrisc_ibex/python-requirements.txt
@@ -17,7 +17,7 @@ pathlib3x  # Backports some useful features
 typing-utils  # Ditto
 typeguard ~= 2.13
 portalocker
-pydantic
+pydantic >= 2
 svg.py
 
 # Needed by dvsim.py (not actually used in Ibex)
diff --git a/vendor/lowrisc_ibex/rtl/ibex_controller.sv b/vendor/lowrisc_ibex/rtl/ibex_controller.sv
index 79c2a87e..1b2666c0 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_controller.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_controller.sv
@@ -175,7 +175,7 @@ module ibex_controller #(
     // print warning in case of decoding errors
     if ((ctrl_fsm_cs == DECODE) && instr_valid_i && !instr_fetch_err_i && illegal_insn_d) begin
       $display("%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, u_ibex_core.hart_id_i,
-               pc_id_i, id_stage_i.instr_rdata_i);
+               pc_id_i, instr_is_compressed_i ? {16'b0, instr_compressed_i} : instr_i );
     end
   end
   // synopsys translate_on
@@ -352,7 +352,7 @@ module ibex_controller #(
 
     // As integrity error is the only internal interrupt implement, set irq_nm_* signals directly
     // within this generate block.
-    assign irq_nm_int       = mem_resp_intg_err_irq_set | mem_resp_intg_err_irq_pending_q;
+    assign irq_nm_int       = mem_resp_intg_err_irq_pending_q;
     assign irq_nm_int_cause = NMI_INT_CAUSE_ECC;
     assign irq_nm_int_mtval = mem_resp_intg_err_addr_q;
   end else begin : g_no_intg_irq_int
@@ -925,79 +925,14 @@ module ibex_controller #(
       RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH,
       IRQ_TAKEN, DBG_TAKEN_IF, DBG_TAKEN_ID})
 
-  `ifdef INC_ASSERT
-    // If something that causes a jump into an exception handler is seen that jump must occur before
-    // the next instruction executes. The logic tracks whether a jump into an exception handler is
-    // expected. Assertions check the jump occurs.
-
-    logic exception_req, exception_req_pending, exception_req_accepted, exception_req_done;
-    logic exception_pc_set, seen_exception_pc_set, expect_exception_pc_set;
-    logic exception_req_needs_pc_set;
-
-    assign exception_req = (special_req | enter_debug_mode | handle_irq);
-    // Any exception rquest will cause a transition out of DECODE, once the controller transitions
-    // back into DECODE we're done handling the request.
-    assign exception_req_done =
-      exception_req_pending & (ctrl_fsm_cs != DECODE) & (ctrl_fsm_ns == DECODE);
-
-    assign exception_req_needs_pc_set = enter_debug_mode | handle_irq | special_req_pc_change;
-
-    // An exception PC set uses specific PC types
-    assign exception_pc_set =
-      exception_req_pending & (pc_set_o & (pc_mux_o inside {PC_EXC, PC_ERET, PC_DRET}));
-
-    always @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        exception_req_pending   <= 1'b0;
-        exception_req_accepted  <= 1'b0;
-        expect_exception_pc_set <= 1'b0;
-        seen_exception_pc_set   <= 1'b0;
-      end else begin
-        // Keep `exception_req_pending` asserted once an exception_req is seen until it is done
-        exception_req_pending <= (exception_req_pending | exception_req) & ~exception_req_done;
-
-        // The exception req has been accepted once the controller transitions out of decode
-        exception_req_accepted <= (exception_req_accepted & ~exception_req_done) |
-          (exception_req & ctrl_fsm_ns != DECODE);
-
-        // Set `expect_exception_pc_set` if exception req needs one and keep it asserted until
-        // exception req is done
-        expect_exception_pc_set <= (expect_exception_pc_set | exception_req_needs_pc_set) &
-          ~exception_req_done;
-
-        // Keep `seen_exception_pc_set` asserted once an exception PC set is seen until the
-        // exception req is done
-        seen_exception_pc_set <= (seen_exception_pc_set | exception_pc_set) & ~exception_req_done;
-      end
-    end
-
-    // Once an exception request has been accepted it must be handled before controller goes back to
-    // DECODE
-    `ASSERT(IbexNoDoubleExceptionReq, exception_req_accepted |-> ctrl_fsm_cs != DECODE)
-
-    // Only signal ready, allowing a new instruction into ID, if there is no exception request
-    // pending or it is done this cycle.
-    `ASSERT(IbexDontSkipExceptionReq,
-      id_in_ready_o |-> !exception_req_pending || exception_req_done)
-
-    // Once a PC set has been performed for an exception request there must not be any other
-    // excepting those to move into debug mode.
-    `ASSERT(IbexNoDoubleSpecialReqPCSet,
-      seen_exception_pc_set &&
-        !((ctrl_fsm_cs inside {DBG_TAKEN_IF, DBG_TAKEN_ID}) &&
-          (pc_mux_o == PC_EXC) && (exc_pc_mux_o == EXC_PC_DBD))
-      |-> !pc_set_o)
-
-    // When an exception request is done there must have been an appropriate PC set (either this
-    // cycle or a previous one).
-    `ASSERT(IbexSetExceptionPCOnSpecialReqIfExpected,
-      exception_req_pending && expect_exception_pc_set && exception_req_done |->
-      seen_exception_pc_set || exception_pc_set)
-
-    // If there's a pending exception req that doesn't need a PC set we must not see one
-    `ASSERT(IbexNoPCSetOnSpecialReqIfNotExpected,
-      exception_req_pending && !expect_exception_pc_set |-> ~pc_set_o)
-  `endif
+  // If entering or exiting debug mode, the pipeline must be flushed. This is because Ibex
+  // currently does not support some of the pipeline stages being in debug mode; either all or
+  // none of the pipeline stages must be in debug mode. As `flush_id_o` only affects the ID/EX
+  // stage but does not prevent a fetched instruction from proceeding to ID/EX the next cycle, the
+  // assertion additionally requires `pc_set_o`, which sets the PC in the IF stage to a new value,
+  // hence preventing a fetched instruction from proceeding to the ID/EX stage in the next cycle.
+  `ASSERT(IbexPipelineFlushOnChangingDebugMode,
+    debug_mode_d != debug_mode_q |-> flush_id_o & pc_set_o)
 
   `ifdef RVFI
     // Workaround for internal verilator error when using hierarchical refers to calcuate this
diff --git a/vendor/lowrisc_ibex/rtl/ibex_core.f b/vendor/lowrisc_ibex/rtl/ibex_core.f
index 83e8396b..cde47fca 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_core.f
+++ b/vendor/lowrisc_ibex/rtl/ibex_core.f
@@ -1,3 +1,7 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
 ibex_pkg.sv
 ibex_alu.sv
 ibex_compressed_decoder.sv
diff --git a/vendor/lowrisc_ibex/rtl/ibex_core.sv b/vendor/lowrisc_ibex/rtl/ibex_core.sv
index 67548fdb..b8f693ca 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_core.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_core.sv
@@ -14,39 +14,48 @@
  * Top level module of the ibex RISC-V core
  */
 module ibex_core import ibex_pkg::*; #(
-  parameter bit          PMPEnable         = 1'b0,
-  parameter int unsigned PMPGranularity    = 0,
-  parameter int unsigned PMPNumRegions     = 4,
-  parameter int unsigned MHPMCounterNum    = 0,
-  parameter int unsigned MHPMCounterWidth  = 40,
-  parameter bit          RV32E             = 1'b0,
-  parameter rv32m_e      RV32M             = RV32MFast,
-  parameter rv32b_e      RV32B             = RV32BNone,
-  parameter bit          BranchTargetALU   = 1'b0,
-  parameter bit          WritebackStage    = 1'b0,
-  parameter bit          ICache            = 1'b0,
-  parameter bit          ICacheECC         = 1'b0,
-  parameter int unsigned BusSizeECC        = BUS_SIZE,
-  parameter int unsigned TagSizeECC        = IC_TAG_SIZE,
-  parameter int unsigned LineSizeECC       = IC_LINE_SIZE,
-  parameter bit          BranchPredictor   = 1'b0,
-  parameter bit          DbgTriggerEn      = 1'b0,
-  parameter int unsigned DbgHwBreakNum     = 1,
-  parameter bit          ResetAll          = 1'b0,
-  parameter lfsr_seed_t  RndCnstLfsrSeed   = RndCnstLfsrSeedDefault,
-  parameter lfsr_perm_t  RndCnstLfsrPerm   = RndCnstLfsrPermDefault,
-  parameter bit          SecureIbex        = 1'b0,
-  parameter bit          DummyInstructions = 1'b0,
-  parameter bit          RegFileECC        = 1'b0,
-  parameter int unsigned RegFileDataWidth  = 32,
-  parameter bit          MemECC            = 1'b0,
-  parameter int unsigned MemDataWidth      = MemECC ? 32 + 7 : 32,
-  parameter int unsigned DmHaltAddr        = 32'h1A110800,
-  parameter int unsigned DmExceptionAddr   = 32'h1A110808
+  parameter bit                     PMPEnable        = 1'b0,
+  parameter int unsigned            PMPGranularity   = 0,
+  parameter int unsigned            PMPNumRegions    = 4,
+  parameter ibex_pkg::pmp_cfg_t     PMPRstCfg[16]    = ibex_pkg::PmpCfgRst,
+  parameter logic [33:0]            PMPRstAddr[16]   = ibex_pkg::PmpAddrRst,
+  parameter ibex_pkg::pmp_mseccfg_t PMPRstMsecCfg    = ibex_pkg::PmpMseccfgRst,
+  parameter int unsigned            MHPMCounterNum   = 0,
+  parameter int unsigned            MHPMCounterWidth = 40,
+  parameter bit                     RV32E            = 1'b0,
+  parameter rv32m_e                 RV32M            = RV32MFast,
+  parameter rv32b_e                 RV32B            = RV32BNone,
+  parameter bit                     BranchTargetALU  = 1'b0,
+  parameter bit                     WritebackStage   = 1'b0,
+  parameter bit                     ICache           = 1'b0,
+  parameter bit                     ICacheECC        = 1'b0,
+  parameter int unsigned            BusSizeECC       = BUS_SIZE,
+  parameter int unsigned            TagSizeECC       = IC_TAG_SIZE,
+  parameter int unsigned            LineSizeECC      = IC_LINE_SIZE,
+  parameter bit                     BranchPredictor  = 1'b0,
+  parameter bit                     DbgTriggerEn     = 1'b0,
+  parameter int unsigned            DbgHwBreakNum    = 1,
+  parameter bit                     ResetAll         = 1'b0,
+  parameter lfsr_seed_t             RndCnstLfsrSeed  = RndCnstLfsrSeedDefault,
+  parameter lfsr_perm_t             RndCnstLfsrPerm  = RndCnstLfsrPermDefault,
+  parameter bit                     SecureIbex       = 1'b0,
+  parameter bit                     DummyInstructions= 1'b0,
+  parameter bit                     RegFileECC       = 1'b0,
+  parameter int unsigned            RegFileDataWidth = 32,
+  parameter bit                     MemECC           = 1'b0,
+  parameter int unsigned            MemDataWidth     = MemECC ? 32 + 7 : 32,
+  parameter int unsigned            DmBaseAddr       = 32'h1A110000,
+  parameter int unsigned            DmAddrMask       = 32'h00000FFF,
+  parameter int unsigned            DmHaltAddr       = 32'h1A110800,
+  parameter int unsigned            DmExceptionAddr  = 32'h1A110808
 ) (
   // Clock and Reset
   input  logic                         clk_i,
+  // Internally generated resets in ibex_lockstep cause IMPERFECTSCH warnings.
+  // TODO: Remove when upgrading Verilator #2134.
+  /* verilator lint_off IMPERFECTSCH */
   input  logic                         rst_ni,
+  /* verilator lint_on IMPERFECTSCH */
 
   input  logic [31:0]                  hart_id_i,
   input  logic [31:0]                  boot_addr_i,
@@ -137,7 +146,8 @@ module ibex_core import ibex_pkg::*; #(
   output logic [ 3:0]                  rvfi_mem_wmask,
   output logic [31:0]                  rvfi_mem_rdata,
   output logic [31:0]                  rvfi_mem_wdata,
-  output logic [31:0]                  rvfi_ext_mip,
+  output logic [31:0]                  rvfi_ext_pre_mip,
+  output logic [31:0]                  rvfi_ext_post_mip,
   output logic                         rvfi_ext_nmi,
   output logic                         rvfi_ext_nmi_int,
   output logic                         rvfi_ext_debug_req,
@@ -207,11 +217,14 @@ module ibex_core import ibex_pkg::*; #(
   exc_cause_t  exc_cause;                      // Exception cause
 
   logic        instr_intg_err;
-  logic        lsu_load_err;
-  logic        lsu_store_err;
+  logic        lsu_load_err, lsu_load_err_raw;
+  logic        lsu_store_err, lsu_store_err_raw;
   logic        lsu_load_resp_intg_err;
   logic        lsu_store_resp_intg_err;
 
+  logic        expecting_load_resp_id;
+  logic        expecting_store_resp_id;
+
   // LSU signals
   logic        lsu_addr_incr_req;
   logic [31:0] lsu_addr_last;
@@ -286,6 +299,7 @@ module ibex_core import ibex_pkg::*; #(
   logic [1:0]  lsu_type;
   logic        lsu_sign_ext;
   logic        lsu_req;
+  logic        lsu_rdata_valid;
   logic [31:0] lsu_wdata;
   logic        lsu_req_done;
 
@@ -604,6 +618,7 @@ module ibex_core import ibex_pkg::*; #(
     // CSR ID/EX
     .csr_access_o         (csr_access),
     .csr_op_o             (csr_op),
+    .csr_addr_o           (csr_addr),
     .csr_op_en_o          (csr_op_en),
     .csr_save_if_o        (csr_save_if),  // control signal to save PC
     .csr_save_id_o        (csr_save_id),  // control signal to save PC
@@ -633,6 +648,9 @@ module ibex_core import ibex_pkg::*; #(
     .lsu_store_err_i          (lsu_store_err),
     .lsu_store_resp_intg_err_i(lsu_store_resp_intg_err),
 
+    .expecting_load_resp_o (expecting_load_resp_id),
+    .expecting_store_resp_o(expecting_store_resp_id),
+
     // Interrupt Signals
     .csr_mstatus_mie_i(csr_mstatus_mie),
     .irq_pending_i    (irq_pending_o),
@@ -770,7 +788,7 @@ module ibex_core import ibex_pkg::*; #(
     .lsu_sign_ext_i(lsu_sign_ext),
 
     .lsu_rdata_o      (rf_wdata_lsu),
-    .lsu_rdata_valid_o(rf_we_lsu),
+    .lsu_rdata_valid_o(lsu_rdata_valid),
     .lsu_req_i        (lsu_req),
     .lsu_req_done_o   (lsu_req_done),
 
@@ -783,9 +801,9 @@ module ibex_core import ibex_pkg::*; #(
     .lsu_resp_valid_o(lsu_resp_valid),
 
     // exception signals
-    .load_err_o           (lsu_load_err),
+    .load_err_o           (lsu_load_err_raw),
     .load_resp_intg_err_o (lsu_load_resp_intg_err),
-    .store_err_o          (lsu_store_err),
+    .store_err_o          (lsu_store_err_raw),
     .store_resp_intg_err_o(lsu_store_resp_intg_err),
 
     .busy_o(lsu_busy),
@@ -840,6 +858,28 @@ module ibex_core import ibex_pkg::*; #(
     .instr_done_wb_o(instr_done_wb)
   );
 
+  if (SecureIbex) begin : g_check_mem_response
+    // For secure configurations only process load/store responses if we're expecting them to guard
+    // against false responses being injected on to the bus
+    assign lsu_load_err  = lsu_load_err_raw  & (outstanding_load_wb  | expecting_load_resp_id);
+    assign lsu_store_err = lsu_store_err_raw & (outstanding_store_wb | expecting_store_resp_id);
+    assign rf_we_lsu     = lsu_rdata_valid   & (outstanding_load_wb  | expecting_load_resp_id);
+  end else begin : g_no_check_mem_response
+    // For non-secure configurations trust the bus protocol is being followed and we'll only ever
+    // see a response if we have an outstanding request.
+    assign lsu_load_err  = lsu_load_err_raw;
+    assign lsu_store_err = lsu_store_err_raw;
+    assign rf_we_lsu     = lsu_rdata_valid;
+
+    // expected_load_resp_id/expected_store_resp_id signals are only used to guard against false
+    // responses so they are unused in non-secure configurations
+    logic unused_expecting_load_resp_id;
+    logic unused_expecting_store_resp_id;
+
+    assign unused_expecting_load_resp_id  = expecting_load_resp_id;
+    assign unused_expecting_store_resp_id = expecting_store_resp_id;
+  end
+
   /////////////////////////////
   // Register file interface //
   /////////////////////////////
@@ -882,8 +922,8 @@ module ibex_core import ibex_pkg::*; #(
     assign rf_rdata_b = rf_rdata_b_ecc_i[31:0];
 
     // Calculate errors - qualify with WB forwarding to avoid xprop into the alert signal
-    assign rf_ecc_err_a_id = |rf_ecc_err_a & rf_ren_a & ~rf_rd_a_wb_match;
-    assign rf_ecc_err_b_id = |rf_ecc_err_b & rf_ren_b & ~rf_rd_b_wb_match;
+    assign rf_ecc_err_a_id = |rf_ecc_err_a & rf_ren_a & ~(rf_rd_a_wb_match & rf_write_wb);
+    assign rf_ecc_err_b_id = |rf_ecc_err_b & rf_ren_b & ~(rf_rd_b_wb_match & rf_write_wb);
 
     // Combined error
     assign rf_ecc_err_comb = instr_valid_id & (rf_ecc_err_a_id | rf_ecc_err_b_id);
@@ -981,13 +1021,19 @@ module ibex_core import ibex_pkg::*; #(
     end
   end
 
-  // When fetch is disabled no instructions should be executed. Once fetch is disabled either the
+  // A 1-bit encoding of fetch_enable_i to avoid polluting the NoExecWhenFetchEnableNotOn assertion
+  // with notes about SecureIbex and mubi values.
+  logic fetch_enable_raw;
+  assign fetch_enable_raw = SecureIbex ? (fetch_enable_i == IbexMuBiOn) : fetch_enable_i[0];
+
+  // When fetch is disabled, no instructions should be executed. Once fetch is disabled either the
   // ID/EX stage is not valid or the PC of the ID/EX stage must remain as it was at disable. The
   // ID/EX valid should not ressert once it has been cleared.
-  `ASSERT(NoExecWhenFetchEnableNotOn, fetch_enable_i != IbexMuBiOn |=>
-    (~instr_valid_id || (pc_id == pc_at_fetch_disable)) && ~$rose(instr_valid_id))
+  `ASSERT(NoExecWhenFetchEnableNotOn,
+          !fetch_enable_raw |=>
+          (~instr_valid_id || (pc_id == pc_at_fetch_disable)) && ~$rose(instr_valid_id))
 
-  `endif
+  `endif // INC_ASSERT
 
   ////////////////////////
   // RF (Register File) //
@@ -1001,7 +1047,6 @@ module ibex_core import ibex_pkg::*; #(
   /////////////////////////////////////////
 
   assign csr_wdata  = alu_operand_a_ex;
-  assign csr_addr   = csr_num_e'(csr_access ? alu_operand_b_ex[11:0] : 12'b0);
 
   ibex_cs_registers #(
     .DbgTriggerEn     (DbgTriggerEn),
@@ -1015,6 +1060,9 @@ module ibex_core import ibex_pkg::*; #(
     .PMPEnable        (PMPEnable),
     .PMPGranularity   (PMPGranularity),
     .PMPNumRegions    (PMPNumRegions),
+    .PMPRstCfg        (PMPRstCfg),
+    .PMPRstAddr       (PMPRstAddr),
+    .PMPRstMsecCfg    (PMPRstMsecCfg),
     .RV32E            (RV32E),
     .RV32M            (RV32M),
     .RV32B            (RV32B)
@@ -1137,6 +1185,8 @@ module ibex_core import ibex_pkg::*; #(
     assign pmp_priv_lvl[PMP_D]  = priv_mode_lsu;
 
     ibex_pmp #(
+      .DmBaseAddr    (DmBaseAddr),
+      .DmAddrMask    (DmAddrMask),
       .PMPGranularity(PMPGranularity),
       .PMPNumChan    (PMPNumChan),
       .PMPNumRegions (PMPNumRegions)
@@ -1145,6 +1195,7 @@ module ibex_core import ibex_pkg::*; #(
       .csr_pmp_cfg_i    (csr_pmp_cfg),
       .csr_pmp_addr_i   (csr_pmp_addr),
       .csr_pmp_mseccfg_i(csr_pmp_mseccfg),
+      .debug_mode_i     (debug_mode),
       .priv_mode_i      (pmp_priv_lvl),
       // Access checking channels
       .pmp_req_addr_i   (pmp_req_addr),
@@ -1250,7 +1301,8 @@ module ibex_core import ibex_pkg::*; #(
 
   // RVFI extension for co-simulation support
   // debug_req and MIP captured at IF -> ID transition so one extra stage
-  ibex_pkg::irqs_t rvfi_ext_stage_mip              [RVFI_STAGES+1];
+  ibex_pkg::irqs_t rvfi_ext_stage_pre_mip          [RVFI_STAGES+1];
+  ibex_pkg::irqs_t rvfi_ext_stage_post_mip         [RVFI_STAGES];
   logic            rvfi_ext_stage_nmi              [RVFI_STAGES+1];
   logic            rvfi_ext_stage_nmi_int          [RVFI_STAGES+1];
   logic            rvfi_ext_stage_debug_req        [RVFI_STAGES+1];
@@ -1295,11 +1347,21 @@ module ibex_core import ibex_pkg::*; #(
   always_comb begin
     // Use always_comb instead of continuous assign so first assign can set 0 as default everywhere
     // that is overridden by more specific settings.
-    rvfi_ext_mip                                     = '0;
-    rvfi_ext_mip[CSR_MSIX_BIT]                       = rvfi_ext_stage_mip[RVFI_STAGES].irq_software;
-    rvfi_ext_mip[CSR_MTIX_BIT]                       = rvfi_ext_stage_mip[RVFI_STAGES].irq_timer;
-    rvfi_ext_mip[CSR_MEIX_BIT]                       = rvfi_ext_stage_mip[RVFI_STAGES].irq_external;
-    rvfi_ext_mip[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = rvfi_ext_stage_mip[RVFI_STAGES].irq_fast;
+    rvfi_ext_pre_mip               = '0;
+    rvfi_ext_pre_mip[CSR_MSIX_BIT] = rvfi_ext_stage_pre_mip[RVFI_STAGES].irq_software;
+    rvfi_ext_pre_mip[CSR_MTIX_BIT] = rvfi_ext_stage_pre_mip[RVFI_STAGES].irq_timer;
+    rvfi_ext_pre_mip[CSR_MEIX_BIT] = rvfi_ext_stage_pre_mip[RVFI_STAGES].irq_external;
+
+    rvfi_ext_pre_mip[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] =
+      rvfi_ext_stage_pre_mip[RVFI_STAGES].irq_fast;
+
+    rvfi_ext_post_mip               = '0;
+    rvfi_ext_post_mip[CSR_MSIX_BIT] = rvfi_ext_stage_post_mip[RVFI_STAGES-1].irq_software;
+    rvfi_ext_post_mip[CSR_MTIX_BIT] = rvfi_ext_stage_post_mip[RVFI_STAGES-1].irq_timer;
+    rvfi_ext_post_mip[CSR_MEIX_BIT] = rvfi_ext_stage_post_mip[RVFI_STAGES-1].irq_external;
+
+    rvfi_ext_post_mip[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] =
+      rvfi_ext_stage_post_mip[RVFI_STAGES-1].irq_fast;
   end
 
   assign rvfi_ext_nmi              = rvfi_ext_stage_nmi              [RVFI_STAGES];
@@ -1454,12 +1516,12 @@ module ibex_core import ibex_pkg::*; #(
   // the DV environment will see if a trap should have been taken but wasn't.
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
-      rvfi_ext_stage_mip[0]       <= '0;
+      rvfi_ext_stage_pre_mip[0]       <= '0;
       rvfi_ext_stage_nmi[0]       <= '0;
       rvfi_ext_stage_nmi_int[0]   <= '0;
       rvfi_ext_stage_debug_req[0] <= '0;
     end else if ((if_stage_i.instr_valid_id_d & if_stage_i.instr_new_id_d) | rvfi_irq_valid) begin
-      rvfi_ext_stage_mip[0]       <= instr_valid_id | ~captured_valid ? cs_registers_i.mip :
+      rvfi_ext_stage_pre_mip[0]   <= instr_valid_id | ~captured_valid ? cs_registers_i.mip :
                                                                         captured_mip;
       rvfi_ext_stage_nmi[0]       <= instr_valid_id | ~captured_valid ? irq_nm_i :
                                                                         captured_nmi;
@@ -1520,7 +1582,8 @@ module ibex_core import ibex_pkg::*; #(
         rvfi_stage_mem_rdata[i]            <= '0;
         rvfi_stage_mem_wdata[i]            <= '0;
         rvfi_stage_mem_addr[i]             <= '0;
-        rvfi_ext_stage_mip[i+1]            <= '0;
+        rvfi_ext_stage_pre_mip[i+1]        <= '0;
+        rvfi_ext_stage_post_mip[i]         <= '0;
         rvfi_ext_stage_nmi[i+1]            <= '0;
         rvfi_ext_stage_nmi_int[i+1]        <= '0;
         rvfi_ext_stage_debug_req[i+1]      <= '0;
@@ -1534,7 +1597,7 @@ module ibex_core import ibex_pkg::*; #(
 
         if (i == 0) begin
           if (rvfi_id_done) begin
-            rvfi_stage_halt[i]      <= '0;
+            rvfi_stage_halt[i]                 <= '0;
             rvfi_stage_trap[i]                 <= rvfi_trap_id;
             rvfi_stage_intr[i]                 <= rvfi_intr_d;
             rvfi_stage_order[i]                <= rvfi_stage_order_d;
@@ -1572,7 +1635,8 @@ module ibex_core import ibex_pkg::*; #(
           // providing information along with a retired instruction. Move these up the rvfi pipeline
           // for both cases.
           if (rvfi_id_done | rvfi_ext_stage_irq_valid[i]) begin
-            rvfi_ext_stage_mip[i+1]       <= rvfi_ext_stage_mip[i];
+            rvfi_ext_stage_pre_mip[i+1]   <= rvfi_ext_stage_pre_mip[i];
+            rvfi_ext_stage_post_mip[i]    <= cs_registers_i.mip;
             rvfi_ext_stage_nmi[i+1]       <= rvfi_ext_stage_nmi[i];
             rvfi_ext_stage_nmi_int[i+1]   <= rvfi_ext_stage_nmi_int[i];
             rvfi_ext_stage_debug_req[i+1] <= rvfi_ext_stage_debug_req[i];
@@ -1619,7 +1683,8 @@ module ibex_core import ibex_pkg::*; #(
           // providing information along with a retired instruction. Move these up the rvfi pipeline
           // for both cases.
           if (rvfi_wb_done | rvfi_ext_stage_irq_valid[i]) begin
-            rvfi_ext_stage_mip[i+1]       <= rvfi_ext_stage_mip[i];
+            rvfi_ext_stage_pre_mip[i+1]   <= rvfi_ext_stage_pre_mip[i];
+            rvfi_ext_stage_post_mip[i]    <= rvfi_ext_stage_post_mip[i-1];
             rvfi_ext_stage_nmi[i+1]       <= rvfi_ext_stage_nmi[i];
             rvfi_ext_stage_nmi_int[i+1]   <= rvfi_ext_stage_nmi_int[i];
             rvfi_ext_stage_debug_req[i+1] <= rvfi_ext_stage_debug_req[i];
@@ -1630,7 +1695,7 @@ module ibex_core import ibex_pkg::*; #(
   end
 
 
-  // Memory adddress/write data available first cycle of ld/st instruction from register read
+  // Memory address/write data available first cycle of ld/st instruction from register read
   always_comb begin
     if (instr_first_cycle_id) begin
       rvfi_mem_addr_d  = alu_adder_result_ex;
@@ -1806,6 +1871,9 @@ module ibex_core import ibex_pkg::*; #(
   // Certain parameter combinations are not supported
   `ASSERT_INIT(IllegalParamSecure, !(SecureIbex && (RV32M == RV32MNone)))
 
+  // If the ID stage signals its ready the mult/div FSMs must be idle in the following cycle
+  `ASSERT(MultDivFSMIdleOnIdReady, id_in_ready |=> ex_block_i.sva_multdiv_fsm_idle)
+
   //////////
   // FCOV //
   //////////
diff --git a/vendor/lowrisc_ibex/rtl/ibex_counter.sv b/vendor/lowrisc_ibex/rtl/ibex_counter.sv
index a6187b78..83b31dee 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_counter.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_counter.sv
@@ -1,3 +1,7 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
 module ibex_counter #(
   parameter int CounterWidth = 32,
   // When set `counter_val_upd_o` provides an incremented version of the counter value, otherwise
@@ -47,27 +51,38 @@ module ibex_counter #(
   end
 
 `ifdef FPGA_XILINX
-  // Set DSP pragma for supported xilinx FPGAs
-  localparam int DspPragma = CounterWidth < 49 ? "yes" : "no";
-  (* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q;
-
-  // DSP output register requires synchronous reset.
-  `define COUNTER_FLOP_RST posedge clk_i
+  // On Xilinx FPGAs, 48-bit DSPs are available that can be used for the
+  // counter. Hence, use Xilinx specific flop implementation. The datatype for
+  // UseDsp is on purpose int as with string Xilinx throws an error for the
+  // use_dsp pragma.
+  localparam int UseDsp = CounterWidth < 49 ? "yes" : "no";
+  (* use_dsp = UseDsp *) logic [CounterWidth-1:0] counter_q;
 `else
+  localparam int UseDsp = "no";
   logic [CounterWidth-1:0] counter_q;
-
-  `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni
 `endif
 
-  // Counter flop
-  always_ff @(`COUNTER_FLOP_RST) begin
-    if (!rst_ni) begin
-      counter_q <= '0;
-    end else begin
-      counter_q <= counter_d;
+  if (UseDsp == "yes") begin : g_cnt_dsp
+    // Use sync. reset for DSP.
+    always_ff @(posedge clk_i) begin
+      if (!rst_ni) begin
+        counter_q <= '0;
+      end else begin
+        counter_q <= counter_d;
+      end
+    end
+  end else begin : g_cnt_no_dsp
+    // Use async. reset for flop.
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+        counter_q <= '0;
+      end else begin
+        counter_q <= counter_d;
+      end
     end
   end
 
+
   if (CounterWidth < 64) begin : g_counter_narrow
     logic [63:CounterWidth] unused_counter_load;
 
@@ -94,6 +109,3 @@ module ibex_counter #(
   assign counter_val_o = counter;
 
 endmodule
-
-// Keep helper defines file-local.
-`undef COUNTER_FLOP_RST
diff --git a/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv b/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
index 06a46565..cc8fc700 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
@@ -10,20 +10,23 @@
 `include "prim_assert.sv"
 
 module ibex_cs_registers #(
-  parameter bit               DbgTriggerEn      = 0,
-  parameter int unsigned      DbgHwBreakNum     = 1,
-  parameter bit               DataIndTiming     = 1'b0,
-  parameter bit               DummyInstructions = 1'b0,
-  parameter bit               ShadowCSR         = 1'b0,
-  parameter bit               ICache            = 1'b0,
-  parameter int unsigned      MHPMCounterNum    = 10,
-  parameter int unsigned      MHPMCounterWidth  = 40,
-  parameter bit               PMPEnable         = 0,
-  parameter int unsigned      PMPGranularity    = 0,
-  parameter int unsigned      PMPNumRegions     = 4,
-  parameter bit               RV32E             = 0,
-  parameter ibex_pkg::rv32m_e RV32M             = ibex_pkg::RV32MFast,
-  parameter ibex_pkg::rv32b_e RV32B             = ibex_pkg::RV32BNone
+  parameter bit                     DbgTriggerEn      = 0,
+  parameter int unsigned            DbgHwBreakNum     = 1,
+  parameter bit                     DataIndTiming     = 1'b0,
+  parameter bit                     DummyInstructions = 1'b0,
+  parameter bit                     ShadowCSR         = 1'b0,
+  parameter bit                     ICache            = 1'b0,
+  parameter int unsigned            MHPMCounterNum    = 10,
+  parameter int unsigned            MHPMCounterWidth  = 40,
+  parameter bit                     PMPEnable         = 0,
+  parameter int unsigned            PMPGranularity    = 0,
+  parameter int unsigned            PMPNumRegions     = 4,
+  parameter ibex_pkg::pmp_cfg_t     PMPRstCfg[16]     = ibex_pkg::PmpCfgRst,
+  parameter logic [33:0]            PMPRstAddr[16]    = ibex_pkg::PmpAddrRst,
+  parameter ibex_pkg::pmp_mseccfg_t PMPRstMsecCfg     = ibex_pkg::PmpMseccfgRst,
+  parameter bit                     RV32E             = 0,
+  parameter ibex_pkg::rv32m_e RV32M                   = ibex_pkg::RV32MFast,
+  parameter ibex_pkg::rv32b_e RV32B                   = ibex_pkg::RV32BNone
 ) (
   // Clock and Reset
   input  logic                 clk_i,
@@ -1073,13 +1076,6 @@ module ibex_cs_registers #(
   // -----------------
 
   if (PMPEnable) begin : g_pmp_registers
-    // PMP reset values
-    `ifdef IBEX_CUSTOM_PMP_RESET_VALUES
-      `include "ibex_pmp_reset.svh"
-    `else
-      `include "ibex_pmp_reset_default.svh"
-    `endif
-
     pmp_mseccfg_t                pmp_mseccfg_q, pmp_mseccfg_d;
     logic                        pmp_mseccfg_we;
     logic                        pmp_mseccfg_err;
@@ -1168,7 +1164,7 @@ module ibex_cs_registers #(
       ibex_csr #(
         .Width     ($bits(pmp_cfg_t)),
         .ShadowCopy(ShadowCSR),
-        .ResetValue(pmp_cfg_rst[i])
+        .ResetValue(PMPRstCfg[i])
       ) u_pmp_cfg_csr (
         .clk_i     (clk_i),
         .rst_ni    (rst_ni),
@@ -1203,7 +1199,7 @@ module ibex_cs_registers #(
       ibex_csr #(
         .Width     (PMPAddrWidth),
         .ShadowCopy(ShadowCSR),
-        .ResetValue(pmp_addr_rst[i][33-:PMPAddrWidth])
+        .ResetValue(PMPRstAddr[i][33-:PMPAddrWidth])
       ) u_pmp_addr_csr (
         .clk_i     (clk_i),
         .rst_ni    (rst_ni),
@@ -1213,7 +1209,7 @@ module ibex_cs_registers #(
         .rd_error_o(pmp_addr_err[i])
       );
 
-      `ASSERT_INIT(PMPAddrRstLowBitsZero_A, pmp_addr_rst[i][33-PMPAddrWidth:0] == '0)
+      `ASSERT_INIT(PMPAddrRstLowBitsZero_A, PMPRstAddr[i][33-PMPAddrWidth:0] == '0)
 
       assign csr_pmp_cfg_o[i]  = pmp_cfg[i];
       assign csr_pmp_addr_o[i] = {pmp_addr_rdata[i], 2'b00};
@@ -1236,7 +1232,7 @@ module ibex_cs_registers #(
     ibex_csr #(
       .Width     ($bits(pmp_mseccfg_t)),
       .ShadowCopy(ShadowCSR),
-      .ResetValue(pmp_mseccfg_rst)
+      .ResetValue(PMPRstMsecCfg)
     ) u_pmp_mseccfg (
       .clk_i     (clk_i),
       .rst_ni    (rst_ni),
diff --git a/vendor/lowrisc_ibex/rtl/ibex_decoder.sv b/vendor/lowrisc_ibex/rtl/ibex_decoder.sv
index 4b019593..6e925f56 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_decoder.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_decoder.sv
@@ -83,6 +83,7 @@ module ibex_decoder #(
   // CSRs
   output logic                 csr_access_o,          // access to CSR
   output ibex_pkg::csr_op_e    csr_op_o,              // operation to perform on CSR
+  output ibex_pkg::csr_num_e   csr_addr_o,            // CSR address
 
   // LSU
   output logic                 data_req_o,            // start transaction to data memory
@@ -138,6 +139,8 @@ module ibex_decoder #(
   assign imm_u_type_o = { instr[31:12], 12'b0 };
   assign imm_j_type_o = { {12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 };
 
+  assign csr_addr_o = csr_num_e'(instr[31:20]);
+
   // immediate for CSR manipulation (zero extended)
   assign zimm_rs1_type_o = { 27'b0, instr_rs1 }; // rs1
 
@@ -1168,9 +1171,10 @@ module ibex_decoder #(
           alu_op_b_mux_sel_o = OP_B_IMM;
         end else begin
           // instruction to read/modify CSR
-          alu_op_b_mux_sel_o = OP_B_IMM;
           imm_a_mux_sel_o    = IMM_A_Z;
-          imm_b_mux_sel_o    = IMM_B_I;  // CSR address is encoded in I imm
+
+          // No need for operand/immediate B mux selection. The CSR address is fed out as csr_addr_o
+          // as the CSR address always comes from the same field in the instruction.
 
           if (instr_alu[14]) begin
             // rs1 field is used as immediate
diff --git a/vendor/lowrisc_ibex/rtl/ibex_ex_block.sv b/vendor/lowrisc_ibex/rtl/ibex_ex_block.sv
index ee900164..c44a9316 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_ex_block.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_ex_block.sv
@@ -196,4 +196,22 @@ module ibex_ex_block #(
   // final cycle of ALU operation).
   assign ex_valid_o = multdiv_sel ? multdiv_valid : ~(|alu_imd_val_we);
 
+`ifdef INC_ASSERT
+  // This is intended to be accessed via hierarchal references so isn't output from this module nor
+  // used in any logic in this module
+  logic sva_multdiv_fsm_idle;
+
+  if (RV32M == RV32MSlow) begin : gen_multdiv_sva_idle_slow
+    assign sva_multdiv_fsm_idle = gen_multdiv_slow.multdiv_i.sva_fsm_idle;
+  end else if (RV32M == RV32MFast || RV32M == RV32MSingleCycle) begin : gen_multdiv_sva_idle_fast
+    assign sva_multdiv_fsm_idle = gen_multdiv_fast.multdiv_i.sva_fsm_idle;
+  end else begin : gen_multdiv_sva_idle_none
+    assign sva_multdiv_fsm_idle = 1'b1;
+  end
+
+  // Mark the sva_multdiv_fsm_idle as unused to avoid lint issues
+  logic unused_sva_multdiv_fsm_idle;
+  assign unused_sva_multdiv_fsm_idle = sva_multdiv_fsm_idle;
+`endif
+
 endmodule
diff --git a/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv b/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
index 95b4fa9b..43f7762f 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
@@ -95,6 +95,7 @@ module ibex_id_stage #(
   // CSR
   output logic                      csr_access_o,
   output ibex_pkg::csr_op_e         csr_op_o,
+  output ibex_pkg::csr_num_e        csr_addr_o,
   output logic                      csr_op_en_o,
   output logic                      csr_save_if_o,
   output logic                      csr_save_id_o,
@@ -135,6 +136,9 @@ module ibex_id_stage #(
   input  logic                      lsu_store_err_i,
   input  logic                      lsu_store_resp_intg_err_i,
 
+  output logic                      expecting_load_resp_o,
+  output logic                      expecting_store_resp_o,
+
   // Debug Signal
   output logic                      debug_mode_o,
   output logic                      debug_mode_entering_o,
@@ -287,6 +291,7 @@ module ibex_id_stage #(
   logic        data_req_allowed;
 
   // CSR control
+  logic        no_flush_csr_addr;
   logic        csr_pipe_flush;
 
   logic [31:0] alu_operand_a;
@@ -494,6 +499,7 @@ module ibex_id_stage #(
     // CSRs
     .csr_access_o(csr_access_o),
     .csr_op_o    (csr_op_o),
+    .csr_addr_o  (csr_addr_o),
 
     // LSU
     .data_req_o           (lsu_req_dec),
@@ -506,36 +512,20 @@ module ibex_id_stage #(
     .branch_in_dec_o(branch_in_dec)
   );
 
-  /////////////////////////////////
-  // CSR-related pipeline flushes //
-  /////////////////////////////////
-  always_comb begin : csr_pipeline_flushes
-    csr_pipe_flush = 1'b0;
-
-    // A pipeline flush is needed to let the controller react after modifying certain CSRs:
-    // - When enabling interrupts, pending IRQs become visible to the controller only during
-    //   the next cycle. If during that cycle the core disables interrupts again, it does not
-    //   see any pending IRQs and consequently does not start to handle interrupts.
-    // - When modifying any PMP CSR, PMP check of the next instruction might get invalidated.
-    //   Hence, a pipeline flush is needed to instantiate another PMP check with the updated CSRs.
-    // - When modifying debug CSRs.
-    if (csr_op_en_o == 1'b1 && (csr_op_o == CSR_OP_WRITE || csr_op_o == CSR_OP_SET)) begin
-      if (csr_num_e'(instr_rdata_i[31:20]) == CSR_MSTATUS ||
-          csr_num_e'(instr_rdata_i[31:20]) == CSR_MIE     ||
-          csr_num_e'(instr_rdata_i[31:20]) == CSR_MSECCFG ||
-          // To catch all PMPCFG/PMPADDR registers, get the shared top most 7 bits.
-          instr_rdata_i[31:25] == 7'h1D) begin
-        csr_pipe_flush = 1'b1;
-      end
-    end else if (csr_op_en_o == 1'b1 && csr_op_o != CSR_OP_READ) begin
-      if (csr_num_e'(instr_rdata_i[31:20]) == CSR_DCSR      ||
-          csr_num_e'(instr_rdata_i[31:20]) == CSR_DPC       ||
-          csr_num_e'(instr_rdata_i[31:20]) == CSR_DSCRATCH0 ||
-          csr_num_e'(instr_rdata_i[31:20]) == CSR_DSCRATCH1) begin
-        csr_pipe_flush = 1'b1;
-      end
-    end
-  end
+  // Flush pipe on most CSR modification. Some CSR modifications alter how instructions execute
+  // (e.g. the PMP CSRs) so this ensures all instructions always see the latest architectural state
+  // when entering the fetch stage. This causes some needless flushes but performance impact is
+  // limited. We have a single fetch stage to flush not many stages of a deep pipeline and CSR
+  // instructions are in general rare and not part of performance critical parts of the code.
+  //
+  // No flush is triggered for a small number of specific CSRs. These are ones that have been
+  // specifically identified to be a) likely to be modifed in exception handlers and b) safe to
+  // alter without a flush.
+  assign no_flush_csr_addr = csr_addr_o inside {CSR_MSCRATCH, CSR_MEPC};
+
+  assign csr_pipe_flush = (csr_op_en_o == 1)                                         &&
+                          (csr_op_o inside {CSR_OP_WRITE, CSR_OP_SET, CSR_OP_CLEAR}) &&
+                          !no_flush_csr_addr;
 
   ////////////////
   // Controller //
@@ -659,7 +649,7 @@ module ibex_id_stage #(
   assign lsu_sign_ext_o          = lsu_sign_ext;
   assign lsu_wdata_o             = rf_rdata_b_fwd;
   // csr_op_en_o is set when CSR access should actually happen.
-  // csv_access_o is set when CSR access instruction is present and is used to compute whether a CSR
+  // csr_access_o is set when CSR access instruction is present and is used to compute whether a CSR
   // access is illegal. A combinational loop would be created if csr_op_en_o was used along (as
   // asserting it for an illegal csr access would result in a flush that would need to deassert it).
   assign csr_op_en_o             = csr_access_o & instr_executing & instr_id_done_o;
@@ -1016,6 +1006,11 @@ module ibex_id_stage #(
 
     assign perf_dside_wait_o = instr_valid_i & ~instr_kill &
                                (outstanding_memory_access | stall_ld_hz);
+
+    // With writeback stage load/store responses are processed in the writeback stage so the ID/EX
+    // stage is never expecting a load or store response.
+    assign expecting_load_resp_o  = 1'b0;
+    assign expecting_store_resp_o = 1'b0;
   end else begin : gen_no_stall_mem
 
     assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : ex_valid_i;
@@ -1044,6 +1039,13 @@ module ibex_id_stage #(
     assign rf_rd_a_wb_match_o = 1'b0;
     assign rf_rd_b_wb_match_o = 1'b0;
 
+    // First cycle of a load or store is always the request. We're expecting a response the cycles
+    // following. Note if the request isn't immediatly accepted these signals will still assert.
+    // However in this case the LSU won't signal a response as it's still waiting for the grant
+    // (even if the external memory bus signals are glitched to generate a false response).
+    assign expecting_load_resp_o  = instr_valid_i & lsu_req_dec & ~instr_first_cycle & ~lsu_we;
+    assign expecting_store_resp_o = instr_valid_i & lsu_req_dec & ~instr_first_cycle &  lsu_we;
+
     // Unused Writeback stage only IO & wiring
     // Assign inputs and internal wiring to unused signals to satisfy lint checks
     // Tie-off outputs to constant values
@@ -1143,6 +1145,10 @@ module ibex_id_stage #(
   // includes Xs
   `ASSERT(IbexDuplicateInstrMatch, instr_valid_i |-> instr_rdata_i === instr_rdata_alu_i)
 
+  // Check that when ID stage is ready for next instruction FSM is in FIRST_CYCLE state the
+  // following cycle (when the new instructon may begin executing).
+  `ASSERT(IbexMoveToFirstCycleWhenIdReady, id_in_ready_o |=> id_fsm_q == FIRST_CYCLE)
+
   `ifdef CHECK_MISALIGNED
   `ASSERT(IbexMisalignedMemoryAccess, !lsu_addr_incr_req_i)
   `endif
diff --git a/vendor/lowrisc_ibex/rtl/ibex_lockstep.sv b/vendor/lowrisc_ibex/rtl/ibex_lockstep.sv
index 7778ff74..7466e9eb 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_lockstep.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_lockstep.sv
@@ -9,36 +9,41 @@
 
 // SEC_CM: LOGIC.SHADOW
 module ibex_lockstep import ibex_pkg::*; #(
-  parameter int unsigned LockstepOffset    = 2,
-  parameter bit          PMPEnable         = 1'b0,
-  parameter int unsigned PMPGranularity    = 0,
-  parameter int unsigned PMPNumRegions     = 4,
-  parameter int unsigned MHPMCounterNum    = 0,
-  parameter int unsigned MHPMCounterWidth  = 40,
-  parameter bit          RV32E             = 1'b0,
-  parameter rv32m_e      RV32M             = RV32MFast,
-  parameter rv32b_e      RV32B             = RV32BNone,
-  parameter bit          BranchTargetALU   = 1'b0,
-  parameter bit          WritebackStage    = 1'b0,
-  parameter bit          ICache            = 1'b0,
-  parameter bit          ICacheECC         = 1'b0,
-  parameter int unsigned BusSizeECC        = BUS_SIZE,
-  parameter int unsigned TagSizeECC        = IC_TAG_SIZE,
-  parameter int unsigned LineSizeECC       = IC_LINE_SIZE,
-  parameter bit          BranchPredictor   = 1'b0,
-  parameter bit          DbgTriggerEn      = 1'b0,
-  parameter int unsigned DbgHwBreakNum     = 1,
-  parameter bit          ResetAll          = 1'b0,
-  parameter lfsr_seed_t  RndCnstLfsrSeed   = RndCnstLfsrSeedDefault,
-  parameter lfsr_perm_t  RndCnstLfsrPerm   = RndCnstLfsrPermDefault,
-  parameter bit          SecureIbex        = 1'b0,
-  parameter bit          DummyInstructions = 1'b0,
-  parameter bit          RegFileECC        = 1'b0,
-  parameter int unsigned RegFileDataWidth  = 32,
-  parameter bit          MemECC            = 1'b0,
-  parameter int unsigned MemDataWidth      = MemECC ? 32 + 7 : 32,
-  parameter int unsigned DmHaltAddr        = 32'h1A110800,
-  parameter int unsigned DmExceptionAddr   = 32'h1A110808
+  parameter int unsigned            LockstepOffset    = 2,
+  parameter bit                     PMPEnable         = 1'b0,
+  parameter int unsigned            PMPGranularity    = 0,
+  parameter int unsigned            PMPNumRegions     = 4,
+  parameter ibex_pkg::pmp_cfg_t     PMPRstCfg[16]     = ibex_pkg::PmpCfgRst,
+  parameter logic [33:0]            PMPRstAddr[16]    = ibex_pkg::PmpAddrRst,
+  parameter ibex_pkg::pmp_mseccfg_t PMPRstMsecCfg     = ibex_pkg::PmpMseccfgRst,
+  parameter int unsigned            MHPMCounterNum    = 0,
+  parameter int unsigned            MHPMCounterWidth  = 40,
+  parameter bit                     RV32E             = 1'b0,
+  parameter rv32m_e                 RV32M             = RV32MFast,
+  parameter rv32b_e                 RV32B             = RV32BNone,
+  parameter bit                     BranchTargetALU   = 1'b0,
+  parameter bit                     WritebackStage    = 1'b0,
+  parameter bit                     ICache            = 1'b0,
+  parameter bit                     ICacheECC         = 1'b0,
+  parameter int unsigned            BusSizeECC        = BUS_SIZE,
+  parameter int unsigned            TagSizeECC        = IC_TAG_SIZE,
+  parameter int unsigned            LineSizeECC       = IC_LINE_SIZE,
+  parameter bit                     BranchPredictor   = 1'b0,
+  parameter bit                     DbgTriggerEn      = 1'b0,
+  parameter int unsigned            DbgHwBreakNum     = 1,
+  parameter bit                     ResetAll          = 1'b0,
+  parameter lfsr_seed_t             RndCnstLfsrSeed   = RndCnstLfsrSeedDefault,
+  parameter lfsr_perm_t             RndCnstLfsrPerm   = RndCnstLfsrPermDefault,
+  parameter bit                     SecureIbex        = 1'b0,
+  parameter bit                     DummyInstructions = 1'b0,
+  parameter bit                     RegFileECC        = 1'b0,
+  parameter int unsigned            RegFileDataWidth  = 32,
+  parameter bit                     MemECC            = 1'b0,
+  parameter int unsigned            MemDataWidth      = MemECC ? 32 + 7 : 32,
+  parameter int unsigned            DmBaseAddr        = 32'h1A110000,
+  parameter int unsigned            DmAddrMask        = 32'h00000FFF,
+  parameter int unsigned            DmHaltAddr        = 32'h1A110800,
+  parameter int unsigned            DmExceptionAddr   = 32'h1A110808
 ) (
   input  logic                         clk_i,
   input  logic                         rst_ni,
@@ -120,33 +125,51 @@ module ibex_lockstep import ibex_pkg::*; #(
   // - The reset of the shadow core is synchronously released.
   // The comparison is started in the following clock cycle.
 
-  logic [LockstepOffsetW-1:0] rst_shadow_cnt_d, rst_shadow_cnt_q, rst_shadow_cnt_incr;
-  // Internally generated resets cause IMPERFECTSCH warnings
-  /* verilator lint_off IMPERFECTSCH */
-  logic                       rst_shadow_set_d, rst_shadow_set_q;
-  logic                       rst_shadow_n, enable_cmp_q;
-  /* verilator lint_on IMPERFECTSCH */
+  logic [LockstepOffsetW-1:0] rst_shadow_cnt;
+  logic                       rst_shadow_cnt_err;
+  ibex_mubi_t                 rst_shadow_set_d, rst_shadow_set_q;
+  logic                       rst_shadow_n, rst_shadow_set_single_bit;
+  ibex_mubi_t                 enable_cmp_d, enable_cmp_q;
+
+  // This counter primitive starts counting to LockstepOffset after a system
+  // reset. The counter value saturates at LockstepOffset.
+  prim_count #(
+    .Width      (LockstepOffsetW        ),
+    .ResetValue (LockstepOffsetW'(1'b0) )
+  ) u_rst_shadow_cnt (
+    .clk_i              (clk_i                  ),
+    .rst_ni             (rst_ni                 ),
+    .clr_i              (1'b0                   ),
+    .set_i              (1'b0                   ),
+    .set_cnt_i          ('0                     ),
+    .incr_en_i          (1'b1                   ),
+    .decr_en_i          (1'b0                   ),
+    .step_i             (LockstepOffsetW'(1'b1) ),
+    .commit_i           (1'b1                   ),
+    .cnt_o              (rst_shadow_cnt         ),
+    .cnt_after_commit_o (                       ),
+    .err_o              (rst_shadow_cnt_err     )
+  );
 
-  assign rst_shadow_cnt_incr = rst_shadow_cnt_q + 1'b1;
+  // When the LockstepOffset counter value is reached, activate the lockstep
+  // comparison. We do not explicitly check whether rst_shadow_set_q forms a valid
+  // multibit signal as this value is implicitly checked by the enable_cmp
+  // comparison below.
+  assign rst_shadow_set_d =
+    (rst_shadow_cnt >= LockstepOffsetW'(LockstepOffset - 1)) ? IbexMuBiOn : IbexMuBiOff;
 
-  assign rst_shadow_set_d = (rst_shadow_cnt_q == LockstepOffsetW'(LockstepOffset - 1));
-  assign rst_shadow_cnt_d = rst_shadow_set_d ? rst_shadow_cnt_q : rst_shadow_cnt_incr;
+  // Enable lockstep comparison.
+  assign enable_cmp_d = rst_shadow_set_q;
 
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      rst_shadow_cnt_q <= '0;
-      enable_cmp_q     <= '0;
-    end else begin
-      rst_shadow_cnt_q <= rst_shadow_cnt_d;
-      enable_cmp_q     <= rst_shadow_set_q;
-    end
-  end
+  // This assignment is needed in order to avoid "Warning-IMPERFECTSCH" messages.
+  // TODO: Remove when updating Verilator #2134.
+  assign rst_shadow_set_single_bit = rst_shadow_set_q[0];
 
   // The primitives below are used to place size-only constraints in order to prevent
   // synthesis optimizations and preserve anchor points for constraining backend tools.
   prim_flop #(
-    .Width(1),
-    .ResetValue(1'b0)
+    .Width(IbexMuBiWidth),
+    .ResetValue(IbexMuBiOff)
   ) u_prim_rst_shadow_set_flop (
     .clk_i (clk_i),
     .rst_ni(rst_ni),
@@ -154,10 +177,20 @@ module ibex_lockstep import ibex_pkg::*; #(
     .q_o   (rst_shadow_set_q)
   );
 
+  prim_flop #(
+    .Width(IbexMuBiWidth),
+    .ResetValue(IbexMuBiOff)
+  ) u_prim_enable_cmp_flop (
+    .clk_i (clk_i),
+    .rst_ni(rst_ni),
+    .d_i   (enable_cmp_d),
+    .q_o   (enable_cmp_q)
+  );
+
   prim_clock_mux2 #(
     .NoFpgaBufG(1'b1)
   ) u_prim_rst_shadow_n_mux2 (
-    .clk0_i(rst_shadow_set_q),
+    .clk0_i(rst_shadow_set_single_bit),
     .clk1_i(scan_rst_ni),
     .sel_i (test_en_i),
     .clk_o (rst_shadow_n)
@@ -319,6 +352,9 @@ module ibex_lockstep import ibex_pkg::*; #(
     .PMPEnable         ( PMPEnable         ),
     .PMPGranularity    ( PMPGranularity    ),
     .PMPNumRegions     ( PMPNumRegions     ),
+    .PMPRstCfg         ( PMPRstCfg         ),
+    .PMPRstAddr        ( PMPRstAddr        ),
+    .PMPRstMsecCfg     ( PMPRstMsecCfg     ),
     .MHPMCounterNum    ( MHPMCounterNum    ),
     .MHPMCounterWidth  ( MHPMCounterWidth  ),
     .RV32E             ( RV32E             ),
@@ -343,6 +379,8 @@ module ibex_lockstep import ibex_pkg::*; #(
     .RegFileDataWidth  ( RegFileDataWidth  ),
     .MemECC            ( MemECC            ),
     .MemDataWidth      ( MemDataWidth      ),
+    .DmBaseAddr        ( DmBaseAddr        ),
+    .DmAddrMask        ( DmAddrMask        ),
     .DmHaltAddr        ( DmHaltAddr        ),
     .DmExceptionAddr   ( DmExceptionAddr   )
   ) u_shadow_core (
@@ -427,7 +465,8 @@ module ibex_lockstep import ibex_pkg::*; #(
     .rvfi_mem_wmask            (),
     .rvfi_mem_rdata            (),
     .rvfi_mem_wdata            (),
-    .rvfi_ext_mip              (),
+    .rvfi_ext_pre_mip          (),
+    .rvfi_ext_post_mip         (),
     .rvfi_ext_nmi              (),
     .rvfi_ext_nmi_int          (),
     .rvfi_ext_debug_req        (),
@@ -458,8 +497,10 @@ module ibex_lockstep import ibex_pkg::*; #(
 
   logic outputs_mismatch;
 
-  assign outputs_mismatch       = enable_cmp_q & (shadow_outputs_q != core_outputs_q[0]);
-  assign alert_major_internal_o = outputs_mismatch | shadow_alert_major_internal;
+  assign outputs_mismatch =
+    (enable_cmp_q != IbexMuBiOff) & (shadow_outputs_q != core_outputs_q[0]);
+  assign alert_major_internal_o
+    = outputs_mismatch | shadow_alert_major_internal | rst_shadow_cnt_err;
   assign alert_major_bus_o      = shadow_alert_major_bus;
   assign alert_minor_o          = shadow_alert_minor;
 
diff --git a/vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv b/vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv
index 3f0d27ac..2e48dc52 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_multdiv_fast.sv
@@ -84,6 +84,9 @@ module ibex_multdiv_fast #(
   logic        mult_en_internal;
   logic        div_en_internal;
 
+  // Used for SVA purposes, no functional relevance
+  logic        sva_mul_fsm_idle;
+
   typedef enum logic [2:0] {
     MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH
   } md_fsm_e;
@@ -254,6 +257,8 @@ module ibex_multdiv_fast #(
     // States must be knwon/valid.
     `ASSERT_KNOWN(IbexMultStateKnown, mult_state_q)
 
+    assign sva_mul_fsm_idle = mult_state_q == MULL;
+
   // The fast multiplier uses one 17 bit multiplier to compute MUL instructions in 3 cycles
   // and MULH instructions in 4 cycles.
   end else begin : gen_mult_fast
@@ -372,6 +377,8 @@ module ibex_multdiv_fast #(
     // States must be knwon/valid.
     `ASSERT_KNOWN(IbexMultStateKnown, mult_state_q)
 
+    assign sva_mul_fsm_idle = mult_state_q == ALBL;
+
   end // gen_mult_fast
 
   // Divider
@@ -518,12 +525,28 @@ module ibex_multdiv_fast #(
     endcase // md_state_q
   end
 
+
   assign valid_o = mult_valid | div_valid;
 
   // States must be knwon/valid.
   `ASSERT(IbexMultDivStateValid, md_state_q inside {
       MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH})
 
+`ifdef INC_ASSERT
+  logic sva_fsm_idle;
+  logic unused_sva_fsm_idle;
+
+  // This is intended to be accessed via hierarchal references so isn't output from this module nor
+  // used in any logic in this module
+  assign sva_fsm_idle = (md_state_q == MD_IDLE) && sva_mul_fsm_idle;
+  // Mark the sva_fsm_idle as unused to avoid lint issues
+  assign unused_sva_fsm_idle = sva_fsm_idle;
+`else
+  logic unused_sva_mul_fsm_idle;
+
+  assign unused_sva_mul_fsm_idle = sva_mul_fsm_idle;
+`endif
+
 `ifdef FORMAL
   `ifdef YOSYS
     `include "formal_tb_frag.svh"
diff --git a/vendor/lowrisc_ibex/rtl/ibex_multdiv_slow.sv b/vendor/lowrisc_ibex/rtl/ibex_multdiv_slow.sv
index 214d3f59..c409e296 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_multdiv_slow.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_multdiv_slow.sv
@@ -327,6 +327,7 @@ module ibex_multdiv_slow
     end // (mult_sel_i || div_sel_i)
   end
 
+
   //////////////////////////////////////////
   // Mutliplier / Divider state registers //
   //////////////////////////////////////////
@@ -369,6 +370,17 @@ module ibex_multdiv_slow
       MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH
       }, clk_i, !rst_ni)
 
+`ifdef INC_ASSERT
+  logic sva_fsm_idle;
+  logic unused_sva_fsm_idle;
+
+  // This is intended to be accessed via hierarchal references so isn't output from this module nor
+  // used in any logic in this module
+  assign sva_fsm_idle = (md_state_q == MD_IDLE);
+  // Mark the sva_fsm_idle as unused to avoid lint issues
+  assign unused_sva_fsm_idle = sva_fsm_idle;
+`endif
+
 `ifdef FORMAL
   `ifdef YOSYS
     `include "formal_tb_frag.svh"
diff --git a/vendor/lowrisc_ibex/rtl/ibex_pkg.sv b/vendor/lowrisc_ibex/rtl/ibex_pkg.sv
index 9a3c7faa..5a939c78 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_pkg.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_pkg.sv
@@ -655,7 +655,8 @@ package ibex_pkg;
 
   // Mult-bit signal used for security hardening. For non-secure implementation all bits other than
   // the bottom bit are ignored.
-  typedef logic [3:0] ibex_mubi_t;
+  parameter int IbexMuBiWidth = 4;
+  typedef logic [IbexMuBiWidth-1:0] ibex_mubi_t;
 
   // Note that if adjusting these parameters it is assumed the bottom bit is set for On and unset
   // for Off. This allows the use of IbexMuBiOn/IbexMuBiOff to work for both secure and non-secure
@@ -663,4 +664,54 @@ package ibex_pkg;
   // and core_busy signals within `ibex_core` may need adjusting.
   parameter ibex_mubi_t IbexMuBiOn  = 4'b0101;
   parameter ibex_mubi_t IbexMuBiOff = 4'b1010;
+
+  // Default reset values for PMP CSRs. Where the number of regions
+  // (PMPNumRegions) is less than 16 the reset values for the higher numbered
+  // regions are ignored.
+  //
+  // See the Ibex Reference Guide (Custom Reset Values under Physical Memory
+  // Protection) for more information.
+
+  parameter pmp_cfg_t PmpCfgRst[16] = '{
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 0
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 1
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 2
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 3
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 4
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 5
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 6
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 7
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 8
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 9
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 10
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 11
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 12
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 13
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 14
+    '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}  // region 15
+  };
+
+  // Addresses are given in byte granularity for readibility. A minimum of two
+  // bits will be stripped off the bottom (PMPGranularity == 0) with more stripped
+  // off at coarser granularities.
+  parameter logic [33:0] PmpAddrRst[16] = '{
+    34'h0, // region 0
+    34'h0, // region 1
+    34'h0, // region 2
+    34'h0, // region 3
+    34'h0, // region 4
+    34'h0, // region 5
+    34'h0, // region 6
+    34'h0, // region 7
+    34'h0, // region 8
+    34'h0, // region 9
+    34'h0, // region 10
+    34'h0, // region 11
+    34'h0, // region 12
+    34'h0, // region 13
+    34'h0, // region 14
+    34'h0  // region 15
+  };
+
+  parameter pmp_mseccfg_t PmpMseccfgRst = '{rlb : 1'b0, mmwp: 1'b0, mml: 1'b0};
 endpackage
diff --git a/vendor/lowrisc_ibex/rtl/ibex_pmp.sv b/vendor/lowrisc_ibex/rtl/ibex_pmp.sv
index 48c3a7ed..d3561200 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_pmp.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_pmp.sv
@@ -5,6 +5,8 @@
 `include "dv_fcov_macros.svh"
 
 module ibex_pmp #(
+  parameter int unsigned DmBaseAddr     = 32'h1A110000,
+  parameter int unsigned DmAddrMask     = 32'h00000FFF,
   // Granularity of NAPOT access,
   // 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.
   parameter int unsigned PMPGranularity = 0,
@@ -18,6 +20,8 @@ module ibex_pmp #(
   input  logic [33:0]             csr_pmp_addr_i    [PMPNumRegions],
   input  ibex_pkg::pmp_mseccfg_t  csr_pmp_mseccfg_i,
 
+  input  logic                    debug_mode_i,
+
   input  ibex_pkg::priv_lvl_e     priv_mode_i    [PMPNumChan],
   // Access checking channels
   input  logic [33:0]             pmp_req_addr_i [PMPNumChan],
@@ -37,6 +41,7 @@ module ibex_pmp #(
   logic [PMPNumChan-1:0][PMPNumRegions-1:0]   region_match_all;
   logic [PMPNumChan-1:0][PMPNumRegions-1:0]   region_basic_perm_check;
   logic [PMPNumChan-1:0][PMPNumRegions-1:0]   region_perm_check;
+  logic [PMPNumChan-1:0]                      debug_mode_allowed_access;
 
   ///////////////////////
   // Functions for PMP //
@@ -48,6 +53,7 @@ module ibex_pmp #(
   //                                                                                 |
   // region_match_all --------------------------------> access_fault_check <----------
   //                                                            |
+  // !debug_mode_allowed_access ------------------------------> &
   //                                                            \--> pmp_req_err_o
 
   // Compute permissions checks that apply when MSECCFG.MML is set. Added for Smepmp support.
@@ -226,9 +232,18 @@ module ibex_pmp #(
                              pmp_req_addr_i[c][PMPGranularity+2-1:0]};
     end
 
+    // Determine whether the core is in debug mode and the access is to an address in the range of
+    // the Debug Module. According to Section A.2 of the RISC-V Debug Specification, the PMP must
+    // not disallow fetches, loads, or stores in the address range associated with the Debug Module
+    // when the hart is in debug mode.
+    assign debug_mode_allowed_access[c] = debug_mode_i &
+                                          ((pmp_req_addr_i[c][31:0] & ~DmAddrMask) == DmBaseAddr);
+
     // Once the permission checks of the regions are done, decide if the access is
     // denied by figuring out the matching region and its permission check.
-    assign pmp_req_err_o[c] = access_fault_check(csr_pmp_mseccfg_i.mmwp,
+    // No error is raised if the access is allowed as Debug Module access (first term).
+    assign pmp_req_err_o[c] = ~debug_mode_allowed_access[c] &
+                              access_fault_check(csr_pmp_mseccfg_i.mmwp,
                                                  csr_pmp_mseccfg_i.mml,
                                                  pmp_req_type_i[c],
                                                  region_match_all[c],
diff --git a/vendor/lowrisc_ibex/rtl/ibex_pmp_reset_default.svh b/vendor/lowrisc_ibex/rtl/ibex_pmp_reset_default.svh
deleted file mode 100644
index cda701b3..00000000
--- a/vendor/lowrisc_ibex/rtl/ibex_pmp_reset_default.svh
+++ /dev/null
@@ -1,53 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-// Default reset values for PMP CSRs. Where the number of regions
-// (PMPNumRegions) is less than 16 the reset values for the higher numbered
-// regions are ignored.
-//
-// See the Ibex Reference Guide (Custom Reset Values under Physical Memory
-// Protection) for more information.
-
-localparam pmp_cfg_t pmp_cfg_rst[16] = '{
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 0
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 1
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 2
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 3
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 4
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 5
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 6
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 7
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 8
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 9
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 10
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 11
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 12
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 13
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 14
-  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}  // region 15
-};
-
-// Addresses are given in byte granularity for readibility. A minimum of two
-// bits will be stripped off the bottom (PMPGranularity == 0) with more stripped
-// off at coarser granularities.
-localparam [33:0] pmp_addr_rst[16] = '{
-  34'h0, // region 0
-  34'h0, // region 1
-  34'h0, // region 2
-  34'h0, // region 3
-  34'h0, // region 4
-  34'h0, // region 5
-  34'h0, // region 6
-  34'h0, // region 7
-  34'h0, // region 8
-  34'h0, // region 9
-  34'h0, // region 10
-  34'h0, // region 11
-  34'h0, // region 12
-  34'h0, // region 13
-  34'h0, // region 14
-  34'h0  // region 15
-};
-
-localparam pmp_mseccfg_t pmp_mseccfg_rst = '{rlb : 1'b0, mmwp: 1'b0, mml: 1'b0};
diff --git a/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv b/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv
index 7a0ae34b..65698d1c 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv
@@ -147,14 +147,14 @@ module ibex_register_file_fpga #(
       .out_o (mem_o_b)
     );
 
-    assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem_o_a;
-    assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem_o_b;
+    assign rdata_a_o = (raddr_a_i == '0) ? WordZeroVal : mem_o_a;
+    assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem_o_b;
   end else begin : gen_no_rdata_mux_check
-    // async_read a
-    assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem[raddr_a_i];
+    assign rdata_a_o = (raddr_a_i == '0) ? WordZeroVal : mem[raddr_a_i];
+    assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem[raddr_b_i];
 
-    // async_read b
-    assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem[raddr_b_i];
+    assign oh_raddr_a_err = 1'b0;
+    assign oh_raddr_b_err = 1'b0;
   end
 
   // we select
diff --git a/vendor/lowrisc_ibex/rtl/ibex_register_file_latch.sv b/vendor/lowrisc_ibex/rtl/ibex_register_file_latch.sv
index 4c295e2e..375da414 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_register_file_latch.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_register_file_latch.sv
@@ -118,7 +118,7 @@ module ibex_register_file_latch #(
       .clk_i,
       .rst_ni,
       .oh_i   (raddr_onehot_a_buf),
-      .addr_i (raddr_b_int),
+      .addr_i (raddr_a_int),
       // Set enable=1 as address is always valid.
       .en_i   (1'b1),
       .err_o  (oh_raddr_a_err)
diff --git a/vendor/lowrisc_ibex/rtl/ibex_top.sv b/vendor/lowrisc_ibex/rtl/ibex_top.sv
index dff77b0c..a90fee0e 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_top.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_top.sv
@@ -13,31 +13,37 @@
  * Top level module of the ibex RISC-V core
  */
 module ibex_top import ibex_pkg::*; #(
-  parameter bit          PMPEnable        = 1'b0,
-  parameter int unsigned PMPGranularity   = 0,
-  parameter int unsigned PMPNumRegions    = 4,
-  parameter int unsigned MHPMCounterNum   = 0,
-  parameter int unsigned MHPMCounterWidth = 40,
-  parameter bit          RV32E            = 1'b0,
-  parameter rv32m_e      RV32M            = RV32MFast,
-  parameter rv32b_e      RV32B            = RV32BNone,
-  parameter regfile_e    RegFile          = RegFileFF,
-  parameter bit          BranchTargetALU  = 1'b0,
-  parameter bit          WritebackStage   = 1'b0,
-  parameter bit          ICache           = 1'b0,
-  parameter bit          ICacheECC        = 1'b0,
-  parameter bit          BranchPredictor  = 1'b0,
-  parameter bit          DbgTriggerEn     = 1'b0,
-  parameter int unsigned DbgHwBreakNum    = 1,
-  parameter bit          SecureIbex       = 1'b0,
-  parameter bit          ICacheScramble   = 1'b0,
-  parameter lfsr_seed_t  RndCnstLfsrSeed  = RndCnstLfsrSeedDefault,
-  parameter lfsr_perm_t  RndCnstLfsrPerm  = RndCnstLfsrPermDefault,
-  parameter int unsigned DmHaltAddr       = 32'h1A110800,
-  parameter int unsigned DmExceptionAddr  = 32'h1A110808,
+  parameter bit                     PMPEnable                    = 1'b0,
+  parameter int unsigned            PMPGranularity               = 0,
+  parameter int unsigned            PMPNumRegions                = 4,
+  parameter int unsigned            MHPMCounterNum               = 0,
+  parameter int unsigned            MHPMCounterWidth             = 40,
+  parameter ibex_pkg::pmp_cfg_t     PMPRstCfg[16]                = ibex_pkg::PmpCfgRst,
+  parameter logic [33:0]            PMPRstAddr[16]               = ibex_pkg::PmpAddrRst,
+  parameter ibex_pkg::pmp_mseccfg_t PMPRstMsecCfg                = ibex_pkg::PmpMseccfgRst,
+  parameter bit                     RV32E                        = 1'b0,
+  parameter rv32m_e                 RV32M                        = RV32MFast,
+  parameter rv32b_e                 RV32B                        = RV32BNone,
+  parameter regfile_e               RegFile                      = RegFileFF,
+  parameter bit                     BranchTargetALU              = 1'b0,
+  parameter bit                     WritebackStage               = 1'b0,
+  parameter bit                     ICache                       = 1'b0,
+  parameter bit                     ICacheECC                    = 1'b0,
+  parameter bit                     BranchPredictor              = 1'b0,
+  parameter bit                     DbgTriggerEn                 = 1'b0,
+  parameter int unsigned            DbgHwBreakNum                = 1,
+  parameter bit                     SecureIbex                   = 1'b0,
+  parameter bit                     ICacheScramble               = 1'b0,
+  parameter int unsigned            ICacheScrNumPrinceRoundsHalf = 2,
+  parameter lfsr_seed_t             RndCnstLfsrSeed              = RndCnstLfsrSeedDefault,
+  parameter lfsr_perm_t             RndCnstLfsrPerm              = RndCnstLfsrPermDefault,
+  parameter int unsigned            DmBaseAddr                   = 32'h1A110000,
+  parameter int unsigned            DmAddrMask                   = 32'h00000FFF,
+  parameter int unsigned            DmHaltAddr                   = 32'h1A110800,
+  parameter int unsigned            DmExceptionAddr              = 32'h1A110808,
   // Default seed and nonce for scrambling
-  parameter logic [SCRAMBLE_KEY_W-1:0]   RndCnstIbexKey   = RndCnstIbexKeyDefault,
-  parameter logic [SCRAMBLE_NONCE_W-1:0] RndCnstIbexNonce = RndCnstIbexNonceDefault
+  parameter logic [SCRAMBLE_KEY_W-1:0]   RndCnstIbexKey          = RndCnstIbexKeyDefault,
+  parameter logic [SCRAMBLE_NONCE_W-1:0] RndCnstIbexNonce        = RndCnstIbexNonceDefault
 ) (
   // Clock and Reset
   input  logic                         clk_i,
@@ -116,7 +122,8 @@ module ibex_top import ibex_pkg::*; #(
   output logic [ 3:0]                  rvfi_mem_wmask,
   output logic [31:0]                  rvfi_mem_rdata,
   output logic [31:0]                  rvfi_mem_wdata,
-  output logic [31:0]                  rvfi_ext_mip,
+  output logic [31:0]                  rvfi_ext_pre_mip,
+  output logic [31:0]                  rvfi_ext_post_mip,
   output logic                         rvfi_ext_nmi,
   output logic                         rvfi_ext_nmi_int,
   output logic                         rvfi_ext_debug_req,
@@ -155,7 +162,6 @@ module ibex_top import ibex_pkg::*; #(
   localparam int unsigned TagSizeECC        = ICacheECC ? (IC_TAG_SIZE + 6) : IC_TAG_SIZE;
   // Scrambling Parameter
   localparam int unsigned NumAddrScrRounds  = ICacheScramble ? 2 : 0;
-  localparam int unsigned NumDiffRounds     = NumAddrScrRounds;
 
   // Clock signals
   logic                        clk;
@@ -282,6 +288,9 @@ module ibex_top import ibex_pkg::*; #(
     .PMPEnable        (PMPEnable),
     .PMPGranularity   (PMPGranularity),
     .PMPNumRegions    (PMPNumRegions),
+    .PMPRstCfg        (PMPRstCfg),
+    .PMPRstAddr       (PMPRstAddr),
+    .PMPRstMsecCfg    (PMPRstMsecCfg),
     .MHPMCounterNum   (MHPMCounterNum),
     .MHPMCounterWidth (MHPMCounterWidth),
     .RV32E            (RV32E),
@@ -306,6 +315,8 @@ module ibex_top import ibex_pkg::*; #(
     .RegFileDataWidth (RegFileDataWidth),
     .MemECC           (MemECC),
     .MemDataWidth     (MemDataWidth),
+    .DmBaseAddr       (DmBaseAddr),
+    .DmAddrMask       (DmAddrMask),
     .DmHaltAddr       (DmHaltAddr),
     .DmExceptionAddr  (DmExceptionAddr)
   ) u_ibex_core (
@@ -390,7 +401,8 @@ module ibex_top import ibex_pkg::*; #(
     .rvfi_mem_wmask,
     .rvfi_mem_rdata,
     .rvfi_mem_wdata,
-    .rvfi_ext_mip,
+    .rvfi_ext_pre_mip,
+    .rvfi_ext_post_mip,
     .rvfi_ext_nmi,
     .rvfi_ext_nmi_int,
     .rvfi_ext_debug_req,
@@ -552,6 +564,9 @@ module ibex_top import ibex_pkg::*; #(
   // Rams Instantiation //
   ////////////////////////
 
+  logic [IC_NUM_WAYS-1:0] icache_tag_alert;
+  logic [IC_NUM_WAYS-1:0] icache_data_alert;
+
   if (ICache) begin : gen_rams
 
     for (genvar way = 0; way < IC_NUM_WAYS; way++) begin : gen_rams_inner
@@ -561,35 +576,38 @@ module ibex_top import ibex_pkg::*; #(
         // SEC_CM: ICACHE.MEM.SCRAMBLE
         // Tag RAM instantiation
         prim_ram_1p_scr #(
-          .Width            (TagSizeECC),
-          .Depth            (IC_NUM_LINES),
-          .DataBitsPerMask  (TagSizeECC),
-          .EnableParity     (0),
-          .DiffWidth        (TagSizeECC),
-          .NumAddrScrRounds (NumAddrScrRounds),
-          .NumDiffRounds    (NumDiffRounds)
+          .Width              (TagSizeECC),
+          .Depth              (IC_NUM_LINES),
+          .DataBitsPerMask    (TagSizeECC),
+          .EnableParity       (0),
+          .NumPrinceRoundsHalf(ICacheScrNumPrinceRoundsHalf),
+          .NumAddrScrRounds   (NumAddrScrRounds)
         ) tag_bank (
           .clk_i,
           .rst_ni,
 
-          .key_valid_i (scramble_key_valid_q),
-          .key_i       (scramble_key_q),
-          .nonce_i     (scramble_nonce_q),
+          .key_valid_i      (scramble_key_valid_q),
+          .key_i            (scramble_key_q),
+          .nonce_i          (scramble_nonce_q),
 
-          .req_i       (ic_tag_req[way]),
+          .req_i            (ic_tag_req[way]),
 
-          .gnt_o       (),
-          .write_i     (ic_tag_write),
-          .addr_i      (ic_tag_addr),
-          .wdata_i     (ic_tag_wdata),
-          .wmask_i     ({TagSizeECC{1'b1}}),
-          .intg_error_i(1'b0),
+          .gnt_o            (),
+          .write_i          (ic_tag_write),
+          .addr_i           (ic_tag_addr),
+          .wdata_i          (ic_tag_wdata),
+          .wmask_i          ({TagSizeECC{1'b1}}),
+          .intg_error_i     (1'b0),
 
-          .rdata_o     (ic_tag_rdata[way]),
-          .rvalid_o    (),
-          .raddr_o     (),
-          .rerror_o    (),
-          .cfg_i       (ram_cfg_i)
+          .rdata_o          (ic_tag_rdata[way]),
+          .rvalid_o         (),
+          .raddr_o          (),
+          .rerror_o         (),
+          .cfg_i            (ram_cfg_i),
+          .wr_collision_o   (),
+          .write_pending_o  (),
+
+          .alert_o          (icache_tag_alert[way])
         );
 
         // Data RAM instantiation
@@ -599,31 +617,34 @@ module ibex_top import ibex_pkg::*; #(
           .DataBitsPerMask    (LineSizeECC),
           .ReplicateKeyStream (1),
           .EnableParity       (0),
-          .DiffWidth          (LineSizeECC),
-          .NumAddrScrRounds   (NumAddrScrRounds),
-          .NumDiffRounds      (NumDiffRounds)
+          .NumPrinceRoundsHalf(ICacheScrNumPrinceRoundsHalf),
+          .NumAddrScrRounds   (NumAddrScrRounds)
         ) data_bank (
           .clk_i,
           .rst_ni,
 
-          .key_valid_i (scramble_key_valid_q),
-          .key_i       (scramble_key_q),
-          .nonce_i     (scramble_nonce_q),
+          .key_valid_i      (scramble_key_valid_q),
+          .key_i            (scramble_key_q),
+          .nonce_i          (scramble_nonce_q),
 
-          .req_i       (ic_data_req[way]),
+          .req_i            (ic_data_req[way]),
 
-          .gnt_o       (),
-          .write_i     (ic_data_write),
-          .addr_i      (ic_data_addr),
-          .wdata_i     (ic_data_wdata),
-          .wmask_i     ({LineSizeECC{1'b1}}),
-          .intg_error_i(1'b0),
+          .gnt_o            (),
+          .write_i          (ic_data_write),
+          .addr_i           (ic_data_addr),
+          .wdata_i          (ic_data_wdata),
+          .wmask_i          ({LineSizeECC{1'b1}}),
+          .intg_error_i     (1'b0),
 
-          .rdata_o     (ic_data_rdata[way]),
-          .rvalid_o    (),
-          .raddr_o     (),
-          .rerror_o    (),
-          .cfg_i       (ram_cfg_i)
+          .rdata_o          (ic_data_rdata[way]),
+          .rvalid_o         (),
+          .raddr_o          (),
+          .rerror_o         (),
+          .cfg_i            (ram_cfg_i),
+          .wr_collision_o   (),
+          .write_pending_o  (),
+
+          .alert_o          (icache_data_alert[way])
         );
 
         `ifdef INC_ASSERT
@@ -696,6 +717,8 @@ module ibex_top import ibex_pkg::*; #(
           .cfg_i       (ram_cfg_i)
         );
 
+        assign icache_tag_alert  = '{default:'b0};
+        assign icache_data_alert = '{default:'b0};
       end
     end
 
@@ -714,6 +737,8 @@ module ibex_top import ibex_pkg::*; #(
     assign ic_tag_rdata      = '{default:'b0};
     assign ic_data_rdata     = '{default:'b0};
 
+    assign icache_tag_alert  = '{default:'b0};
+    assign icache_data_alert = '{default:'b0};
   end
 
   assign data_wdata_o = data_wdata_core[31:0];
@@ -969,6 +994,9 @@ module ibex_top import ibex_pkg::*; #(
       .PMPEnable        (PMPEnable),
       .PMPGranularity   (PMPGranularity),
       .PMPNumRegions    (PMPNumRegions),
+      .PMPRstCfg        (PMPRstCfg),
+      .PMPRstAddr       (PMPRstAddr),
+      .PMPRstMsecCfg    (PMPRstMsecCfg),
       .MHPMCounterNum   (MHPMCounterNum),
       .MHPMCounterWidth (MHPMCounterWidth),
       .RV32E            (RV32E),
@@ -992,6 +1020,8 @@ module ibex_top import ibex_pkg::*; #(
       .RegFileECC       (RegFileECC),
       .RegFileDataWidth (RegFileDataWidth),
       .MemECC           (MemECC),
+      .DmBaseAddr       (DmBaseAddr),
+      .DmAddrMask       (DmAddrMask),
       .DmHaltAddr       (DmHaltAddr),
       .DmExceptionAddr  (DmExceptionAddr)
     ) u_ibex_lockstep (
@@ -1084,12 +1114,22 @@ module ibex_top import ibex_pkg::*; #(
     assign unused_scan = scan_rst_ni;
   end
 
+  // Enable or disable iCache multi bit encoding checking error generation.
+  // If enabled and a MuBi encoding error is detected, raise a major alert.
+  logic icache_alert_major_internal;
+  assign icache_alert_major_internal = (|icache_tag_alert) | (|icache_data_alert);
+
   assign alert_major_internal_o = core_alert_major_internal |
                                   lockstep_alert_major_internal |
-                                  rf_alert_major_internal;
+                                  rf_alert_major_internal |
+                                  icache_alert_major_internal;
   assign alert_major_bus_o      = core_alert_major_bus | lockstep_alert_major_bus;
   assign alert_minor_o          = core_alert_minor | lockstep_alert_minor;
 
+  // Parameter assertions
+  `ASSERT_INIT(DmHaltAddrInRange_A, (DmHaltAddr & ~DmAddrMask) == DmBaseAddr)
+  `ASSERT_INIT(DmExceptionAddrInRange_A, (DmExceptionAddr & ~DmAddrMask) == DmBaseAddr)
+
   // X checks for top-level outputs
   `ASSERT_KNOWN(IbexInstrReqX, instr_req_o)
   `ASSERT_KNOWN_IF(IbexInstrReqPayloadX, instr_addr_o, instr_req_o)
diff --git a/vendor/lowrisc_ibex/rtl/ibex_top_tracing.sv b/vendor/lowrisc_ibex/rtl/ibex_top_tracing.sv
index 7e480de5..b9f8045c 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_top_tracing.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_top_tracing.sv
@@ -27,6 +27,8 @@ module ibex_top_tracing import ibex_pkg::*; #(
   parameter bit          ICacheScramble   = 1'b0,
   parameter lfsr_seed_t  RndCnstLfsrSeed  = RndCnstLfsrSeedDefault,
   parameter lfsr_perm_t  RndCnstLfsrPerm  = RndCnstLfsrPermDefault,
+  parameter int unsigned DmBaseAddr       = 32'h1A110000,
+  parameter int unsigned DmAddrMask       = 32'h00000FFF,
   parameter int unsigned DmHaltAddr       = 32'h1A110800,
   parameter int unsigned DmExceptionAddr  = 32'h1A110808
 ) (
@@ -119,7 +121,8 @@ module ibex_top_tracing import ibex_pkg::*; #(
   logic [ 3:0] rvfi_mem_wmask;
   logic [31:0] rvfi_mem_rdata;
   logic [31:0] rvfi_mem_wdata;
-  logic [31:0] rvfi_ext_mip;
+  logic [31:0] rvfi_ext_pre_mip;
+  logic [31:0] rvfi_ext_post_mip;
   logic        rvfi_ext_nmi;
   logic        rvfi_ext_nmi_int;
   logic        rvfi_ext_debug_req;
@@ -136,7 +139,8 @@ module ibex_top_tracing import ibex_pkg::*; #(
   logic [31:0] unused_perf_regsh [10];
 
 
-  logic [31:0] unused_rvfi_ext_mip;
+  logic [31:0] unused_rvfi_ext_pre_mip;
+  logic [31:0] unused_rvfi_ext_post_mip;
   logic        unused_rvfi_ext_nmi;
   logic        unused_rvfi_ext_nmi_int;
   logic        unused_rvfi_ext_debug_req;
@@ -148,7 +152,8 @@ module ibex_top_tracing import ibex_pkg::*; #(
 
   // Tracer doesn't use these signals, though other modules may probe down into tracer to observe
   // them.
-  assign unused_rvfi_ext_mip = rvfi_ext_mip;
+  assign unused_rvfi_ext_pre_mip = rvfi_ext_pre_mip;
+  assign unused_rvfi_ext_post_mip = rvfi_ext_post_mip;
   assign unused_rvfi_ext_nmi = rvfi_ext_nmi;
   assign unused_rvfi_ext_nmi_int = rvfi_ext_nmi_int;
   assign unused_rvfi_ext_debug_req = rvfi_ext_debug_req;
@@ -181,6 +186,8 @@ module ibex_top_tracing import ibex_pkg::*; #(
     .ICacheScramble   ( ICacheScramble   ),
     .RndCnstLfsrSeed  ( RndCnstLfsrSeed  ),
     .RndCnstLfsrPerm  ( RndCnstLfsrPerm  ),
+    .DmBaseAddr       ( DmBaseAddr       ),
+    .DmAddrMask       ( DmAddrMask       ),
     .DmHaltAddr       ( DmHaltAddr       ),
     .DmExceptionAddr  ( DmExceptionAddr  )
   ) u_ibex_top (
@@ -252,7 +259,8 @@ module ibex_top_tracing import ibex_pkg::*; #(
     .rvfi_mem_wmask,
     .rvfi_mem_rdata,
     .rvfi_mem_wdata,
-    .rvfi_ext_mip,
+    .rvfi_ext_pre_mip,
+    .rvfi_ext_post_mip,
     .rvfi_ext_nmi,
     .rvfi_ext_nmi_int,
     .rvfi_ext_debug_req,
diff --git a/vendor/lowrisc_ibex/rtl/ibex_tracer.sv b/vendor/lowrisc_ibex/rtl/ibex_tracer.sv
index f361ddb3..c086f52b 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_tracer.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_tracer.sv
@@ -136,10 +136,10 @@ module ibex_tracer (
     if ((data_accessed & MEM) != 0) begin
       $fwrite(fh, " PA:0x%08x", rvfi_mem_addr);
 
-      if (rvfi_mem_rmask != 4'b0000) begin
+      if (rvfi_mem_wmask != 4'b0000) begin
         $fwrite(fh, " store:0x%08x", rvfi_mem_wdata);
       end
-      if (rvfi_mem_wmask != 4'b0000) begin
+      if (rvfi_mem_rmask != 4'b0000) begin
         $fwrite(fh, " load:0x%08x", rvfi_mem_rdata);
       end
     end
@@ -740,7 +740,7 @@ module ibex_tracer (
       // as a blocking assignment to xx. They then complain about the mixture with that an the
       // non-blocking assignment we use when opening the file. The bug is fixed with recent versions
       // of Verilator, but this hack is probably worth it for now.
-      int fh = file_handle;
+      static int fh = file_handle;
       $fclose(fh);
     end
   end
@@ -748,11 +748,10 @@ module ibex_tracer (
   // log execution
   always @(posedge clk_i) begin
     if (rvfi_valid && trace_log_enable) begin
-
-      int fh = file_handle;
+      static int fh = file_handle;
 
       if (fh == 32'h0) begin
-        string file_name_base = "trace_core";
+        static string file_name_base = "trace_core";
         void'($value$plusargs("ibex_tracer_file_base=%s", file_name_base));
         $sformat(file_name, "%s_%h.log", file_name_base, hart_id_i);
 
diff --git a/vendor/lowrisc_ibex/rtl/ibex_wb_stage.sv b/vendor/lowrisc_ibex/rtl/ibex_wb_stage.sv
index 53528489..38ce421c 100644
--- a/vendor/lowrisc_ibex/rtl/ibex_wb_stage.sv
+++ b/vendor/lowrisc_ibex/rtl/ibex_wb_stage.sv
@@ -166,8 +166,7 @@ module ibex_wb_stage #(
     // that returns too late to be used on the forwarding path.
     assign rf_wdata_fwd_wb_o = rf_wdata_wb_q;
 
-    // For FI hardening, only forward LSU write enable if we're actually waiting for it.
-    assign rf_wdata_wb_mux_we[1] = outstanding_load_wb_o & rf_we_lsu_i;
+    assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i;
 
     if (DummyInstructions) begin : g_dummy_instr_wb
       logic dummy_instr_wb_q;
diff --git a/vendor/lowrisc_ibex/shared/rtl/bus.sv b/vendor/lowrisc_ibex/shared/rtl/bus.sv
index 2fcf09c2..072a9599 100644
--- a/vendor/lowrisc_ibex/shared/rtl/bus.sv
+++ b/vendor/lowrisc_ibex/shared/rtl/bus.sv
@@ -54,14 +54,20 @@ module bus #(
   localparam int unsigned NumBitsHostSel = NrHosts > 1 ? $clog2(NrHosts) : 1;
   localparam int unsigned NumBitsDeviceSel = NrDevices > 1 ? $clog2(NrDevices) : 1;
 
+  logic host_sel_valid;
+  logic device_sel_valid;
+  logic decode_err_resp;
+
   logic [NumBitsHostSel-1:0] host_sel_req, host_sel_resp;
   logic [NumBitsDeviceSel-1:0] device_sel_req, device_sel_resp;
 
   // Master select prio arbiter
   always_comb begin
+    host_sel_valid = 1'b0;
     host_sel_req = '0;
     for (integer host = NrHosts - 1; host >= 0; host = host - 1) begin
       if (host_req_i[host]) begin
+        host_sel_valid = 1'b1;
         host_sel_req = NumBitsHostSel'(host);
       end
     end
@@ -69,10 +75,12 @@ module bus #(
 
   // Device select
   always_comb begin
+    device_sel_valid = 1'b0;
     device_sel_req = '0;
     for (integer device = 0; device < NrDevices; device = device + 1) begin
       if ((host_addr_i[host_sel_req] & cfg_device_addr_mask[device])
           == cfg_device_addr_base[device]) begin
+        device_sel_valid = 1'b1;
         device_sel_req = NumBitsDeviceSel'(device);
       end
     end
@@ -82,16 +90,19 @@ module bus #(
      if (!rst_ni) begin
         host_sel_resp <= '0;
         device_sel_resp <= '0;
+        decode_err_resp <= 1'b0;
      end else begin
         // Responses are always expected 1 cycle after the request
         device_sel_resp <= device_sel_req;
         host_sel_resp <= host_sel_req;
+        // Decode failed; no device matched?
+        decode_err_resp <= host_sel_valid & !device_sel_valid;
      end
   end
 
   always_comb begin
     for (integer device = 0; device < NrDevices; device = device + 1) begin
-      if (NumBitsDeviceSel'(device) == device_sel_req) begin
+      if (device_sel_valid && NumBitsDeviceSel'(device) == device_sel_req) begin
         device_req_o[device]   = host_req_i[host_sel_req];
         device_we_o[device]    = host_we_i[host_sel_req];
         device_addr_o[device]  = host_addr_i[host_sel_req];
@@ -111,8 +122,8 @@ module bus #(
     for (integer host = 0; host < NrHosts; host = host + 1) begin
       host_gnt_o[host] = 1'b0;
       if (NumBitsHostSel'(host) == host_sel_resp) begin
-        host_rvalid_o[host] = device_rvalid_i[device_sel_resp];
-        host_err_o[host]    = device_err_i[device_sel_resp];
+        host_rvalid_o[host] = device_rvalid_i[device_sel_resp] | decode_err_resp;
+        host_err_o[host]    = device_err_i[device_sel_resp]    | decode_err_resp;
         host_rdata_o[host]  = device_rdata_i[device_sel_resp];
       end else begin
         host_rvalid_o[host] = 1'b0;
diff --git a/vendor/lowrisc_ibex/tool_requirements.py b/vendor/lowrisc_ibex/tool_requirements.py
index 876206d2..6f7eb94f 100644
--- a/vendor/lowrisc_ibex/tool_requirements.py
+++ b/vendor/lowrisc_ibex/tool_requirements.py
@@ -5,7 +5,7 @@
 # Version requirements for various tools. Checked by tooling (e.g. fusesoc),
 # and inserted into the Sphinx-generated documentation.
 __TOOL_REQUIREMENTS__ = {
-    'verilator': '4.104',
+    'verilator': '4.210',
     'edalize':   '0.2.0',
     'vcs': {
         'min_version': '2020.03-SP2',
diff --git a/vendor/lowrisc_ibex/util/Makefile b/vendor/lowrisc_ibex/util/Makefile
index 14e8b11b..2a279310 100644
--- a/vendor/lowrisc_ibex/util/Makefile
+++ b/vendor/lowrisc_ibex/util/Makefile
@@ -1,3 +1,7 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
 .PHONY: lint
 lint:
 	mypy --strict sv2v_in_place.py
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip.lock.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip.lock.hjson
index 33a53061..9c3698bb 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip.lock.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip.lock.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/lowRISC/opentitan
-    rev: e6a0e9a1363d33789283ea6ba3c4d94d41f2dee5
+    rev: d268f271f4f75aeb8f3bf9624a497ae5bfb9c47e
   }
 }
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/clk_if.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/clk_if.sv
index 49030ec4..1ec154bb 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/clk_if.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/clk_if.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/clk_rst_if.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/clk_rst_if.sv
index de3f3848..2f5c3b40 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/clk_rst_if.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/clk_rst_if.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -136,6 +136,7 @@ interface clk_rst_if #(
 
   // set the clk frequency in khz
   function automatic void set_freq_khz(int freq_khz);
+    `DV_CHECK_FATAL(freq_khz > 0, , msg_id)
     clk_freq_mhz = $itor(freq_khz) / 1000;
     clk_period_ps = 1000_000 / clk_freq_mhz;
     recompute = 1'b1;
@@ -143,6 +144,7 @@ interface clk_rst_if #(
 
   // set the clk frequency in mhz
   function automatic void set_freq_mhz(int freq_mhz);
+    `DV_CHECK_FATAL(freq_mhz > 0, , msg_id)
     set_freq_khz(freq_mhz * 1000);
   endfunction
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/common_ifs.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/common_ifs.core
index efa3872f..e6467984 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/common_ifs.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/common_ifs.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:common_ifs"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/common_ifs_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/common_ifs_pkg.sv
index 4a1fd9a0..d2409665 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/common_ifs_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/common_ifs_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_if.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_if.core
index 3e2b9c5c..981934f8 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_if.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_if.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:entropy_subsys_fifo_exception_if"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_if.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_if.sv
index ab3636a0..41cdd15b 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_if.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_if.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_pkg.sv
index 9ca3e6d0..700e4297 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/pins_if.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/pins_if.sv
index 23168809..bf90c272 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/pins_if.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/pins_if.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/pins_ifs.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/pins_ifs.core
index f528e12d..46633658 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/pins_ifs.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/pins_ifs.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:pins_if"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/rst_shadowed_if.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/rst_shadowed_if.core
index 082921dd..8cbbcaf1 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/rst_shadowed_if.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/rst_shadowed_if.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:rst_shadowed_if"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/rst_shadowed_if.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/rst_shadowed_if.sv
index 233f3686..3a7e02ef 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/rst_shadowed_if.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/common_ifs/rst_shadowed_if.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/csr_utils/csr_seq_lib.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/csr_utils/csr_seq_lib.sv
index 34cbd947..1ef67731 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/csr_utils/csr_seq_lib.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/csr_utils/csr_seq_lib.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -88,12 +88,13 @@ class csr_base_seq extends uvm_reg_sequence #(uvm_sequence #(uvm_reg_item));
     end_idx = test_csr_chunk * chunk_size;
     if (end_idx >= all_csrs.size()) end_idx = all_csrs.size() - 1;
 
-    test_csrs = all_csrs[start_idx:end_idx];
     `uvm_info(`gtn, $sformatf("Testing %0d csrs [%0d - %0d] in all supplied models.",
                               test_csrs.size(), start_idx, end_idx), UVM_MEDIUM)
-    foreach (test_csrs[i]) begin
-      `uvm_info(`gtn, $sformatf("Testing CSR %0s, reset: 0x%0x.", test_csrs[i].get_full_name(),
-                                test_csrs[i].get_mirrored_value()), UVM_HIGH)
+    test_csrs.delete();
+    for (int i = start_idx; i <= end_idx; i++) begin
+      test_csrs.push_back(all_csrs[i]);
+      `uvm_info(`gtn, $sformatf("Testing CSR %0s, reset: 0x%0x.", all_csrs[i].get_full_name(),
+                                all_csrs[i].get_mirrored_value()), UVM_HIGH)
     end
     test_csrs.shuffle();
   endfunction
@@ -328,7 +329,19 @@ class csr_bit_bash_seq extends csr_base_seq;
   `uvm_object_new
 
   virtual task body();
+    int unsigned total_count = test_csrs.size();
+    int unsigned done_count = 0;
+
+    `uvm_info(`gtn,
+              $sformatf("Running bit bash sequence for %0d registers", total_count),
+              UVM_MEDIUM)
     foreach (test_csrs[i]) begin
+      done_count++;
+      `uvm_info(`gtn,
+                $sformatf("Verifying register bit bash for %0s (register %0d/%0d)",
+                          test_csrs[i].get_full_name(), done_count, total_count),
+                UVM_MEDIUM)
+
       // check if parent block or register is excluded from write
       if (is_excl(test_csrs[i], CsrExclWrite, CsrBitBashTest) ||
           is_excl(test_csrs[i], CsrExclWriteCheck, CsrBitBashTest)) begin
@@ -337,9 +350,6 @@ class csr_bit_bash_seq extends csr_base_seq;
         continue;
       end
 
-      `uvm_info(`gtn, $sformatf("Verifying register bit bash for %0s",
-                test_csrs[i].get_full_name()), UVM_MEDIUM)
-
       begin
         uvm_reg_field   fields[$];
         string          mode[`UVM_REG_DATA_WIDTH];
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/csr_utils/csr_utils.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/csr_utils/csr_utils.core
index 0b2cbf41..256e57a3 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/csr_utils/csr_utils.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/csr_utils/csr_utils.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:csr_utils"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/csr_utils/csr_utils_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/csr_utils/csr_utils_pkg.sv
index 907ec802..94ce5d15 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/csr_utils/csr_utils_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/csr_utils/csr_utils_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -26,10 +26,14 @@ package csr_utils_pkg;
 
   function automatic void increment_outstanding_access();
     outstanding_accesses++;
+    `uvm_info("csr_utils_pkg", $sformatf("increment_outstanding_access %0d", outstanding_accesses),
+              UVM_HIGH)
   endfunction
 
   function automatic void decrement_outstanding_access();
     outstanding_accesses--;
+    `uvm_info("csr_utils_pkg", $sformatf("decrement_outstanding_access %0d", outstanding_accesses),
+              UVM_HIGH)
   endfunction
 
   task automatic wait_no_outstanding_access();
@@ -340,7 +344,7 @@ package csr_utils_pkg;
                             input  uvm_reg_map        map = null,
                             input  uvm_reg_frontdoor  user_ftdr = default_user_frontdoor);
     if (backdoor) begin
-      csr_peek(ptr, value, check);
+      value = csr_peek(ptr, check);
       status = UVM_IS_OK;
       return;
     end
@@ -383,35 +387,40 @@ package csr_utils_pkg;
 
   // backdoor read csr
   // uvm_reg::peek() returns a 2-state value, directly get data from hdl path
-  task automatic csr_peek(input uvm_object      ptr,
-                          output uvm_reg_data_t value,
-                          input uvm_check_e     check = default_csr_check,
-                          input bkdr_reg_path_e kind = BkdrRegPathRtl);
-    string      msg_id = {csr_utils_pkg::msg_id, "::csr_peek"};
-    csr_field_t csr_or_fld = decode_csr_or_field(ptr);
-    uvm_reg     csr = csr_or_fld.csr;
-
-    if (csr.has_hdl_path(kind.name)) begin
-      uvm_hdl_path_concat paths[$];
-
-      csr.get_full_hdl_path(paths, kind.name);
-      foreach (paths[0].slices[i]) begin
-        uvm_reg_data_t field_val;
-        if (uvm_hdl_read(paths[0].slices[i].path, field_val)) begin
-          if (check == UVM_CHECK) `DV_CHECK_EQ($isunknown(value), 0, "", error, msg_id)
-          value |= field_val << paths[0].slices[i].offset;
-        end else begin
-          `uvm_fatal(msg_id, $sformatf("uvm_hdl_read failed for %0s", csr.get_full_name()))
-        end
-      end
-    end else begin
-      `uvm_fatal(msg_id, $sformatf("No backdoor defined for %0s path's %0s",
-                                   csr.get_full_name(), kind.name))
+  function automatic uvm_reg_data_t csr_peek(uvm_object      ptr,
+                                             uvm_check_e     check = default_csr_check,
+                                             bkdr_reg_path_e kind = BkdrRegPathRtl);
+    string         msg_id = {csr_utils_pkg::msg_id, "::csr_peek"};
+    csr_field_t    csr_or_fld = decode_csr_or_field(ptr);
+    uvm_reg        csr = csr_or_fld.csr;
+    uvm_reg_data_t value = 0;
+
+    uvm_hdl_path_concat paths[$];
+    csr.get_full_hdl_path(paths, kind.name);
+
+    `DV_CHECK_FATAL(paths.size() > 0,
+                    $sformatf("No backdoor defined for %0s path's %0s",
+                              csr.get_full_name(), kind.name),
+                    msg_id)
+
+    foreach (paths[0].slices[i]) begin
+      uvm_reg_data_t field_val;
+      `DV_CHECK_FATAL(uvm_hdl_read(paths[0].slices[i].path, field_val),
+                      $sformatf("Failed to read %s, slice %d, at path %s",
+                                csr.get_full_name(), i, paths[0].slices[i].path),
+                      msg_id)
+      if (check == UVM_CHECK) `DV_CHECK_EQ($isunknown(field_val), 0, "", error, msg_id)
+
+      value |= field_val << paths[0].slices[i].offset;
     end
 
-    // if it's field, only return field value
+    // We now have the contents of the field or register in value. If ptr was a sub-field of some
+    // register, it will be laid out in the same way as the field is laid out in the register.
+    // That's no problem: we can just extract the relevant field from the laid-out value here.
     if (csr_or_fld.field != null) value = get_field_val(csr_or_fld.field, value);
-  endtask
+
+    return value;
+  endfunction
 
   task automatic csr_rd_check(input  uvm_object         ptr,
                               input  uvm_check_e        check = default_csr_check,
@@ -544,6 +553,7 @@ package csr_utils_pkg;
         fork
           while (!under_reset) begin
             if (spinwait_delay_ns) #(spinwait_delay_ns * 1ns);
+            `uvm_info("csr_utils_pkg", "In csr_spinwait", verbosity)
             csr_rd(.ptr(ptr), .value(read_data), .check(check), .path(path),
                    .blocking(1), .map(map), .user_ftdr(user_ftdr), .backdoor(backdoor));
             `uvm_info(msg_id, $sformatf("ptr %0s == 0x%0h",
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/csr_excl_item.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/csr_excl_item.sv
index b577d3bc..fa6f5777 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/csr_excl_item.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/csr_excl_item.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_lockable_field_cov.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_lockable_field_cov.sv
index 65f852e4..62e8c9d0 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_lockable_field_cov.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_lockable_field_cov.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_mem.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_mem.sv
index b8cd99bd..631c457b 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_mem.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_mem.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_mubi_cov.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_mubi_cov.sv
index f3af2b9e..2cbe9fe5 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_mubi_cov.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_mubi_cov.sv
@@ -1,12 +1,11 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
 // coverage object for a fixed width mubi
 class mubi_cov #(parameter int Width = 4,
-                parameter int ValueTrue = prim_mubi_pkg::MuBi4True,
-                parameter int ValueFalse = prim_mubi_pkg::MuBi4False
-                ) extends uvm_object;
+                 parameter int unsigned ValueTrue = prim_mubi_pkg::MuBi4True,
+                 parameter int unsigned ValueFalse = prim_mubi_pkg::MuBi4False) extends uvm_object;
   `uvm_object_param_utils(mubi_cov #(Width, ValueTrue, ValueFalse))
 
   // Collect true, false and at least N other values (N = Width)
@@ -43,6 +42,18 @@ typedef mubi_cov #(.Width(12),
 typedef mubi_cov #(.Width(16),
                    .ValueTrue(prim_mubi_pkg::MuBi16True),
                    .ValueFalse(prim_mubi_pkg::MuBi16False)) mubi16_cov;
+typedef mubi_cov #(.Width(20),
+                   .ValueTrue(prim_mubi_pkg::MuBi20True),
+                   .ValueFalse(prim_mubi_pkg::MuBi20False)) mubi20_cov;
+typedef mubi_cov #(.Width(24),
+                   .ValueTrue(prim_mubi_pkg::MuBi24True),
+                   .ValueFalse(prim_mubi_pkg::MuBi24False)) mubi24_cov;
+typedef mubi_cov #(.Width(28),
+                   .ValueTrue(prim_mubi_pkg::MuBi28True),
+                   .ValueFalse(prim_mubi_pkg::MuBi28False)) mubi28_cov;
+typedef mubi_cov #(.Width(32),
+                   .ValueTrue(prim_mubi_pkg::MuBi32True),
+                   .ValueFalse(prim_mubi_pkg::MuBi32False)) mubi32_cov;
 
 // a mubi coverage object, which allows to dynamically select the width of mubi
 class dv_base_mubi_cov extends uvm_object;
@@ -53,6 +64,10 @@ class dv_base_mubi_cov extends uvm_object;
   mubi8_cov m_mubi8_cov;
   mubi12_cov m_mubi12_cov;
   mubi16_cov m_mubi16_cov;
+  mubi20_cov m_mubi20_cov;
+  mubi24_cov m_mubi24_cov;
+  mubi28_cov m_mubi28_cov;
+  mubi32_cov m_mubi32_cov;
 
   `uvm_object_utils(dv_base_mubi_cov)
   `uvm_object_new
@@ -70,6 +85,10 @@ class dv_base_mubi_cov extends uvm_object;
       8:  m_mubi8_cov  = mubi8_cov::type_id::create(cov_name);
       12: m_mubi12_cov = mubi12_cov::type_id::create(cov_name);
       16: m_mubi16_cov = mubi16_cov::type_id::create(cov_name);
+      20: m_mubi20_cov = mubi20_cov::type_id::create(cov_name);
+      24: m_mubi24_cov = mubi24_cov::type_id::create(cov_name);
+      28: m_mubi28_cov = mubi28_cov::type_id::create(cov_name);
+      32: m_mubi32_cov = mubi32_cov::type_id::create(cov_name);
       default: `uvm_fatal(`gfn, $sformatf("Unsupported mubi width (%0d) is used", mubi_width))
     endcase
   endfunction : create_cov
@@ -80,9 +99,11 @@ class dv_base_mubi_cov extends uvm_object;
       8:  m_mubi8_cov.sample(value);
       12: m_mubi12_cov.sample(value);
       16: m_mubi16_cov.sample(value);
+      20: m_mubi20_cov.sample(value);
+      24: m_mubi24_cov.sample(value);
+      28: m_mubi28_cov.sample(value);
+      32: m_mubi32_cov.sample(value);
       default: `uvm_fatal(`gfn, $sformatf("Unsupported mubi width (%0d) is used", mubi_width))
     endcase
   endfunction : sample
 endclass : dv_base_mubi_cov
-
-
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg.core
index d961118c..cbae5d75 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:dv_base_reg"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg.sv
index 5daf3f34..f25f6abd 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -102,6 +102,15 @@ class dv_base_reg extends uvm_reg;
     end
   endfunction
 
+  // Return a mask of read-only bits in the register.
+  virtual function uvm_reg_data_t get_ro_mask();
+    dv_base_reg_field flds[$];
+    this.get_dv_base_reg_fields(flds);
+    foreach (flds[i]) begin
+      get_ro_mask |= flds[i].get_ro_mask();
+    end
+  endfunction
+
   // this function can only be called when this reg is intr_state reg
   // Example: ral.intr_state.get_intr_pins_exp_value(). And it returns value of
   // intr_state & intr_enable, which represents value of interrupt pins
@@ -305,14 +314,15 @@ class dv_base_reg extends uvm_reg;
       end
       do_update_shadow_vals = 0;
     end
-    lock_lockable_flds(rw.value[0]);
+    lock_lockable_flds(rw.value[0], kind);
   endfunction
 
   // This function is used for wen_reg to lock its lockable flds by changing the lockable flds'
   // access policy. For register write via csr_wr(), this function is included in post_write().
   // For register write via tl_access(), user will need to call this function manually.
-  virtual function void lock_lockable_flds(uvm_reg_data_t val);
+  virtual function void lock_lockable_flds(uvm_reg_data_t val, uvm_predict_e kind);
     if (is_wen_reg()) begin
+      `uvm_info(`gfn, $sformatf("lock_lockable_flds %d val", val), UVM_LOW);
       foreach (m_fields[i]) begin
         dv_base_reg_field fld;
         `downcast(fld, m_fields[i])
@@ -322,7 +332,17 @@ class dv_base_reg extends uvm_reg;
           case (field_access)
             // discussed in issue #1922: enable register is standarized to W0C or RO (if HW has
             // write access).
-            "W0C": if (field_val == 1'b0) fld.set_lockable_flds_access(1);
+            "W0C": begin
+              // This is the regular behavior with W0C access policy enabled (i.e., only
+              // clearing is possible).
+              if (kind == UVM_PREDICT_WRITE && field_val == 1'b0) begin
+                fld.set_lockable_flds_access(1);
+              // In this case we are using direct prediction where the access policy is not
+              // applied. I.e., a regwen bit that has been set to 0 can be set to 1 again.
+              end else if (kind == UVM_PREDICT_DIRECT) begin
+                fld.set_lockable_flds_access((~field_val) & fld.get_field_mask());
+              end
+            end
             "RO": ; // if RO, it's updated by design, need to predict in scb
             default:`uvm_fatal(`gfn, $sformatf("lock register invalid access %s", field_access))
           endcase
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_block.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_block.sv
index 84d7dc13..74c3f733 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_block.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_block.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_field.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_field.sv
index 3909fb46..f20f832e 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_field.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_field.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -17,6 +17,11 @@ class dv_base_reg_field extends uvm_reg_field;
   // This is used for get_field_by_name
   string alias_name = "";
 
+  // If this field encodes a mubi, this field encodes special access modes such as W1C that cannot
+  // be captured with the regular access configuration, since UVM does not model such access modes
+  // correctly for mubis.
+  string mubi_access = "";
+
   // Default mubi_width = 0 indicates this register field is not a mubi type.
   protected int mubi_width;
 
@@ -58,6 +63,7 @@ class dv_base_reg_field extends uvm_reg_field;
                                   int unsigned   size,
                                   int unsigned   lsb_pos,
                                   string         access,
+                                  string         mubi_access,
                                   bit            volatile,
                                   uvm_reg_data_t reset,
                                   bit            has_reset,
@@ -73,7 +79,7 @@ class dv_base_reg_field extends uvm_reg_field;
                       .is_rand  (is_rand),
                       .individually_accessible(individually_accessible));
       value.rand_mode(is_rand);
-
+      this.mubi_access = mubi_access;
       is_intr_test_fld = !(uvm_re_match("intr_test*", get_parent().get_name()));
       shadowed_val = ~committed_val;
     endfunction
@@ -83,10 +89,53 @@ class dv_base_reg_field extends uvm_reg_field;
     `downcast(get_dv_base_reg_parent, csr)
   endfunction
 
+  // Local helper function to reduce code in do_predict further below.
+  function uvm_reg_data_t mubi_or_hi (uvm_reg_data_t a, uvm_reg_data_t b);
+    import prim_mubi_pkg::*;
+    uvm_reg_data_t out;
+    case (mubi_width)
+      4:  out = uvm_reg_data_t'(mubi4_or_hi(mubi4_t'(a), mubi4_t'(b)));
+      8:  out = uvm_reg_data_t'(mubi8_or_hi(mubi8_t'(a), mubi8_t'(b)));
+      12: out = uvm_reg_data_t'(mubi12_or_hi(mubi12_t'(a), mubi12_t'(b)));
+      16: out = uvm_reg_data_t'(mubi16_or_hi(mubi16_t'(a), mubi16_t'(b)));
+      default: $error("Unsupported mubi width %d.", mubi_width);
+    endcase
+    return out;
+  endfunction: mubi_or_hi
+
+  // Local helper function to reduce code in do_predict further below.
+  function uvm_reg_data_t mubi_and_hi (uvm_reg_data_t a, uvm_reg_data_t b);
+    import prim_mubi_pkg::*;
+    uvm_reg_data_t out;
+    case (mubi_width)
+      4:  out = uvm_reg_data_t'(mubi4_and_hi(mubi4_t'(a), mubi4_t'(b)));
+      8:  out = uvm_reg_data_t'(mubi8_and_hi(mubi8_t'(a), mubi8_t'(b)));
+      12: out = uvm_reg_data_t'(mubi12_and_hi(mubi12_t'(a), mubi12_t'(b)));
+      16: out = uvm_reg_data_t'(mubi16_and_hi(mubi16_t'(a), mubi16_t'(b)));
+      default: $error("Unsupported mubi width: %d.", mubi_width);
+    endcase
+    return out;
+  endfunction: mubi_and_hi
+
+  // Local helper function to reduce code in do_predict further below.
+  function uvm_reg_data_t mubi_false ();
+    import prim_mubi_pkg::*;
+    uvm_reg_data_t out;
+    case (mubi_width)
+      4:  out = uvm_reg_data_t'(MuBi4False);
+      8:  out = uvm_reg_data_t'(MuBi8False);
+      12: out = uvm_reg_data_t'(MuBi12False);
+      16: out = uvm_reg_data_t'(MuBi16False);
+      default: $error("Unsupported mubi width: %d.", mubi_width);
+    endcase
+    return out;
+  endfunction: mubi_false
+
   virtual function void do_predict (uvm_reg_item      rw,
                                     uvm_predict_e     kind = UVM_PREDICT_DIRECT,
                                     uvm_reg_byte_en_t be = -1);
     uvm_reg_data_t field_val = rw.value[0] & ((1 << get_n_bits())-1);
+    string access = get_access();
 
     // update intr_state mirrored value if this is an intr_test reg
     // if kind is UVM_PREDICT_DIRECT or UVM_PREDICT_READ, super.do_predict can handle
@@ -94,15 +143,34 @@ class dv_base_reg_field extends uvm_reg_field;
       uvm_reg_field intr_state_fld = get_intr_state_field();
       uvm_reg_data_t predict_val;
       if (intr_state_fld.get_access == "RO") begin // status interrupt
-        predict_val = field_val;
+        predict_val = field_val | intr_state_fld.get_reset();
       end else begin // regular W1C interrupt
         `DV_CHECK_STREQ(intr_state_fld.get_access, "W1C")
         predict_val = field_val | `gmv(intr_state_fld);
       end
       // use UVM_PREDICT_READ to avoid uvm_warning due to UVM_PREDICT_DIRECT
       void'(intr_state_fld.predict(predict_val, .kind(UVM_PREDICT_READ)));
-    end
 
+    end else if (kind == UVM_PREDICT_WRITE && mubi_access inside {"W1S", "W1C", "W0C"})
+    begin
+      // Some smoke checking of the byte enables. RTL does not latch anything if not all affected
+      // bytes of the field are enabled. Note that we still use UVM_PREDICT_WRITE further below
+      // since the underlying access is set to RW in the RAL model.
+      if (mubi_width <= 8 && be[0] || mubi_width > 8 && mubi_width <= 16 && &be[1:0]) begin
+        // In case this is a clearable MUBI field, we have to interpret the write value correctly.
+        // ICEBOX(#9273): Note that this just uses bitwise functions to update the value and does
+        // not rectify incorrect mubi values. At a later point, we should discuss if and how to
+        // tighten this up, as discussed on the linked issue.
+        case (mubi_access)
+          "W1S": rw.value[0] = this.mubi_or_hi(rw.value[0], `gmv(this));
+          "W1C": rw.value[0] = this.mubi_and_hi(~rw.value[0], `gmv(this));
+          "W0C": rw.value[0] = this.mubi_and_hi(rw.value[0], `gmv(this));
+          default: ; // unreachable
+        endcase
+      end
+    end else if (kind == UVM_PREDICT_READ && mubi_access == "RC") begin
+      rw.value[0] = this.mubi_false();
+    end
     super.do_predict(rw, kind, be);
   endfunction
 
@@ -120,11 +188,19 @@ class dv_base_reg_field extends uvm_reg_field;
     return m_original_access;
   endfunction
 
+  // Return a mask of valid bits in the field.
   virtual function uvm_reg_data_t get_field_mask();
     get_field_mask = (1'b1 << this.get_n_bits()) - 1;
     get_field_mask = get_field_mask << this.get_lsb_pos();
   endfunction
 
+  // Return a mask of read-only bits in the field.
+  virtual function uvm_reg_data_t get_ro_mask();
+    bit is_ro = (this.get_access() == "RO");
+    get_ro_mask = (is_ro << this.get_n_bits()) - is_ro;
+    get_ro_mask = get_ro_mask << this.get_lsb_pos();
+  endfunction
+
   virtual function void set_original_access(string access);
     if (m_original_access == "") begin
       m_original_access = access;
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_map.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_map.sv
index cce6d6ec..ee748f51 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_map.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_map.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_pkg.sv
index 827d5ac4..95fe70dd 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_shadowed_field_cov.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_shadowed_field_cov.sv
index e1dc3c67..bae4a6a1 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_shadowed_field_cov.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_shadowed_field_cov.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_agent.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_agent.sv
index a909aa1f..0d561de5 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_agent.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_agent.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -65,4 +65,3 @@ class dv_base_agent #(type CFG_T            = dv_base_agent_cfg,
   endfunction
 
 endclass
-
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_agent_cfg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_agent_cfg.sv
index 338fadf7..0caf0f78 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_agent_cfg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_agent_cfg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_agent_cov.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_agent_cov.sv
index 545f6764..03b9e268 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_agent_cov.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_agent_cov.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_driver.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_driver.sv
index 43810076..264f5e93 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_driver.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_driver.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -34,4 +34,3 @@ class dv_base_driver #(type ITEM_T     = uvm_sequence_item,
   endtask
 
 endclass
-
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env.sv
index 2c5e865c..2ce662fa 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv
index 69ae9c0f..106d812f 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -12,6 +12,7 @@ class dv_base_env_cfg #(type RAL_T = dv_base_reg_block) extends uvm_object;
   bit en_cov            = 0; // Enable via plusarg, only if coverage collection is turned on.
   bit en_dv_cdc         = 0; // Enable via plusarg.
 
+  local bit will_reset  = 0;
   bit under_reset       = 0;
   bit is_initialized;        // Indicates that the initialize() method has been called.
 
@@ -107,8 +108,22 @@ class dv_base_env_cfg #(type RAL_T = dv_base_reg_block) extends uvm_object;
   protected virtual function void post_build_ral_settings(dv_base_reg_block ral);
   endfunction
 
+  // This can be used to stop transaction generators either upon reset or in preparation to
+  // issue a random reset.
+  virtual function bit stop_transaction_generators();
+    return this.will_reset || this.under_reset;
+  endfunction
+
+  // This can be used to announce the intention to generate a random reset soon, to allow
+  // transaction generators to stop, and fire a reset with no outstanding transactions.
+  virtual function void set_intention_to_reset();
+    `uvm_info(`gfn, "Setting intention to reset", UVM_MEDIUM)
+    this.will_reset = 1'b1;
+  endfunction
+
   virtual function void reset_asserted();
     this.under_reset = 1;
+    this.will_reset = 0;
     csr_utils_pkg::reset_asserted();
   endfunction
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cov.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cov.sv
index 48bf92ad..47064386 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cov.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cov.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_monitor.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_monitor.sv
index 47208142..b535934a 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_monitor.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_monitor.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -38,12 +38,12 @@ class dv_base_monitor #(type ITEM_T = uvm_sequence_item,
 
   virtual task run_phase(uvm_phase phase);
     fork
-      collect_trans(phase);
+      collect_trans();
     join
   endtask
 
   // collect transactions forever
-  virtual protected task collect_trans(uvm_phase phase);
+  virtual protected task collect_trans();
     `uvm_fatal(`gfn, "this method is not supposed to be called directly!")
   endtask
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_scoreboard.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_scoreboard.sv
index facd89db..c8b4acc6 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_scoreboard.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_scoreboard.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -78,4 +78,3 @@ class dv_base_scoreboard #(type RAL_T = dv_base_reg_block,
   endfunction : pre_abort
 
 endclass
-
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_seq.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_seq.sv
index 8c6aca97..616b47f3 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_seq.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_seq.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_sequencer.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_sequencer.sv
index 501929a2..33d43109 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_sequencer.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_sequencer.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_test.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_test.sv
index 8227de69..d4c564a2 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_test.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_test.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_virtual_sequencer.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_virtual_sequencer.sv
index 3fe74281..1b39b874 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_virtual_sequencer.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_virtual_sequencer.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_vseq.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_vseq.sv
index 081863ea..d196fe46 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_vseq.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_vseq.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_lib.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_lib.core
index 30615289..a7b72772 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_lib.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_lib.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:dv_lib"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_lib_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_lib_pkg.sv
index a53733eb..d7eafc0d 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_lib_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_lib/dv_lib_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.core
index 02c03356..45428865 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:dv_fcov_macros"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh
index 8ca12cdc..6b5111eb 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.core
index 5f2fb800..61a236b5 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:dv_macros"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh
index e33b1622..f922b1a9 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -360,14 +360,13 @@
   `define GET_PARITY(val, odd=0) (^val ^ odd)
 `endif
 
-// Wait a task or statement with exit condition
-// Kill the thread when either the wait statement is completed or exit condition occurs
-// input WAIT_ need to be a statement. Here are some examples
-// `DV_SPINWAIT(wait(...);, "Wait for ...")
-// `DV_SPINWAIT(
-//              while (1) begin
-//                ...
-//              end)
+// Wait for a statement but stop early if the EXIT statement completes.
+//
+// Example usage:
+//
+//    `DV_SPINWAIT_EXIT(do_something_time_consuming();,
+//                      wait(stop_now_flag);,
+//                      "The stop flag was set when we were working")
 `ifndef DV_SPINWAIT_EXIT
 `define DV_SPINWAIT_EXIT(WAIT_, EXIT_, MSG_ = "exit condition occurred!", ID_ =`gfn) \
   begin \
@@ -398,7 +397,7 @@
   end
 `endif
 
-// wait a task or statement with timer watchdog
+// Wait for a statement, but exit early after a timeout
 `ifndef DV_SPINWAIT
 `define DV_SPINWAIT(WAIT_, MSG_ = "timeout occurred!", TIMEOUT_NS_ = default_spinwait_timeout_ns, ID_ =`gfn) \
   `DV_SPINWAIT_EXIT(WAIT_, `DV_WAIT_TIMEOUT(TIMEOUT_NS_, ID_, MSG_);, "", ID_)
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_catcher.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_catcher.sv
index 91e3337e..7ab687a7 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_catcher.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_catcher.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 // Report catcher/demoter
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_server.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_server.sv
index a5d7440e..f48f62e1 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_server.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_server.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status.core
index e11cfd4b..fdeea3eb 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:dv_test_status"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status_pkg.sv
index 3933673e..d1516a2b 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils.core
index 95ffd58d..f8e0a4ef 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:dv_utils"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv
index fd2a48c2..00a6cd73 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -36,7 +36,6 @@ package dv_utils_pkg;
 
   // typedef parameterized pins_if for ease of implementation for interrupts and alerts
   typedef virtual pins_if #(NUM_MAX_INTERRUPTS) intr_vif;
-  typedef virtual pins_if #(1)                  devmode_vif;
 
   // interface direction / mode - Host or Device
   typedef enum bit {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_vif_wrap.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_vif_wrap.sv
index 61d99479..528eb978 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_vif_wrap.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/dv_utils/dv_vif_wrap.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util.core
index 0ab9509a..63e06e97 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:mem_bkdr_util"
@@ -15,7 +15,7 @@ filesets:
       - lowrisc:prim:cipher_pkg:0.1
       - lowrisc:prim:secded:0.1
       - lowrisc:ip:otp_ctrl_pkg:1.0
-      - lowrisc:ip:flash_ctrl_pkg
+      - lowrisc:ip_interfaces:flash_ctrl_pkg
       - lowrisc:dv:digestpp_dpi
       - lowrisc:ip:kmac_pkg
     files:
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util.sv
index 69b2d475..c3354bb7 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__flash.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__flash.sv
index 66bf585a..56a96148 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__flash.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__flash.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__otp.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__otp.sv
index aeb67ae4..3ce18e43 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__otp.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__otp.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -123,15 +123,11 @@ virtual function void otp_write_secret2_partition(bit [RmaTokenSize*8-1:0] rma_u
   write64(Secret2DigestOffset, digest);
 endfunction
 
-virtual function void otp_write_hw_cfg_partition(
-    bit [DeviceIdSize*8-1:0] device_id, bit [ManufStateSize*8-1:0] manuf_state,
-    bit [EnSramIfetchSize*8-1:0] en_sram_ifetch,
-    bit [EnCsrngSwAppReadSize*8-1:0] en_csrng_sw_app_read,
-    bit [EnEntropySrcFwReadSize*8-1:0] en_entropy_src_fw_read,
-    bit [EnEntropySrcFwOverSize*8-1:0] en_entropy_src_fw_over);
-  bit [HwCfgDigestSize*8-1:0] digest;
+virtual function void otp_write_hw_cfg0_partition(
+    bit [DeviceIdSize*8-1:0] device_id, bit [ManufStateSize*8-1:0] manuf_state);
+  bit [HwCfg0DigestSize*8-1:0] digest;
 
-  bit [bus_params_pkg::BUS_DW-1:0] hw_cfg_data[$];
+  bit [bus_params_pkg::BUS_DW-1:0] hw_cfg0_data[$];
 
   for (int i = 0; i < DeviceIdSize; i += 4) begin
     write32(i + DeviceIdOffset, device_id[i*8+:32]);
@@ -139,14 +135,27 @@ virtual function void otp_write_hw_cfg_partition(
   for (int i = 0; i < ManufStateSize; i += 4) begin
     write32(i + ManufStateOffset, manuf_state[i*8+:32]);
   end
-  write32(EnSramIfetchOffset,
-          {en_entropy_src_fw_over, en_entropy_src_fw_read, en_csrng_sw_app_read, en_sram_ifetch});
 
-  hw_cfg_data = {<<32 {32'h0, en_entropy_src_fw_over, en_entropy_src_fw_read,
-                       en_csrng_sw_app_read, en_sram_ifetch, manuf_state, device_id}};
-  digest = cal_digest(HwCfgIdx, hw_cfg_data);
+  hw_cfg0_data = {<<32 {manuf_state, device_id}};
+  digest = cal_digest(HwCfg0Idx, hw_cfg0_data);
+
+  write64(HwCfg0DigestOffset, digest);
+endfunction
+
+virtual function void otp_write_hw_cfg1_partition(
+    bit [EnCsrngSwAppReadSize*8-1:0] en_csrng_sw_app_read,
+    bit [EnSramIfetchSize*8-1:0] en_sram_ifetch,
+    bit [EnSramIfetchSize*8-1:0] dis_rv_dm_late_debug);
+  bit [HwCfg1DigestSize*8-1:0] digest;
+
+  bit [bus_params_pkg::BUS_DW-1:0] hw_cfg1_data[$];
+
+  write32(EnSramIfetchOffset, {dis_rv_dm_late_debug, en_csrng_sw_app_read, en_sram_ifetch});
+
+  hw_cfg1_data = {<<32 {32'h0, dis_rv_dm_late_debug, en_csrng_sw_app_read, en_sram_ifetch}};
+  digest = cal_digest(HwCfg1Idx, hw_cfg1_data);
 
-  write64(HwCfgDigestOffset, digest);
+  write64(HwCfg1DigestOffset, digest);
 endfunction
 
 // Functions that clear the provisioning state of the buffered partitions.
@@ -169,8 +178,8 @@ virtual function void otp_clear_secret2_partition();
   end
 endfunction
 
-virtual function void otp_clear_hw_cfg_partition();
-  for (int i = 0; i < HwCfgSize; i += 4) begin
-    write32(i + HwCfgOffset, 32'h0);
+virtual function void otp_clear_hw_cfg0_partition();
+  for (int i = 0; i < HwCfg0Size; i += 4) begin
+    write32(i + HwCfg0Offset, 32'h0);
   end
 endfunction
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__rom.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__rom.sv
index d021ca56..b2904435 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__rom.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__rom.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -59,7 +59,6 @@ virtual function bit [38:0] rom_encrypt_read32(bit [bus_params_pkg::BUS_AW-1:0]
     zero_key[i] = '0;
   end
 
-  data_arr = sram_scrambler_pkg::sp_decrypt(data_arr, 39, zero_key);
   for (int i = 0; i < 39; i++) begin
     data[i] = data_arr[i] ^ keystream[i];
   end
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__sram.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__sram.sv
index f5edc537..9fe8a69c 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__sram.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util__sram.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -9,7 +9,7 @@
 function logic [bus_params_pkg::BUS_AW-1:0] get_sram_encrypt_addr (
   logic [bus_params_pkg::BUS_AW-1:0] addr,
   logic [SRAM_BLOCK_WIDTH-1:0] nonce,
-  logic [31:0] extra_addr_bits = '0);
+  logic [31:0] extra_addr_bits);
 
   int full_addr_width = addr_width + extra_addr_bits;
 
@@ -43,8 +43,8 @@ function logic [38:0] get_sram_encrypt32_intg_data (
   logic [31:0]                       data,
   logic [SRAM_KEY_WIDTH-1:0]         key,
   logic [SRAM_BLOCK_WIDTH-1:0]       nonce,
-  bit   [38:0]                       flip_bits = '0,
-  int                                extra_addr_bits=0);
+  int                                extra_addr_bits,
+  bit   [38:0]                       flip_bits = '0);
 
   logic [38:0]                       integ_data;
   logic [38:0]                       scrambled_data;
@@ -77,9 +77,10 @@ endfunction : get_sram_encrypt32_intg_data
 // It simply ignores the integrity bits.
 virtual function logic [38:0] sram_encrypt_read32_integ(logic [bus_params_pkg::BUS_AW-1:0] addr,
                                                         logic [SRAM_KEY_WIDTH-1:0]         key,
-                                                        logic [SRAM_BLOCK_WIDTH-1:0]       nonce);
-  logic [bus_params_pkg::BUS_AW-1:0] scr_addr = get_sram_encrypt_addr(addr, nonce);
-  logic [38:0] rdata39 = _sram_decrypt_read39(addr, scr_addr, key, nonce);
+                                                        logic [SRAM_BLOCK_WIDTH-1:0]       nonce,
+                                                        int extra_addr_bits);
+  logic [bus_params_pkg::BUS_AW-1:0] scr_addr = get_sram_encrypt_addr(addr, nonce, extra_addr_bits);
+  logic [38:0] rdata39 = _sram_decrypt_read39(addr, scr_addr, key, nonce, extra_addr_bits);
   return rdata39[31:0];
 endfunction : sram_encrypt_read32_integ
 
@@ -89,17 +90,19 @@ local function logic [38:0] _sram_decrypt_read39(
     logic [bus_params_pkg::BUS_AW-1:0] addr,
     logic [bus_params_pkg::BUS_AW-1:0] scr_addr,
     logic [SRAM_KEY_WIDTH-1:0]   key,
-    logic [SRAM_BLOCK_WIDTH-1:0] nonce);
+    logic [SRAM_BLOCK_WIDTH-1:0] nonce,
+    int extra_addr_bits);
   logic [38:0]                       rdata39 = '0;
 
   logic rdata_arr     [] = new[39];
   logic addr_arr      [] = new[addr_width];
   logic key_arr       [] = new[SRAM_KEY_WIDTH];
   logic nonce_arr     [] = new[SRAM_BLOCK_WIDTH];
+  int   full_addr_width = addr_width + extra_addr_bits;
 
   key_arr   = {<<{key}};
   nonce_arr = {<<{nonce}};
-  for (int i = 0; i < addr_width; i++) begin
+  for (int i = 0; i < full_addr_width; i++) begin
     addr_arr[i] = addr[addr_lsb + i];
   end
 
@@ -107,7 +110,7 @@ local function logic [38:0] _sram_decrypt_read39(
   `uvm_info(`gfn, $sformatf("scr data: 0x%0x", rdata39), UVM_HIGH)
   rdata_arr = {<<{rdata39}};
   rdata_arr = sram_scrambler_pkg::decrypt_sram_data(
-      rdata_arr, 39, 39, addr_arr, addr_width, key_arr, nonce_arr
+      rdata_arr, 39, 39, addr_arr, full_addr_width, key_arr, nonce_arr
   );
   rdata39 = {<<{rdata_arr}};
   return rdata39;
@@ -119,11 +122,13 @@ virtual function void sram_encrypt_write32_integ(logic [bus_params_pkg::BUS_AW-1
                                                  logic [31:0]                       data,
                                                  logic [SRAM_KEY_WIDTH-1:0]         key,
                                                  logic [SRAM_BLOCK_WIDTH-1:0]       nonce,
+                                                 int                                extra_addr_bits,
                                                  bit   [38:0]                       flip_bits = 0);
-  logic [bus_params_pkg::BUS_AW-1:0] scr_addr = get_sram_encrypt_addr(addr, nonce);
-  _sram_encrypt_write39(addr, scr_addr, data, key, nonce, flip_bits);
+  logic [bus_params_pkg::BUS_AW-1:0] scr_addr = get_sram_encrypt_addr(addr, nonce, extra_addr_bits);
+  _sram_encrypt_write39(addr, scr_addr, data, key, nonce, extra_addr_bits, flip_bits);
 endfunction : sram_encrypt_write32_integ
 
+
 // This encrypts, possibly flips some bits to inject errors, and writes the resulting data
 // to a scrambled address.
 local function void _sram_encrypt_write39(logic [bus_params_pkg::BUS_AW-1:0] addr,
@@ -131,8 +136,9 @@ local function void _sram_encrypt_write39(logic [bus_params_pkg::BUS_AW-1:0] add
                                           logic [31:0]                 data,
                                           logic [SRAM_KEY_WIDTH-1:0]   key,
                                           logic [SRAM_BLOCK_WIDTH-1:0] nonce,
+                                          int                          extra_addr_bits,
                                           bit [38:0]                   flip_bits);
-  logic [38:0] scrambled_data = get_sram_encrypt32_intg_data(addr, data, key, nonce, flip_bits);
+  logic [38:0] scrambled_data = get_sram_encrypt32_intg_data(addr, data, key, nonce, extra_addr_bits, flip_bits);
   write39integ(scr_addr, scrambled_data);
 endfunction : _sram_encrypt_write39
 
@@ -145,7 +151,8 @@ endfunction : _sram_encrypt_write39
 virtual function void sram_inject_integ_error(logic [bus_params_pkg::BUS_AW-1:0] addr,
                                               logic [bus_params_pkg::BUS_AW-1:0] scr_addr,
                                               logic [SRAM_KEY_WIDTH-1:0]   key,
-                                              logic [SRAM_BLOCK_WIDTH-1:0] nonce);
+                                              logic [SRAM_BLOCK_WIDTH-1:0] nonce,
+                                              int extra_addr_bits);
   int max_attempts = 40;
   int attempt = 0;
 
@@ -154,8 +161,8 @@ virtual function void sram_inject_integ_error(logic [bus_params_pkg::BUS_AW-1:0]
     bit [38:0] rdata_integ;
     prim_secded_pkg::secded_inv_39_32_t dec;
     // The specific bits to be flipped should be irrelevant.
-    _sram_encrypt_write39(addr, scr_addr, data, key, nonce, 39'h1001);
-    rdata_integ = _sram_decrypt_read39(addr, scr_addr, key, nonce);
+    _sram_encrypt_write39(addr, scr_addr, data, key, nonce, extra_addr_bits, 39'h1001);
+    rdata_integ = _sram_decrypt_read39(addr, scr_addr, key, nonce, extra_addr_bits);
     dec = prim_secded_pkg::prim_secded_inv_39_32_dec(rdata_integ);
     if (dec.err) begin
       `uvm_info(`gfn, $sformatf(
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util_pkg.sv
index 68e205f0..b9bc4890 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/otp_scrambler_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/otp_scrambler_pkg.sv
index 4ea062ec..74a8cf6c 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/otp_scrambler_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/otp_scrambler_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/sram_scrambler_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/sram_scrambler_pkg.sv
index f832a5f5..b86dd436 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/sram_scrambler_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_bkdr_util/sram_scrambler_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -40,7 +40,8 @@ package sram_scrambler_pkg;
   // Fixed data block size - PRINCE cipher operates on 64-bit data blocks.
   parameter int SRAM_BLOCK_WIDTH = 64;
 
-  parameter int NUM_ROUNDS = 2;
+  parameter int NUM_PRINCE_ROUNDS_HALF = 3;
+  parameter int NUM_SP_ROUNDS = 2;
 
   // Create a generic typedef for dynamic array of logic to be able to return these values.
   typedef logic state_t[];
@@ -97,10 +98,10 @@ package sram_scrambler_pkg;
     return state_out;
   endfunction : perm_layer
 
-  // Performs NUM_ROUNDS full encryption rounds
+  // Performs NUM_SP_ROUNDS full encryption rounds
   function automatic state_t sp_encrypt(state_t data, int width, state_t key);
     logic state[] = new[width](data);
-    for (int i = 0; i < NUM_ROUNDS; i++) begin
+    for (int i = 0; i < NUM_SP_ROUNDS; i++) begin
       // xor the data and key
       for (int j = 0; j < width; j++) begin
         state[j] = state[j] ^ key[j];
@@ -119,10 +120,10 @@ package sram_scrambler_pkg;
     return state;
   endfunction : sp_encrypt
 
-  // Performs NUM_ROUNDS full decryption rounds
+  // Performs NUM_SP_ROUNDS full decryption rounds
   function automatic state_t sp_decrypt(state_t data, int width, state_t key);
     logic state[] = new[width](data);
-    for (int i = 0; i < NUM_ROUNDS; i++) begin
+    for (int i = 0; i < NUM_SP_ROUNDS; i++) begin
       // xor data and key
       for (int j = 0; j < width; j++) begin
         state[j] = state[j] ^ key[j];
@@ -147,7 +148,7 @@ package sram_scrambler_pkg;
   // Should not be called directly.
   function automatic state_t gen_keystream(logic addr[], int addr_width,
                                            logic key[], logic nonce[]);
-    logic [NUM_ROUNDS-1:0][SRAM_BLOCK_WIDTH-1:0] prince_result_arr;
+    logic [NUM_PRINCE_ROUNDS_HALF-1:0][SRAM_BLOCK_WIDTH-1:0] prince_result_arr;
 
     logic [SRAM_BLOCK_WIDTH-1:0]  prince_plaintext;
     logic [SRAM_KEY_WIDTH-1:0]    prince_key;
@@ -182,7 +183,7 @@ package sram_scrambler_pkg;
                                                  .key(prince_key),
                                                  .old_key_schedule(0),
                                                  .ciphertext(prince_result_arr));
-    prince_result = prince_result_arr[NUM_ROUNDS-1];
+    prince_result = prince_result_arr[NUM_PRINCE_ROUNDS_HALF-1];
 
     key_out = {<< {prince_result}};
 
@@ -234,13 +235,13 @@ package sram_scrambler_pkg;
 
   endfunction : decrypt_sram_addr
 
-  // SRAM data encryption is more involved, we need to run 2 rounds of PRINCE on the nonce and key
+  // SRAM data encryption is more involved, we need to run 3 rounds of PRINCE on the nonce and key
   // and then XOR the result with the data.
   //
-  // After that, the XORed data neeeds to them be passed through the S&P network one byte at a time.
+  // Optionally, the XORed data can be passed through the S&P network.
   function automatic state_t encrypt_sram_data(logic data[], int data_width, int sp_width,
                                                logic addr[], int addr_width,
-                                               logic key[], logic nonce[]);
+                                               logic key[], logic nonce[], bit use_sp_layer = 0);
     logic keystream[] = new[SRAM_BLOCK_WIDTH];
     logic data_enc[] = new[data_width];
     logic byte_to_enc[] = new[8];
@@ -262,31 +263,33 @@ package sram_scrambler_pkg;
       data_enc[i] = data[i] ^ keystream[i % ks_width];
     end
 
-    if (data_width == sp_width) begin
-      // pass the entire word through the subst/perm network at once (the next cases would give the
-      // same results too, but this should be a bit more efficient)
-      data_enc = sp_encrypt(data_enc, data_width, zero_key);
-    end else if (sp_width == 8) begin
-      // pass each byte of the encoded result through the subst/perm network (special case of the
-      // general code below)
-      for (int i = 0; i < data_width / 8; i++) begin
-        byte_to_enc = data_enc[i*8 +: 8];
-        enc_byte = sp_encrypt(byte_to_enc, 8, zero_key);
-        data_enc[i*8 +: 8] = enc_byte;
-      end
-    end else begin
-      // divide the word into sp_width chunks to pass it through the subst/perm network
-      for (int chunk_lsb = 0; chunk_lsb < data_width; chunk_lsb += sp_width) begin
-        int bits_remaining = data_width - chunk_lsb;
-        int chunk_width = (bits_remaining < sp_width) ? bits_remaining : sp_width;
-        logic chunk[] = new[chunk_width];
-
-        for (int j = 0; j < chunk_width; j++) begin
-          chunk[j] = data_enc[chunk_lsb + j];
+    if (use_sp_layer) begin
+      if (data_width == sp_width) begin
+        // pass the entire word through the subst/perm network at once (the next cases would give the
+        // same results too, but this should be a bit more efficient)
+        data_enc = sp_encrypt(data_enc, data_width, zero_key);
+      end else if (sp_width == 8) begin
+        // pass each byte of the encoded result through the subst/perm network (special case of the
+        // general code below)
+        for (int i = 0; i < data_width / 8; i++) begin
+          byte_to_enc = data_enc[i*8 +: 8];
+          enc_byte = sp_encrypt(byte_to_enc, 8, zero_key);
+          data_enc[i*8 +: 8] = enc_byte;
         end
-        chunk = sp_encrypt(chunk, chunk_width, zero_key);
-        for (int j = 0; j < chunk_width; j++) begin
-          data_enc[chunk_lsb + j] = chunk[j];
+      end else begin
+        // divide the word into sp_width chunks to pass it through the subst/perm network
+        for (int chunk_lsb = 0; chunk_lsb < data_width; chunk_lsb += sp_width) begin
+          int bits_remaining = data_width - chunk_lsb;
+          int chunk_width = (bits_remaining < sp_width) ? bits_remaining : sp_width;
+          logic chunk[] = new[chunk_width];
+
+          for (int j = 0; j < chunk_width; j++) begin
+            chunk[j] = data_enc[chunk_lsb + j];
+          end
+          chunk = sp_encrypt(chunk, chunk_width, zero_key);
+          for (int j = 0; j < chunk_width; j++) begin
+            data_enc[chunk_lsb + j] = chunk[j];
+          end
         end
       end
     end
@@ -296,7 +299,7 @@ package sram_scrambler_pkg;
 
   function automatic state_t decrypt_sram_data(logic data[], int data_width, int sp_width,
                                                logic addr[], int addr_width,
-                                               logic key[], logic nonce[]);
+                                               logic key[], logic nonce[], bit use_sp_layer = 0);
     logic keystream[] = new[SRAM_BLOCK_WIDTH];
     logic data_dec[] = new[data_width];
     logic byte_to_dec[] = new[8];
@@ -312,38 +315,45 @@ package sram_scrambler_pkg;
     // Generate the keystream
     keystream = gen_keystream(addr, addr_width, key, nonce);
 
-    if (data_width == sp_width) begin
-      // pass the entire word through the subst/perm network at once (the next cases would give the
-      // same results too, but this should be a bit more efficient)
-      data_dec = sp_decrypt(data, data_width, zero_key);
-    end else if (sp_width == 8) begin
-      // pass each byte of the data through the subst/perm network (special case of the general code
-      // below)
-      for (int i = 0; i < data_width / 8; i++) begin
-        byte_to_dec = data[i*8 +: 8];
-        dec_byte = sp_decrypt(byte_to_dec, 8, zero_key);
-        data_dec[i*8 +: 8] = dec_byte;
-      end
-    end else begin
-      // divide the word into sp_width chunks to pass it through the subst/perm network
-      for (int chunk_lsb = 0; chunk_lsb < data_width; chunk_lsb += sp_width) begin
-        int bits_remaining = data_width - chunk_lsb;
-        int chunk_width = (bits_remaining < sp_width) ? bits_remaining : sp_width;
-        logic chunk[] = new[chunk_width];
-
-        for (int j = 0; j < chunk_width; j++) begin
-          chunk[j] = data[chunk_lsb + j];
+    if (use_sp_layer) begin
+      if (data_width == sp_width) begin
+        // pass the entire word through the subst/perm network at once (the next cases would give the
+        // same results too, but this should be a bit more efficient)
+        data_dec = sp_decrypt(data, data_width, zero_key);
+      end else if (sp_width == 8) begin
+        // pass each byte of the data through the subst/perm network (special case of the general code
+        // below)
+        for (int i = 0; i < data_width / 8; i++) begin
+          byte_to_dec = data[i*8 +: 8];
+          dec_byte = sp_decrypt(byte_to_dec, 8, zero_key);
+          data_dec[i*8 +: 8] = dec_byte;
         end
-        chunk = sp_decrypt(chunk, chunk_width, zero_key);
-        for (int j = 0; j < chunk_width; j++) begin
-          data_dec[chunk_lsb + j] = chunk[j];
+      end else begin
+        // divide the word into sp_width chunks to pass it through the subst/perm network
+        for (int chunk_lsb = 0; chunk_lsb < data_width; chunk_lsb += sp_width) begin
+          int bits_remaining = data_width - chunk_lsb;
+          int chunk_width = (bits_remaining < sp_width) ? bits_remaining : sp_width;
+          logic chunk[] = new[chunk_width];
+
+          for (int j = 0; j < chunk_width; j++) begin
+            chunk[j] = data[chunk_lsb + j];
+          end
+          chunk = sp_decrypt(chunk, chunk_width, zero_key);
+          for (int j = 0; j < chunk_width; j++) begin
+            data_dec[chunk_lsb + j] = chunk[j];
+          end
         end
       end
-    end
 
-    // XOR result data with the keystream
-    for (int i = 0; i < data_width; i++) begin
-      data_dec[i] = data_dec[i] ^ keystream[i % ks_width];
+      // XOR result data with the keystream
+      for (int i = 0; i < data_width; i++) begin
+        data_dec[i] = data_dec[i] ^ keystream[i % ks_width];
+      end
+    end else begin
+      // XOR result data with the keystream
+      for (int i = 0; i < data_width; i++) begin
+        data_dec[i] = data[i] ^ keystream[i % ks_width];
+      end
     end
 
     return data_dec;
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_model/mem_model.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_model/mem_model.core
index 5eadedce..a7abbf3a 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_model/mem_model.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_model/mem_model.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:mem_model"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_model/mem_model.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_model/mem_model.sv
index b698c28f..f4579b86 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_model/mem_model.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_model/mem_model.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -44,7 +44,7 @@ class mem_model #(int AddrWidth = bus_params_pkg::BUS_AW,
 
   function void compare_byte(mem_addr_t addr, logic [7:0] act_data);
    `uvm_info(`gfn, $sformatf("Compare Mem : Addr[0x%0h], Act Data[0x%0h], Exp Data[0x%0h]",
-                             addr, act_data, system_memory[addr]), UVM_MEDIUM)
+                             addr, act_data, system_memory[addr]), UVM_HIGH)
     `DV_CHECK_CASE_EQ(act_data, system_memory[addr],
                       $sformatf("addr 0x%0h read out mismatch", addr))
   endfunction
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_model/mem_model_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_model/mem_model_pkg.sv
index 5e3653c9..975e3bd4 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_model/mem_model_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/mem_model/mem_model_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent.core
index 9ba58d63..85a59bbb 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:push_pull_agent:0.1"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent.sv
index e9c9910d..ecb01035 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_cfg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_cfg.sv
index f9d24e6f..75eee996 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_cfg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_cfg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -142,12 +142,14 @@ class push_pull_agent_cfg #(parameter int HostDataWidth = 32,
   // Setter method for the user data queues - must be called externally to place specific user-data
   // to be sent by the driver.
   function void add_h_user_data(bit [HostDataWidth-1:0] data);
+    `uvm_info(`gfn, $sformatf("Added h user data %p", data), UVM_HIGH)
     h_user_data_q.push_back(data);
   endfunction
 
   // Setter method for the user data queues - must be called externally to place specific user-data
   // to be sent by the driver.
   function void add_d_user_data(bit [DeviceDataWidth-1:0] data);
+    `uvm_info(`gfn, $sformatf("Added d user data %p", data), UVM_HIGH)
     d_user_data_q.push_back(data);
   endfunction
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_cov.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_cov.sv
index 9f9ddead..eddeff02 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_cov.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_cov.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_pkg.sv
index 41b5fc8b..0b2e6ccc 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_driver_lib.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_driver_lib.sv
index 92dca530..6d1e3e6a 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_driver_lib.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_driver_lib.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_if.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_if.sv
index 49c8c49a..ee28a021 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_if.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_if.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_item.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_item.sv
index 7a806598..07c13868 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_item.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_item.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_monitor.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_monitor.sv
index 240831be..2f8cd057 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_monitor.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_monitor.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -21,9 +21,10 @@ class push_pull_monitor #(parameter int HostDataWidth = 32,
 
   task run_phase(uvm_phase phase);
     @(posedge cfg.vif.rst_n);
+    cfg.in_reset = 0;
     fork
       monitor_reset();
-      collect_trans(phase);
+      collect_trans();
       // Collect partial pull reqs for the reactive pull device agent.
       collect_pull_req();
       collect_cov();
@@ -49,7 +50,7 @@ class push_pull_monitor #(parameter int HostDataWidth = 32,
   // Collect fully-completed transactions.
   //
   // TODO : sample covergroups
-  virtual protected task collect_trans(uvm_phase phase);
+  virtual protected task collect_trans();
     if (cfg.agent_type == PushAgent) begin
       forever begin
         @(cfg.vif.mon_cb);
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_sequencer.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_sequencer.sv
index 06c64595..510f60a4 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_sequencer.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_sequencer.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_base_seq.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_base_seq.sv
index 66b858ab..e91bce81 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_base_seq.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_base_seq.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_device_seq.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_device_seq.sv
index 0b15f3f7..6b7ef97d 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_device_seq.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_device_seq.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_host_seq.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_host_seq.sv
index 98c3b029..f1aa3c73 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_host_seq.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_host_seq.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_indefinite_host_seq.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_indefinite_host_seq.sv
index 90c12267..ebee1244 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_indefinite_host_seq.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_indefinite_host_seq.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_seq_list.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_seq_list.sv
index d591fb7f..ec836cac 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_seq_list.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/push_pull_agent/seq_lib/push_pull_seq_list.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/str_utils/str_utils.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/str_utils/str_utils.core
index 565c2ee4..14eebda7 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/str_utils/str_utils.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/str_utils/str_utils.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:str_utils"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/str_utils/str_utils_pkg.sv b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/str_utils/str_utils_pkg.sv
index dfd73a4f..5bd5ac97 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/str_utils/str_utils_pkg.sv
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/sv/str_utils/str_utils_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/common.tcl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/common.tcl
index 81f7b985..cfa0b37b 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/common.tcl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/common.tcl
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/bazel.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/bazel.hjson
index 8453b279..407bfb11 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/bazel.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/bazel.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/common_modes.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/common_modes.hjson
index 7cdf7102..d74d13eb 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/common_modes.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/common_modes.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
@@ -52,14 +52,14 @@
     // in two ways. One of them is setting the pre-processor macro `BUILD_SEED` to the seed value,
     // which is done below. The SystemVerilog testbench sources can use the `BUILD_SEED` macro
     // value to set some design constants (such as parameters) upon instantiation. The `BUILD_SEED`,
-    // if not set externally (by passing the --build-seed switch) is set to 1 in 
-    // `hw/dv/sv/dv_utils/dv_macros.svh`. The other way is by passing the {seed} value to utility 
-    // scripts that generate packages that contain randomized constants. These utility scripts can 
-    // be invoked as a `pre_build_cmd`, wrapped within the `build_seed` sim mode in the DUT 
+    // if not set externally (by passing the --build-seed switch) is set to 1 in
+    // `hw/dv/sv/dv_utils/dv_macros.svh`. The other way is by passing the {seed} value to utility
+    // scripts that generate packages that contain randomized constants. These utility scripts can
+    // be invoked as a `pre_build_cmd`, wrapped within the `build_seed` sim mode in the DUT
     // simulation configuration Hjson file. All forms of build randomization must be wrapped within
-    // this `build_seed` sim mode. They will all use the same {seed} value, which allows us to 
-    // deterministically reproduce failures. The `--build-seed` switch is expected to be passed 
-    // when running the nightly regressions. The `seed` value set by dvsim is a 32-bit unsigned 
+    // this `build_seed` sim mode. They will all use the same {seed} value, which allows us to
+    // deterministically reproduce failures. The `--build-seed` switch is expected to be passed
+    // when running the nightly regressions. The `seed` value set by dvsim is a 32-bit unsigned
     // integer (unless specified on the command-line).
     {
       name: build_seed
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson
index e2a3e0a2..1cf530b0 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/dsim.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/dsim.hjson
index 42171a58..84f35461 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/dsim.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/dsim.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/fusesoc.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/fusesoc.hjson
index c085052b..1e441668 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/fusesoc.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/fusesoc.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/questa.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/questa.hjson
index 794fd904..5e6abec0 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/questa.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/questa.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/riviera.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/riviera.hjson
index 1169fdd0..30352752 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/riviera.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/riviera.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/sim.mk b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/sim.mk
index 0f8f6b7f..692b5aad 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/sim.mk
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/sim.mk
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -19,9 +19,9 @@ pre_build:
 	mkdir -p ${build_dir}
 ifneq (${pre_build_cmds},)
 	# pre_build_cmds are likely changing the in-tree sources. We hence use FLOCK
-        # utility to prevent multiple builds that may be running in parallel from
-        # stepping on each other. TODO: Enforce the list of pre_build_cmds is
-        # identical across all build modes.
+	# utility to prevent multiple builds that may be running in parallel from
+	# stepping on each other. TODO: Enforce the list of pre_build_cmds is
+	# identical across all build modes.
 	${LOCK_ROOT_DIR} "cd ${build_dir} && ${pre_build_cmds}"
 endif
 
@@ -124,7 +124,7 @@ ifneq (${sw_images},)
 				--output=label_kind | cut -f1 -d' '); \
 			if [[ $${kind} == "opentitan_test" \
 					|| $${bazel_label} == "//sw/device/lib/testing/test_rom:test_rom_sim_dv" \
-					|| $${bazel_label} == "//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv" ]]; then \
+					|| $${bazel_label} == "//sw/device/silicon_creator/rom:mask_rom_sim_dv" ]]; then \
 				for artifact in $$($${bazel_cmd} cquery $${bazel_airgapped_opts} \
 					$${bazel_label} \
 					--ui_event_filters=-info \
@@ -229,18 +229,18 @@ cov_analyze:
 	${cov_analyze_cmd} ${cov_analyze_opts}
 
 .PHONY: build \
-        pre_build \
-        gen_sv_flist \
-        do_build \
-        post_build \
-        build_result \
-        run \
-        pre_run \
-        sw_build \
-        simulate \
-        post_run \
-        run_result \
-        debug_waves \
-        cov_merge \
-        cov_analyze \
-        cov_report
+	pre_build \
+	gen_sv_flist \
+	do_build \
+	post_build \
+	build_result \
+	run \
+	pre_run \
+	sw_build \
+	simulate \
+	post_run \
+	run_result \
+	debug_waves \
+	cov_merge \
+	cov_analyze \
+	cov_report
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson
index 0e673ca6..505e3bfc 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson
index d31480cc..fb8319b3 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/fpv_csr_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/fpv_csr_testplan.hjson
index 8c5c7cce..88ad3b9b 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/fpv_csr_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/fpv_csr_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson
index 0db9d533..905c6ae7 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/mem_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/mem_testplan.hjson
index ec6f59de..82f5751b 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/mem_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/mem_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/passthru_mem_intg_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/passthru_mem_intg_testplan.hjson
index 20ddfcbd..b2a4c199 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/passthru_mem_intg_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/passthru_mem_intg_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson
index 5e2b86ca..c66deb7b 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_double_lfsr_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_double_lfsr_testplan.hjson
index e81e054f..b2807a2b 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_double_lfsr_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_double_lfsr_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson
index 65c44250..e205cc9a 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_one_hot_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_one_hot_testplan.hjson
index ac54631d..631e2f0c 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_one_hot_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_one_hot_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson
index 6cc64557..8e642c5e 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson
index 3e8097cc..2785f3af 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson
index f3c63d6c..f405656a 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_wo_intg_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_wo_intg_testplan.hjson
index be1d1e0a..13dfb933 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_wo_intg_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_wo_intg_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
@@ -23,7 +23,7 @@
               - address and size aren't aligned, e.g. `a_address = 0x01`, `a_size != 0`
               - size is greater than 2
             - OpenTitan defined error cases
-              - access unmapped address, expect `d_error = 1` when `devmode_i == 1`
+              - access unmapped address, expect `d_error = 1`
               - write a CSR with unaligned address, e.g. `a_address[1:0] != 0`
               - write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
               - write a memory with `a_mask != '1` when it doesn't support partial accesses
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson
index 808d01ec..21c8ddff 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson
index 2f17aec2..af3d97b6 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson
index 41132b76..e83c96f8 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/mem_tests.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/mem_tests.hjson
index b3760144..de9fa5c2 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/mem_tests.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/mem_tests.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/passthru_mem_intg_tests.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/passthru_mem_intg_tests.hjson
index ec898134..46df8854 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/passthru_mem_intg_tests.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/passthru_mem_intg_tests.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson
index 593f912d..6ac55da5 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson
index 8f52b84c..1f1848da 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_all_test.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_all_test.hjson
index 88d3bfaa..297ef1aa 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_all_test.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_all_test.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -10,7 +10,7 @@
     {
       name: "{name}_stress_all"
       uvm_test_seq: "{name}_stress_all_vseq"
-      // 10ms
+      // 10s
       run_opts: ["+test_timeout_ns=10000000000"]
       run_timeout_mins: 180
     }
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_tests.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_tests.hjson
index 10e1db7b..2fe58c65 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_tests.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_tests.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -10,7 +10,7 @@
       name: "{name}_stress_all_with_rand_reset"
       uvm_test_seq: "{name}_common_vseq"
       run_opts: ["+run_stress_all_with_rand_reset",
-                 // 10ms
+                 // 10s
                  "+test_timeout_ns=10000000000",
                  "+stress_seq={name}_stress_all_vseq"]
       run_timeout_mins: 180
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson
index af3e1d04..fd0d1a16 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/vcs.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/vcs.hjson
index 10bf616d..b11e601f 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/vcs.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/vcs.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
@@ -113,7 +113,7 @@
 
   run_opts:   ["-licqueue",
                "-ucli -do {run_script}",
-               "+ntb_random_seed={seed}",
+               "+ntb_random_seed={svseed}",
                // Disable the display of the SystemVerilog assert and cover statement summary
                // at the end of simulation. This summary is list of assertions that started but
                // did not finish because the simulation terminated, or assertions that did not
@@ -134,7 +134,7 @@
 
   // Individual test specific coverage data - this will be deleted if the test fails
   // so that coverage from failiing tests is not included in the final report.
-  cov_db_test_dir_name: "{run_dir_name}.{seed}"
+  cov_db_test_dir_name: "{run_dir_name}.{svseed}"
   cov_db_test_dir: "{cov_db_dir}/snps/coverage/db/testdata/{cov_db_test_dir_name}"
 
   // Merging coverage.
@@ -147,10 +147,14 @@
                      "-full64",
                      // No need of generating report when merging coverage.
                      "-noreport",
+                     // Parallel merge is slower than serial merge for most
+                     // small blocks, and the corresponding flags are commented
+                     // out. If this becomes problematic and you have a powerful
+                     // machine available, uncomment the three flags below.
                      // Merge results from tests in parallel.
-                     "-parallel",
-                     "-parallel_split 20",
-                     "-parallel_temproot {cov_merge_dir}",
+                     // "-parallel",
+                     // "-parallel_split 20",
+                     // "-parallel_temproot {cov_merge_dir}",
                      "+urg+lic+wait",
                      // Merge same assert instances found in different VDBs.
                      "-merge_across_libs",
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/verilator.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/verilator.hjson
index 1241376f..56ab5d25 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/verilator.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/verilator.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
@@ -69,9 +69,7 @@
                // "--x-initial unique",
                ]
 
-  run_opts: [// Set random seed.
-             // "+verilator+seed+{seed}",
-             ]
+  run_opts: []
 
   // Supported wave dumping formats (in order of preference).
   supported_wave_formats: ["fst"]
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/xcelium.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/xcelium.hjson
index 53229307..b523e4c1 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/xcelium.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/dvsim/xcelium.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
@@ -68,7 +68,7 @@
                "-64bit -xmlibdirname {build_db_dir}",
                // Use the same snapshot name set during the build step.
                "-r {tb}",
-               "+SVSEED={seed}",
+               "+SVSEED={svseed}",
                "{uvm_testname_plusarg}",
                "{uvm_testseq_plusarg}",
                // Ignore "IEEE 1800-2009 SystemVerilog simulation semantics" warning
@@ -129,7 +129,7 @@
 
   // Individual test specific coverage data - this will be deleted if the test fails
   // so that coverage from failiing tests is not included in the final report.
-  cov_db_test_dir_name: "{run_dir_name}.{seed}"
+  cov_db_test_dir_name: "{run_dir_name}.{svseed}"
   cov_db_test_dir:      "{cov_db_dir}/{cov_db_test_dir_name}"
 
   // Merging coverage.
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/questa/sim.tcl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/questa/sim.tcl
index 82916769..7279a284 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/questa/sim.tcl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/questa/sim.tcl
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/ralgen/ralgen.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/ralgen/ralgen.core
index b277f413..8a451c48 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/ralgen/ralgen.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/ralgen/ralgen.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/ralgen/ralgen.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/ralgen/ralgen.py
index b8680511..4281666e 100755
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/ralgen/ralgen.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/ralgen/ralgen.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""FuseSoc generator for UVM RAL package created with either regtool or
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/riviera/riviera_run.do b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/riviera/riviera_run.do
index 68c40759..6a9de01d 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/riviera/riviera_run.do
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/riviera/riviera_run.do
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/sim.tcl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/sim.tcl
index c513490e..98a5694d 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/sim.tcl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/sim.tcl
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/common_cov_excl.cfg b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/common_cov_excl.cfg
index 35a32c41..7c5b5c4c 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/common_cov_excl.cfg
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/common_cov_excl.cfg
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/cover.cfg b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/cover.cfg
index ccde34a6..79068f07 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/cover.cfg
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/cover.cfg
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/cover_reg_top.cfg b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/cover_reg_top.cfg
index 771cd563..430f2be9 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/cover_reg_top.cfg
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/cover_reg_top.cfg
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/fsm_reset_cov.cfg b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/fsm_reset_cov.cfg
index 6207462b..1b66a198 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/fsm_reset_cov.cfg
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/fsm_reset_cov.cfg
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/unr.cfg b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/unr.cfg
index 290f3a45..ca91d13e 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/unr.cfg
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/unr.cfg
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/xprop.cfg b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/xprop.cfg
index da9650f8..aaf7edfe 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/xprop.cfg
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/vcs/xprop.cfg
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/waves.tcl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/waves.tcl
index eeb76e2b..3a4ac3ba 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/waves.tcl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/waves.tcl
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/common.ccf b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/common.ccf
index 9d003aed..bf129833 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/common.ccf
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/common.ccf
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/common_cov_excl.tcl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/common_cov_excl.tcl
index 6c9243f9..37083389 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/common_cov_excl.tcl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/common_cov_excl.tcl
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cov_merge.tcl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cov_merge.tcl
index c369810c..1a313857 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cov_merge.tcl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cov_merge.tcl
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cov_report.tcl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cov_report.tcl
index 3d5c2356..cecbc956 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cov_report.tcl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cov_report.tcl
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -8,6 +8,10 @@
 # exclusion script and the coverage refinement files are passed to the IMC invocation using the
 # -load, -init and -load_refinement switches respectively (whichever ones are applicable).
 
+# Generate "detachable" reports that work despite browser Cross-Origin Request Security protection.
+# They have the downside that you have to select the .report file yourself in-browser.
+config reports.detachable_report_data -set true
+
 # Set the output directory for the reports database using the env var 'cov_report_dir'.
 # The supplied env var may have quotes or spaces that needs to be trimmed.
 set cov_report_dir [string trim $::env(cov_report_dir) " \"'"]
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cover.ccf b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cover.ccf
index 7752f489..9a80e7f2 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cover.ccf
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cover.ccf
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cover_reg_top.ccf b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cover_reg_top.ccf
index ba86d3d4..3bd0f5e9 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cover_reg_top.ccf
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cover_reg_top.ccf
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cover_reg_top_toggle_excl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cover_reg_top_toggle_excl
index ae30c553..caf1bc03 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cover_reg_top_toggle_excl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/cover_reg_top_toggle_excl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/unr.cfg b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/unr.cfg
index 9dbea90d..7918effd 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/unr.cfg
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/xcelium/unr.cfg
@@ -1,9 +1,9 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-check_unr -setup 
+check_unr -setup
 
-#Setup the clock and reset the design 
+#Setup the clock and reset the design
 clock -infer
 reset ~dut.rst_ni
 get_reset_info
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/dpi_memutil.cc b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/dpi_memutil.cc
index a6fc452d..945ea392 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/dpi_memutil.cc
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/dpi_memutil.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/dpi_memutil.h b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/dpi_memutil.h
index a41aae99..48656796 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/dpi_memutil.h
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/dpi_memutil.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 #ifndef OPENTITAN_HW_DV_VERILATOR_CPP_DPI_MEMUTIL_H_
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/ecc32_mem_area.cc b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/ecc32_mem_area.cc
index d5926fa1..5136d9c3 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/ecc32_mem_area.cc
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/ecc32_mem_area.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/ecc32_mem_area.h b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/ecc32_mem_area.h
index e42ea2dd..1ba00530 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/ecc32_mem_area.h
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/ecc32_mem_area.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/mem_area.cc b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/mem_area.cc
index 4b29f1fc..58455e49 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/mem_area.cc
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/mem_area.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/mem_area.h b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/mem_area.h
index 84b57d94..05cabf50 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/mem_area.h
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/mem_area.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/ranged_map.h b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/ranged_map.h
index 4bc7cbae..9dcd8d16 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/ranged_map.h
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/ranged_map.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 #ifndef OPENTITAN_HW_DV_VERILATOR_CPP_RANGED_MAP_H_
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/scrambled_ecc32_mem_area.cc b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/scrambled_ecc32_mem_area.cc
index 65f2b36b..c67a9291 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/scrambled_ecc32_mem_area.cc
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/scrambled_ecc32_mem_area.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -162,9 +162,10 @@ void ScrambledEcc32MemArea::WriteBuffer(uint8_t buf[SV_MEM_WIDTH_BYTES],
 std::vector<uint8_t> ScrambledEcc32MemArea::ReadUnscrambled(
     const uint8_t buf[SV_MEM_WIDTH_BYTES], uint32_t src_word) const {
   std::vector<uint8_t> scrambled_data(buf, buf + GetPhysWidthByte());
-  return scramble_decrypt_data(
-      scrambled_data, GetPhysWidth(), 39, AddrIntToBytes(src_word, addr_width_),
-      addr_width_, GetScrambleNonce(), GetScrambleKey(), repeat_keystream_);
+  return scramble_decrypt_data(scrambled_data, GetPhysWidth(), 39,
+                               AddrIntToBytes(src_word, addr_width_),
+                               addr_width_, GetScrambleNonce(),
+                               GetScrambleKey(), repeat_keystream_, false);
 }
 
 void ScrambledEcc32MemArea::ReadBuffer(std::vector<uint8_t> &data,
@@ -196,7 +197,8 @@ void ScrambledEcc32MemArea::ScrambleBuffer(uint8_t buf[SV_MEM_WIDTH_BYTES],
   // Scramble data with integrity
   scramble_buf = scramble_encrypt_data(
       scramble_buf, GetPhysWidth(), 39, AddrIntToBytes(dst_word, addr_width_),
-      addr_width_, GetScrambleNonce(), GetScrambleKey(), repeat_keystream_);
+      addr_width_, GetScrambleNonce(), GetScrambleKey(), repeat_keystream_,
+      false);
 
   // Copy scrambled data to write buffer
   std::copy(scramble_buf.begin(), scramble_buf.end(), &buf[0]);
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/scrambled_ecc32_mem_area.h b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/scrambled_ecc32_mem_area.h
index 31055b1a..e3443878 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/scrambled_ecc32_mem_area.h
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/scrambled_ecc32_mem_area.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/sv_scoped.cc b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/sv_scoped.cc
index 6f537ae8..52a001a8 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/sv_scoped.cc
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/sv_scoped.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/sv_scoped.h b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/sv_scoped.h
index e9c75ff2..49ca1fc3 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/sv_scoped.h
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/sv_scoped.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/verilator_memutil.cc b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/verilator_memutil.cc
index 66ee5d7a..95115281 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/verilator_memutil.cc
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/verilator_memutil.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/verilator_memutil.h b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/verilator_memutil.h
index 128500ba..961554bf 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/verilator_memutil.h
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/cpp/verilator_memutil.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 #ifndef OPENTITAN_HW_DV_VERILATOR_CPP_VERILATOR_MEMUTIL_H_
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_dpi.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_dpi.core
index 7de37f05..a8957e16 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_dpi.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_dpi.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_dpi_scrambled.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_dpi_scrambled.core
index 8467e238..6c27c642 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_dpi_scrambled.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_dpi_scrambled.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_dpi_scrambled_opts.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_dpi_scrambled_opts.hjson
index fc9cca60..ee8ae81f 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_dpi_scrambled_opts.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_dpi_scrambled_opts.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_verilator.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_verilator.core
index b2f27c15..5c2e199d 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_verilator.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/memutil_verilator.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/sim_ctrl_extension.h b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/sim_ctrl_extension.h
index 87c42b50..96460cfb 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/sim_ctrl_extension.h
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/sim_ctrl_extension.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilated_toplevel.cc b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilated_toplevel.cc
index 9c2ef91f..6f054ab3 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilated_toplevel.cc
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilated_toplevel.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilated_toplevel.h b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilated_toplevel.h
index 1d7cc7de..f8af5b36 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilated_toplevel.h
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilated_toplevel.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.cc b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.cc
index d92b1b36..8ae0622d 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.cc
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.h b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.h
index 9e60d1ab..5e90e975 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.h
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/simutil_verilator.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/simutil_verilator.core
index d14327ae..9e2dfc1d 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/simutil_verilator.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/verilator/simutil_verilator/simutil_verilator.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/common.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/common.core
index 4bcd8f3c..20338eaf 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/common.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/common.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:lint:common:0.1"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/comportable.core b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/comportable.core
index f74083e8..851b6c17 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/comportable.core
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/comportable.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:lint:comportable:0.1"
@@ -20,5 +20,3 @@ targets:
     filesets:
       - tool_verilator  ? (files_verilator_waiver)
       - tool_ascentlint ? (files_ascentlint_waiver)
-
-
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/ascentlint/ascentlint-config.tcl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/ascentlint/ascentlint-config.tcl
index a4113b0a..d82ed9ab 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/ascentlint/ascentlint-config.tcl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/ascentlint/ascentlint-config.tcl
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,5 +15,4 @@ set ri_max_single_range_bits 32768
 
 # Increase the maximum loop to 3200 (KmacStateW X 2)
 # this is a temporary fix for non-ASCII character in AscentLint log
-set ri_max_loop_unroll 3200 
-
+set ri_max_loop_unroll 3200
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/ascentlint/common.waiver b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/ascentlint/common.waiver
index f254de2b..6c963949 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/ascentlint/common.waiver
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/ascentlint/common.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -9,5 +9,3 @@
 waive -rules {HIER_NET_NOT_READ HIER_BRANCH_NOT_READ} -regexp {unused_.*}
 waive -rules {HIER_NET_NOT_READ HIER_BRANCH_NOT_READ} -regexp {gen_.*\.unused_.*}
 waive -rules {ONE_BRANCH} -regexp {unique case statement has only one branch}
-
-
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/ascentlint/comportable.waiver b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/ascentlint/comportable.waiver
index dcf62a97..e8515dab 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/ascentlint/comportable.waiver
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/ascentlint/comportable.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/ascentlint.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/ascentlint.hjson
index 7b76f3e2..088a7522 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/ascentlint.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/ascentlint.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/common_lint_cfg.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/common_lint_cfg.hjson
index 05571b5b..9ec23bdf 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/common_lint_cfg.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/common_lint_cfg.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
@@ -29,11 +29,12 @@
                "{fusesoc_core}"]
 
   // Determines which message severities to print into report summaries.
-  report_severities: ["warning", "error"]
+  report_severities: ["info", "warning", "error"]
   // Determines which message severities lead to a pass/fail.
   fail_severities: ["warning", "error"]
   // Define message bucket categories and severities.
   message_buckets: [
+    {category: "flow", severity: "info",     label: ""},
     {category: "flow", severity: "warning",  label: ""},
     {category: "flow", severity: "error",    label: ""},
     {category: "lint", severity: "info",     label: ""},
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/lint.mk b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/lint.mk
index afca82ee..d7ce4708 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/lint.mk
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/lint.mk
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/veriblelint.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/veriblelint.hjson
index a3b8f2f8..601164fa 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/veriblelint.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/veriblelint.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/verilator.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/verilator.hjson
index 62bf0b38..46419053 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/verilator.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/dvsim/verilator.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/veriblelint/lowrisc-styleguide.rules.verible_lint b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/veriblelint/lowrisc-styleguide.rules.verible_lint
index 6f03c3f2..c7678d28 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/veriblelint/lowrisc-styleguide.rules.verible_lint
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/veriblelint/lowrisc-styleguide.rules.verible_lint
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/verilator/common.vlt b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/verilator/common.vlt
index 625b46a8..5416c164 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/verilator/common.vlt
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/verilator/common.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/verilator/comportable.vlt b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/verilator/comportable.vlt
index 5da936b4..9b914ca5 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/verilator/comportable.vlt
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/lint/tools/verilator/comportable.vlt
@@ -1,6 +1,5 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
 // comportable IP waiver rules for verilator
-
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/BUILD b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/BUILD
index ea541965..d1f45166 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/BUILD
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/BUILD
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -35,7 +35,11 @@ py_library(
 
 py_library(
     name = "modes",
-    srcs = ["Modes.py"],
+    srcs = [
+        "Regression.py",
+        "Test.py",
+        "modes.py",
+    ],
     deps = [
         ":utils",
     ],
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/CdcCfg.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/CdcCfg.py
index 34a7956f..6b6058ca 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/CdcCfg.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/CdcCfg.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r'''
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/CfgFactory.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/CfgFactory.py
index 79e64ee5..d571ed07 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/CfgFactory.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/CfgFactory.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/CfgJson.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/CfgJson.py
index 3fee6258..717b9947 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/CfgJson.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/CfgJson.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Deploy.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Deploy.py
index 78cf8118..8f28add0 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Deploy.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Deploy.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -473,6 +473,8 @@ def __init__(self, index, test, build_job, sim_cfg):
         self.index = index
         self.build_seed = sim_cfg.build_seed
         self.seed = RunTest.get_seed()
+        # Systemverilog accepts seeds with a maximum size of 32 bits.
+        self.svseed = int(self.seed) & 0xFFFFFFFF
         self.simulated_time = JobTime()
         super().__init__(sim_cfg)
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/FlowCfg.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/FlowCfg.py
index 8cebeec9..daeae879 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/FlowCfg.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/FlowCfg.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/FormalCfg.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/FormalCfg.py
index ed061500..5be6e724 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/FormalCfg.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/FormalCfg.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -6,9 +6,9 @@
 from pathlib import Path
 
 import hjson
-from tabulate import tabulate
-
 from OneShotCfg import OneShotCfg
+from results_server import ResultsServer
+from tabulate import tabulate
 from utils import subst_wildcards
 
 
@@ -23,8 +23,10 @@ def __init__(self, flow_cfg_file, hjson_data, args, mk_config):
         self.batch_mode_prefix = "" if args.gui else "-batch"
 
         super().__init__(flow_cfg_file, hjson_data, args, mk_config)
-        self.header = ["name", "errors", "warnings", "proven", "cex", "undetermined",
-                       "covered", "unreachable", "pass_rate", "cov_rate"]
+        self.header = [
+            "name", "errors", "warnings", "proven", "cex", "undetermined",
+            "covered", "unreachable", "pass_rate", "cov_rate"
+        ]
 
         # Default not to publish child cfg results.
         if "publish_report" in hjson_data:
@@ -32,10 +34,13 @@ def __init__(self, flow_cfg_file, hjson_data, args, mk_config):
         else:
             self.publish_report = False
         self.sub_flow = hjson_data['sub_flow']
-        self.summary_header = ["name", "pass_rate", "stimuli_cov", "coi_cov", "prove_cov"]
-        self.results_title = self.name.upper() + " Formal " + self.sub_flow.upper() + " Results"
+        self.summary_header = [
+            "name", "pass_rate", "formal_cov", "stimuli_cov", "checker_cov"
+        ]
+        self.results_title = self.name.upper(
+        ) + " Formal " + self.sub_flow.upper() + " Results"
 
-    def parse_dict_to_str(self, input_dict, excl_keys = []):
+    def parse_dict_to_str(self, input_dict, excl_keys=[]):
         # This is a helper function to parse dictionary items into a string.
         # This function has an optional input "excl_keys" for user to exclude
         # printing out certain items according to their keys.
@@ -87,12 +92,13 @@ def get_summary(self, result):
                 str(formal_summary["undetermined"]) + " W ",
                 str(formal_summary["covered"]) + " G ",
                 str(formal_summary["unreachable"]) + " E ",
-                formal_summary["pass_rate"],
-                formal_summary["cov_rate"]
+                formal_summary["pass_rate"], formal_summary["cov_rate"]
             ])
             summary.append(formal_summary["pass_rate"])
             if len(table) > 1:
-                results_str = tabulate(table, headers="firstrow", tablefmt="pipe",
+                results_str = tabulate(table,
+                                       headers="firstrow",
+                                       tablefmt="pipe",
                                        colalign=colalign)
             else:
                 results_str = "No content in summary\n"
@@ -106,21 +112,22 @@ def get_coverage(self, result):
             results_str = "No coverage information found\n"
             summary = ["N/A", "N/A", "N/A"]
         else:
-            cov_header = ["stimuli", "coi", "proof"]
+            cov_header = ["formal", "stimuli", "checker"]
             cov_colalign = ("center", ) * len(cov_header)
             cov_table = [cov_header]
             cov_table.append([
-                formal_coverage["stimuli"],
-                formal_coverage["coi"],
-                formal_coverage["proof"]
+                formal_coverage["formal"], formal_coverage["stimuli"],
+                formal_coverage["checker"]
             ])
+            summary.append(formal_coverage["formal"])
             summary.append(formal_coverage["stimuli"])
-            summary.append(formal_coverage["coi"])
-            summary.append(formal_coverage["proof"])
+            summary.append(formal_coverage["checker"])
 
             if len(cov_table) > 1:
-                results_str = tabulate(cov_table, headers="firstrow",
-                                       tablefmt="pipe", colalign=cov_colalign)
+                results_str = tabulate(cov_table,
+                                       headers="firstrow",
+                                       tablefmt="pipe",
+                                       colalign=cov_colalign)
 
             else:
                 results_str = "No content in formal_coverage\n"
@@ -145,7 +152,9 @@ def gen_results_summary(self):
                 table.append(cfg.result_summary[cfg.name])
             except KeyError as e:
                 table.append([cfg.name, "ERROR", "N/A", "N/A", "N/A"])
-                log.error("cfg: %s could not find generated results_summary: %s", cfg.name, e)
+                log.error(
+                    "cfg: %s could not find generated results_summary: %s",
+                    cfg.name, e)
         if len(table) > 1:
             self.results_summary_md = results_str + tabulate(
                 table, headers="firstrow", tablefmt="pipe", colalign=colalign)
@@ -187,9 +196,9 @@ def _gen_results(self, results):
         # If coverage was enabled then results.hjson will also have an item that
         # shows formal coverage. It will have the following format:
         #   "coverage": {
+        #      formal:  "90 %",
         #      stimuli: "90 %",
-        #      coi    : "90 %",
-        #      proof  : "80 %"
+        #      checker: "80 %"
         #   }
         results_str = "## " + self.results_title + "\n\n"
         results_str += "### " + self.timestamp_long + "\n"
@@ -203,9 +212,9 @@ def _gen_results(self, results):
         mode = self.deploy[0]
 
         if results[mode] == "P":
-            result_data = Path(subst_wildcards(self.build_dir,
-                                               {"build_mode": mode.name}),
-                               'results.hjson')
+            result_data = Path(
+                subst_wildcards(self.build_dir, {"build_mode": mode.name}),
+                'results.hjson')
             try:
                 with open(result_data, "r") as results_file:
                     self.result = hjson.load(results_file, use_decimal=True)
@@ -247,7 +256,7 @@ def _gen_results(self, results):
 
         return self.results_md
 
-    def _publish_results(self):
+    def _publish_results(self, results_server: ResultsServer):
         ''' our agreement with tool vendors allows us to publish the summary
         results (as in gen_results_summary).
 
@@ -258,6 +267,6 @@ def _publish_results(self):
         '''
         if self.publish_report:
             self.publish_results_md = self.gen_results_summary()
-            super()._publish_results()
+            super()._publish_results(results_server)
         else:
             return
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/JobTime.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/JobTime.py
index 69adeba3..ba270b7d 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/JobTime.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/JobTime.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""An abstraction for maintaining job runtime and its units.
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Launcher.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Launcher.py
index ac617c78..a483e94e 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Launcher.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Launcher.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LauncherFactory.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LauncherFactory.py
index 3829187c..cac498d0 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LauncherFactory.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LauncherFactory.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LintCfg.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LintCfg.py
index 1b3cf160..ced74908 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LintCfg.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LintCfg.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r'''
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LintParser.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LintParser.py
index ff697ce6..484b2234 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LintParser.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LintParser.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""Helper class for parsing lint reports into a generic hjson format.
@@ -17,6 +17,7 @@ class LintParser():
 
     def __init__(self) -> None:
         self.buckets = {
+            'flow_info': [],
             'flow_warning': [],
             'flow_error': [],
             'lint_info': [],
@@ -27,6 +28,7 @@ def __init__(self) -> None:
             'fusesoc-error': []
         }
         self.severities = {
+            'flow_info': 'info',
             'flow_warning': 'warning',
             'flow_error': 'error',
             'lint_info': 'info',
@@ -35,14 +37,28 @@ def __init__(self) -> None:
         }
 
     def extract_messages(self, log_content: str, patterns: List[str]) -> None:
-        """
-        This extracts messages from the string buffer log_content.
+        """Extract messages from the string buffer log_content.
+
         The argument patterns needs to be a list of tuples with
         (<error_severity>, <pattern_to_match_for>).
+
+        A substring that matches two different patterns will be stored in the
+        bucket associated with the first pattern that matches.
         """
-        for bucket, pattern in patterns:
-            self.buckets[bucket] += \
-                re.findall(pattern, log_content, flags=re.MULTILINE)
+        # Iterate through all the patterns in reverse order and store hits
+        # against the index of their first character. Doing this in reverse
+        # order means that patterns earlier in the list "win": if two different
+        # patterns match a particular substring, only the bucket of the first
+        # one will end up in the found dict.
+        found = {}
+        for bucket, pattern in reversed(patterns):
+            for m in re.finditer(pattern, log_content, flags=re.MULTILINE):
+                found[m.start()] = (bucket, m.group(0))
+
+        # Now that we've ignored duplicate hits, flatten things out into
+        # self.buckets.
+        for bucket, hit in found.values():
+            self.buckets[bucket].append(hit)
 
     def get_results(self, args: Dict[Path, List[Tuple]]) -> Dict[str, int]:
         """
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LocalLauncher.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LocalLauncher.py
index 2e466f66..670cc5ba 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LocalLauncher.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LocalLauncher.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,9 +15,6 @@ class LocalLauncher(Launcher):
     Implementation of Launcher to launch jobs in the user's local workstation.
     """
 
-    # Misc common LocalLauncher settings.
-    max_odirs = 5
-
     def __init__(self, deploy):
         '''Initialize common class members.'''
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LsfLauncher.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LsfLauncher.py
index 4c623433..2260a017 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LsfLauncher.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/LsfLauncher.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Makefile b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Makefile
index f0ab3777..5585d628 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Makefile
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Makefile
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Modes.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Modes.py
deleted file mode 100644
index 37d6a16d..00000000
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Modes.py
+++ /dev/null
@@ -1,636 +0,0 @@
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-
-import logging as log
-import pprint
-import sys
-
-from utils import VERBOSE
-
-
-class Modes():
-    """
-    Abstraction for specifying collection of options called as 'modes'. This is
-    the base class which is extended for run_modes, build_modes, tests and regressions.
-    """
-
-    def self_str(self):
-        '''
-        This is used to construct the string representation of the entire class object.
-        '''
-        tname = ""
-        if self.type != "":
-            tname = self.type + "_"
-        if self.mname != "":
-            tname += self.mname
-        if log.getLogger().isEnabledFor(VERBOSE):
-            return "\n<---" + tname + ":\n" + pprint.pformat(self.__dict__) + \
-                   "\n--->\n"
-        else:
-            return tname + ":" + self.name
-
-    def __str__(self):
-        return self.self_str()
-
-    def __repr__(self):
-        return self.self_str()
-
-    def __init__(self, mdict):
-        keys = mdict.keys()
-        attrs = self.__dict__.keys()
-
-        if 'name' not in keys:
-            log.error("Key \"name\" missing in mode %s", mdict)
-            sys.exit(1)
-
-        if not hasattr(self, "type"):
-            log.fatal("Key \"type\" is missing or invalid")
-            sys.exit(1)
-
-        if not hasattr(self, "mname"):
-            self.mname = ""
-
-        for key in keys:
-            if key not in attrs:
-                log.error(f"Key {key} in {mdict} is invalid. Supported "
-                          f"attributes in {self.mname} are {attrs}")
-                sys.exit(1)
-            setattr(self, key, mdict[key])
-
-    def get_sub_modes(self):
-        sub_modes = []
-        if hasattr(self, "en_" + self.type + "_modes"):
-            sub_modes = getattr(self, "en_" + self.type + "_modes")
-        return sub_modes
-
-    def set_sub_modes(self, sub_modes):
-        setattr(self, "en_" + self.type + "_modes", sub_modes)
-
-    def merge_mode(self, mode):
-        '''
-        Merge a new mode with self.
-        Merge sub mode specified with 'en_*_modes with self.
-        '''
-
-        sub_modes = self.get_sub_modes()
-        is_sub_mode = mode.name in sub_modes
-
-        if not mode.name == self.name and not is_sub_mode:
-            return False
-
-        # Merge attributes in self with attributes in mode arg, since they are
-        # the same mode but set in separate files, or a sub-mode.
-        for attr, self_attr_val in self.__dict__.items():
-            mode_attr_val = getattr(mode, attr, None)
-
-            # If sub-mode, skip the name fields - they could differ.
-            if is_sub_mode and attr in ['name', 'mname']:
-                continue
-
-            # If mode's value is None, then nothing to do here.
-            if mode_attr_val is None:
-                continue
-
-            # If self value is None, then replace with mode's value.
-            if self_attr_val is None:
-                setattr(self, attr, mode_attr_val)
-                continue
-
-            # If they are equal, then nothing to do here.
-            if self_attr_val == mode_attr_val:
-                continue
-
-            # Extend if they are both lists.
-            if isinstance(self_attr_val, list):
-                assert isinstance(mode_attr_val, list)
-                self_attr_val.extend(mode_attr_val)
-                continue
-
-            # If the current val is default, replace with new.
-            scalar_types = {str: "", int: -1}
-            default_val = scalar_types.get(type(self_attr_val))
-
-            if type(self_attr_val) in scalar_types.keys(
-            ) and self_attr_val == default_val:
-                setattr(self, attr, mode_attr_val)
-                continue
-
-            # Check if their types are compatible.
-            if type(self_attr_val) != type(mode_attr_val):
-                log.error(
-                    "Mode %s cannot be merged into %s due to a conflict "
-                    "(type mismatch): %s: {%s(%s), %s(%s)}", mode.name,
-                    self.name, attr, str(self_attr_val),
-                    str(type(self_attr_val)), str(mode_attr_val),
-                    str(type(mode_attr_val)))
-                sys.exit(1)
-
-            # Check if they are different non-default values.
-            if self_attr_val != default_val and mode_attr_val != default_val:
-                log.error(
-                    "Mode %s cannot be merged into %s due to a conflict "
-                    "(unable to pick one from different values): "
-                    "%s: {%s, %s}", mode.name, self.name, attr,
-                    str(self_attr_val), str(mode_attr_val))
-                sys.exit(1)
-
-        # Check newly appended sub_modes, remove 'self' and duplicates
-        sub_modes = self.get_sub_modes()
-
-        if sub_modes != []:
-            new_sub_modes = []
-            for sub_mode in sub_modes:
-                if self.name != sub_mode and sub_mode not in new_sub_modes:
-                    new_sub_modes.append(sub_mode)
-            self.set_sub_modes(new_sub_modes)
-        return True
-
-    @staticmethod
-    def create_modes(ModeType, mdicts):
-        '''
-        Create modes of type ModeType from a given list of raw dicts
-        Process dependencies.
-        Return a list of modes objects.
-        '''
-
-        def merge_sub_modes(mode, parent, objs):
-            # Check if there are modes available to merge
-            sub_modes = mode.get_sub_modes()
-            if sub_modes == []:
-                return
-
-            # Set parent if it is None. If not, check cyclic dependency
-            if parent is None:
-                parent = mode
-            else:
-                if mode.name == parent.name:
-                    log.error("Cyclic dependency when processing mode \"%s\"",
-                              mode.name)
-                    sys.exit(1)
-
-            for sub_mode in sub_modes:
-                # Find the sub_mode obj from str
-                found = False
-                for obj in objs:
-                    if sub_mode == obj.name:
-                        # First recursively merge the sub_modes
-                        merge_sub_modes(obj, parent, objs)
-
-                        # Now merge the sub mode with mode
-                        mode.merge_mode(obj)
-                        found = True
-                        break
-                if not found:
-                    log.error(
-                        "Sub mode \"%s\" added to mode \"%s\" was not found!",
-                        sub_mode, mode.name)
-                    sys.exit(1)
-
-        modes_objs = []
-        # create a default mode if available
-        default_mode = ModeType.get_default_mode()
-        if default_mode is not None:
-            modes_objs.append(default_mode)
-
-        # Process list of raw dicts that represent the modes
-        # Pass 1: Create unique set of modes by merging modes with the same name
-        for mdict in mdicts:
-            # Create a new item
-            new_mode_merged = False
-            new_mode = ModeType(mdict)
-            for mode in modes_objs:
-                # Merge new one with existing if available
-                if mode.name == new_mode.name:
-                    mode.merge_mode(new_mode)
-                    new_mode_merged = True
-                    break
-
-            # Add the new mode to the list if not already appended
-            if not new_mode_merged:
-                modes_objs.append(new_mode)
-                ModeType.item_names.append(new_mode.name)
-
-        # Pass 2: Recursively expand sub modes within parent modes
-        for mode in modes_objs:
-            merge_sub_modes(mode, None, modes_objs)
-
-        # Return the list of objects
-        return modes_objs
-
-    @staticmethod
-    def get_default_mode(ModeType):
-        return None
-
-    @staticmethod
-    def find_mode(mode_name, modes):
-        '''
-        Given a mode_name in string, go through list of modes and return the mode with
-        the string that matches. Thrown an error and return None if nothing was found.
-        '''
-        for mode in modes:
-            if mode_name == mode.name:
-                return mode
-        return None
-
-    @staticmethod
-    def find_and_merge_modes(mode, mode_names, modes, merge_modes=True):
-        '''
-        '''
-        found_mode_objs = []
-        for mode_name in mode_names:
-            sub_mode = Modes.find_mode(mode_name, modes)
-            if sub_mode is not None:
-                found_mode_objs.append(sub_mode)
-                if merge_modes is True:
-                    mode.merge_mode(sub_mode)
-            else:
-                log.error("Mode \"%s\" enabled within mode \"%s\" not found!",
-                          mode_name, mode.name)
-                sys.exit(1)
-        return found_mode_objs
-
-
-class BuildModes(Modes):
-    """
-    Build modes.
-    """
-
-    # Maintain a list of build_modes str
-    item_names = []
-
-    def __init__(self, bdict):
-        self.name = ""
-        self.type = "build"
-        if not hasattr(self, "mname"):
-            self.mname = "mode"
-        self.is_sim_mode = 0
-        self.pre_build_cmds = []
-        self.post_build_cmds = []
-        self.en_build_modes = []
-        self.build_opts = []
-        self.build_timeout_mins = None
-        self.pre_run_cmds = []
-        self.post_run_cmds = []
-        self.run_opts = []
-        self.sw_images = []
-        self.sw_build_opts = []
-
-        super().__init__(bdict)
-        self.en_build_modes = list(set(self.en_build_modes))
-
-    @staticmethod
-    def get_default_mode():
-        return BuildModes({"name": "default"})
-
-
-class RunModes(Modes):
-    """
-    Run modes.
-    """
-
-    # Maintain a list of run_modes str
-    item_names = []
-
-    def __init__(self, rdict):
-        self.name = ""
-        self.type = "run"
-        if not hasattr(self, "mname"):
-            self.mname = "mode"
-        self.reseed = None
-        self.pre_run_cmds = []
-        self.post_run_cmds = []
-        self.en_run_modes = []
-        self.run_opts = []
-        self.uvm_test = ""
-        self.uvm_test_seq = ""
-        self.build_mode = ""
-        self.run_timeout_mins = None
-        self.run_timeout_multiplier = None
-        self.sw_images = []
-        self.sw_build_device = ""
-        self.sw_build_opts = []
-
-        super().__init__(rdict)
-        self.en_run_modes = list(set(self.en_run_modes))
-
-    @staticmethod
-    def get_default_mode():
-        return None
-
-
-class Tests(RunModes):
-    """
-    Abstraction for tests. The RunModes abstraction can be reused here with a few
-    modifications.
-    """
-
-    # Maintain a list of tests str
-    item_names = []
-
-    # TODO: This info should be passed via hjson
-    defaults = {
-        "reseed": None,
-        "uvm_test": "",
-        "uvm_test_seq": "",
-        "build_mode": "",
-        "sw_images": [],
-        "sw_build_device": "",
-        "sw_build_opts": [],
-        "run_timeout_mins": None,
-        "run_timeout_multiplier": None
-    }
-
-    def __init__(self, tdict):
-        if not hasattr(self, "mname"):
-            self.mname = "test"
-        super().__init__(tdict)
-
-    @staticmethod
-    def create_tests(tdicts, sim_cfg):
-        '''
-        Create Tests from a given list of raw dicts.
-        TODO: enhance the raw dict to include file scoped defaults.
-        Process enabled run modes and the set build mode.
-        Return a list of test objects.
-        '''
-
-        def get_pruned_en_run_modes(test_en_run_modes, global_en_run_modes):
-            pruned_en_run_modes = []
-            for test_en_run_mode in test_en_run_modes:
-                if test_en_run_mode not in global_en_run_modes:
-                    pruned_en_run_modes.append(test_en_run_mode)
-            return pruned_en_run_modes
-
-        tests_objs = []
-        # Pass 1: Create unique set of tests by merging tests with the same name
-        for tdict in tdicts:
-            # Create a new item
-            new_test_merged = False
-            new_test = Tests(tdict)
-            for test in tests_objs:
-                # Merge new one with existing if available
-                if test.name == new_test.name:
-                    test.merge_mode(new_test)
-                    new_test_merged = True
-                    break
-
-            # Add the new test to the list if not already appended
-            if not new_test_merged:
-                tests_objs.append(new_test)
-                Tests.item_names.append(new_test.name)
-
-        # Pass 2: Process dependencies
-        build_modes = []
-        if hasattr(sim_cfg, "build_modes"):
-            build_modes = getattr(sim_cfg, "build_modes")
-
-        run_modes = []
-        if hasattr(sim_cfg, "run_modes"):
-            run_modes = getattr(sim_cfg, "run_modes")
-
-        attrs = Tests.defaults
-        for test_obj in tests_objs:
-            # Unpack run_modes first
-            en_run_modes = get_pruned_en_run_modes(test_obj.en_run_modes,
-                                                   sim_cfg.en_run_modes)
-            Modes.find_and_merge_modes(test_obj, en_run_modes, run_modes)
-
-            # Find and set the missing attributes from sim_cfg
-            # If not found in sim_cfg either, then throw a warning
-            # TODO: These should be file-scoped
-            for attr in attrs.keys():
-                # Check if attr value is default
-                val = getattr(test_obj, attr)
-                default_val = attrs[attr]
-                if val == default_val:
-                    global_val = None
-                    # Check if we can find a default in sim_cfg
-                    if hasattr(sim_cfg, attr):
-                        global_val = getattr(sim_cfg, attr)
-
-                    if global_val is not None and global_val != default_val:
-                        setattr(test_obj, attr, global_val)
-
-            # Unpack the build mode for this test
-            build_mode_objs = Modes.find_and_merge_modes(test_obj,
-                                                         [test_obj.build_mode],
-                                                         build_modes,
-                                                         merge_modes=False)
-            test_obj.build_mode = build_mode_objs[0]
-
-            # Error if set build mode is actually a sim mode
-            if test_obj.build_mode.is_sim_mode is True:
-                log.error(
-                    "Test \"%s\" uses build_mode %s which is actually a sim mode",
-                    test_obj.name, test_obj.build_mode.name)
-                sys.exit(1)
-
-            # Merge build_mode's params with self
-            test_obj.pre_run_cmds.extend(test_obj.build_mode.pre_run_cmds)
-            test_obj.post_run_cmds.extend(test_obj.build_mode.post_run_cmds)
-            test_obj.run_opts.extend(test_obj.build_mode.run_opts)
-            test_obj.sw_images.extend(test_obj.build_mode.sw_images)
-            test_obj.sw_build_opts.extend(test_obj.build_mode.sw_build_opts)
-
-        # Return the list of tests
-        return tests_objs
-
-    @staticmethod
-    def merge_global_opts(tests, global_pre_build_cmds, global_post_build_cmds,
-                          global_build_opts, global_pre_run_cmds,
-                          global_post_run_cmds, global_run_opts,
-                          global_sw_images, global_sw_build_opts):
-        processed_build_modes = set()
-        for test in tests:
-            if test.build_mode.name not in processed_build_modes:
-                test.build_mode.pre_build_cmds.extend(global_pre_build_cmds)
-                test.build_mode.post_build_cmds.extend(global_post_build_cmds)
-                test.build_mode.build_opts.extend(global_build_opts)
-                processed_build_modes.add(test.build_mode.name)
-            test.pre_run_cmds.extend(global_pre_run_cmds)
-            test.post_run_cmds.extend(global_post_run_cmds)
-            test.run_opts.extend(global_run_opts)
-            test.sw_images.extend(global_sw_images)
-            test.sw_build_opts.extend(global_sw_build_opts)
-
-
-class Regressions(Modes):
-    """
-    Abstraction for test sets / regression sets.
-    """
-
-    # Maintain a list of tests str
-    item_names = []
-
-    # TODO: define __repr__ and __str__ to print list of tests if VERBOSE
-
-    def __init__(self, regdict):
-        self.name = ""
-        self.type = ""
-        if not hasattr(self, "mname"):
-            self.mname = "regression"
-
-        # The `tests` member is typically a list, but it defaults to None.
-        # There are 3 possible cases after all the HJson files are parsed, when
-        # this particular regression is supplied to be run:
-        #
-        # 1. `tests` == None:   This is treated as "run ALL available tests".
-        # 2. `tests` == []:     No available tests to run
-        # 3. `len(tests)` > 0:  The provided set of tests are run.
-        self.tests = None
-        self.test_names = []
-
-        self.reseed = None
-        self.excl_tests = []  # TODO: add support for this
-        self.en_sim_modes = []
-        self.en_run_modes = []
-        self.pre_build_cmds = []
-        self.post_build_cmds = []
-        self.pre_run_cmds = []
-        self.post_run_cmds = []
-        self.build_opts = []
-        self.run_opts = []
-        super().__init__(regdict)
-
-    @staticmethod
-    def create_regressions(regdicts, sim_cfg, tests):
-        '''
-        Create Test sets from a given list of raw dicts.
-        Return a list of test set objects.
-        '''
-
-        regressions_objs = []
-        # Pass 1: Create unique set of test sets by merging test sets with the same name
-        for regdict in regdicts:
-            # Create a new item
-            new_regression_merged = False
-            new_regression = Regressions(regdict)
-
-            # Check for name conflicts with tests before merging
-            if new_regression.name in Tests.item_names:
-                log.error(
-                    "Test names and regression names are required to be unique. "
-                    "The regression \"%s\" bears the same name with an existing test. ",
-                    new_regression.name)
-                sys.exit(1)
-
-            for regression in regressions_objs:
-                # Merge new one with existing if available
-                if regression.name == new_regression.name:
-                    regression.merge_mode(new_regression)
-                    new_regression_merged = True
-                    break
-
-            # Add the new test to the list if not already appended
-            if not new_regression_merged:
-                regressions_objs.append(new_regression)
-                Regressions.item_names.append(new_regression.name)
-
-        # Pass 2: Process dependencies
-        build_modes = []
-        if hasattr(sim_cfg, "build_modes"):
-            build_modes = getattr(sim_cfg, "build_modes")
-
-        run_modes = []
-        if hasattr(sim_cfg, "run_modes"):
-            run_modes = getattr(sim_cfg, "run_modes")
-
-        for regression_obj in regressions_objs:
-            # Unpack the sim modes
-            found_sim_mode_objs = Modes.find_and_merge_modes(
-                regression_obj, regression_obj.en_sim_modes, build_modes,
-                False)
-
-            for sim_mode_obj in found_sim_mode_objs:
-                if sim_mode_obj.is_sim_mode == 0:
-                    log.error(
-                        "Enabled mode \"%s\" within the regression \"%s\" is not a sim mode",
-                        sim_mode_obj.name, regression_obj.name)
-                    sys.exit(1)
-
-                # Check if sim_mode_obj's sub-modes are a part of regressions's
-                # sim modes- if yes, then it will cause duplication of cmds &
-                # opts. Throw an error and exit.
-                for sim_mode_obj_sub in sim_mode_obj.en_build_modes:
-                    if sim_mode_obj_sub in regression_obj.en_sim_modes:
-                        log.error(
-                            "Regression \"%s\" enables sim_modes \"%s\" and \"%s\". "
-                            "The former is already a sub_mode of the latter.",
-                            regression_obj.name, sim_mode_obj_sub,
-                            sim_mode_obj.name)
-                        sys.exit(1)
-
-                # Check if sim_mode_obj is also passed on the command line, in
-                # which case, skip
-                if sim_mode_obj.name in sim_cfg.en_build_modes:
-                    continue
-
-                # Merge the build and run cmds & opts from the sim modes
-                regression_obj.pre_build_cmds.extend(
-                    sim_mode_obj.pre_build_cmds)
-                regression_obj.post_build_cmds.extend(
-                    sim_mode_obj.post_build_cmds)
-                regression_obj.build_opts.extend(sim_mode_obj.build_opts)
-                regression_obj.pre_run_cmds.extend(sim_mode_obj.pre_run_cmds)
-                regression_obj.post_run_cmds.extend(sim_mode_obj.post_run_cmds)
-                regression_obj.run_opts.extend(sim_mode_obj.run_opts)
-
-            # Unpack the run_modes
-            # TODO: If there are other params other than run_opts throw an
-            # error and exit
-            found_run_mode_objs = Modes.find_and_merge_modes(
-                regression_obj, regression_obj.en_run_modes, run_modes, False)
-
-            # Only merge the pre_run_cmds, post_run_cmds & run_opts from the
-            # run_modes enabled
-            for run_mode_obj in found_run_mode_objs:
-                # Check if run_mode_obj is also passed on the command line, in
-                # which case, skip
-                if run_mode_obj.name in sim_cfg.en_run_modes:
-                    continue
-                regression_obj.pre_run_cmds.extend(run_mode_obj.pre_run_cmds)
-                regression_obj.post_run_cmds.extend(run_mode_obj.post_run_cmds)
-                regression_obj.run_opts.extend(run_mode_obj.run_opts)
-
-            # Unpack tests
-            # If `tests` member resolves to None, then we add ALL available
-            # tests for running the regression.
-            if regression_obj.tests is None:
-                log.log(VERBOSE,
-                        "Unpacking all tests in scope for regression \"%s\"",
-                        regression_obj.name)
-                regression_obj.tests = sim_cfg.tests
-                regression_obj.test_names = Tests.item_names
-
-            else:
-                tests_objs = set()
-                regression_obj.test_names = regression_obj.tests
-                for test in regression_obj.tests:
-                    test_obj = Modes.find_mode(test, sim_cfg.tests)
-                    if test_obj is None:
-                        log.error(
-                            "Test \"%s\" added to regression \"%s\" not found!",
-                            test, regression_obj.name)
-                        continue
-                    tests_objs.add(test_obj)
-                regression_obj.tests = list(tests_objs)
-
-        # Return the list of tests
-        return regressions_objs
-
-    def merge_regression_opts(self):
-        processed_build_modes = []
-        for test in self.tests:
-            if test.build_mode.name not in processed_build_modes:
-                test.build_mode.pre_build_cmds.extend(self.pre_build_cmds)
-                test.build_mode.post_build_cmds.extend(self.post_build_cmds)
-                test.build_mode.build_opts.extend(self.build_opts)
-                processed_build_modes.append(test.build_mode.name)
-            test.pre_run_cmds.extend(self.pre_run_cmds)
-            test.post_run_cmds.extend(self.post_run_cmds)
-            test.run_opts.extend(self.run_opts)
-
-            # Override reseed if available.
-            if self.reseed is not None:
-                test.reseed = self.reseed
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/MsgBucket.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/MsgBucket.py
index b6799e6c..84f60d01 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/MsgBucket.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/MsgBucket.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r'''
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/MsgBuckets.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/MsgBuckets.py
index e5f82952..0bbbf861 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/MsgBuckets.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/MsgBuckets.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r'''
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/OneShotCfg.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/OneShotCfg.py
index 574795d7..c23adebd 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/OneShotCfg.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/OneShotCfg.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""
@@ -11,7 +11,7 @@
 
 from Deploy import CompileOneShot
 from FlowCfg import FlowCfg
-from Modes import BuildModes, Modes
+from modes import BuildMode, Mode
 from utils import rm_path
 
 
@@ -116,8 +116,8 @@ def _purge(self):
 
     def _create_objects(self):
         # Create build and run modes objects
-        build_modes = Modes.create_modes(BuildModes,
-                                         getattr(self, "build_modes"))
+        build_modes = Mode.create_modes(BuildMode,
+                                        getattr(self, "build_modes"))
         setattr(self, "build_modes", build_modes)
 
         # All defined build modes are being built, h
@@ -146,11 +146,9 @@ def _create_deploy_objects(self):
         '''Create deploy objects from build modes
         '''
         builds = []
-        build_map = {}
         for build in self.build_modes:
             item = CompileOneShot(build, self)
             builds.append(item)
-            build_map[build] = item
 
         self.builds = builds
         self.deploy = builds
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/RdcCfg.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/RdcCfg.py
index 60f57a2e..e4b753c2 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/RdcCfg.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/RdcCfg.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r'''
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Regression.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Regression.py
new file mode 100644
index 00000000..652f965f
--- /dev/null
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Regression.py
@@ -0,0 +1,182 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+from modes import Mode, find_mode, find_and_merge_modes
+from Test import Test
+
+import logging as log
+import sys
+from utils import VERBOSE
+
+
+class Regression(Mode):
+    """
+    Abstraction for test sets / regression sets.
+    """
+
+    # Maintain a list of tests str
+    item_names = []
+
+    def __init__(self, regdict):
+        self.name = ""
+        self.type = ""
+
+        # The `tests` member is typically a list, but it defaults to None.
+        # There are 3 possible cases after all the HJson files are parsed, when
+        # this particular regression is supplied to be run:
+        #
+        # 1. `tests` == None:   This is treated as "run ALL available tests".
+        # 2. `tests` == []:     No available tests to run
+        # 3. `len(tests)` > 0:  The provided set of tests are run.
+        self.tests = None
+        self.test_names = []
+
+        self.reseed = None
+        self.excl_tests = []  # TODO: add support for this
+        self.en_sim_modes = []
+        self.en_run_modes = []
+        self.pre_build_cmds = []
+        self.post_build_cmds = []
+        self.pre_run_cmds = []
+        self.post_run_cmds = []
+        self.build_opts = []
+        self.run_opts = []
+        super().__init__("regression", regdict)
+
+    @staticmethod
+    def create_regressions(regdicts, sim_cfg, tests):
+        '''
+        Create Test sets from a given list of raw dicts.
+        Return a list of test set objects.
+        '''
+
+        regression_objs = []
+        # Pass 1: Create unique set of test sets by merging test sets with the same name
+        for regdict in regdicts:
+            # Create a new item
+            new_regression_merged = False
+            new_regression = Regression(regdict)
+
+            # Check for name conflicts with tests before merging
+            if new_regression.name in Test.item_names:
+                log.error(
+                    "Test names and regression names are required to be unique. "
+                    "The regression \"%s\" bears the same name with an existing test. ",
+                    new_regression.name)
+                sys.exit(1)
+
+            for regression in regression_objs:
+                # Merge new one with existing if available
+                if regression.name == new_regression.name:
+                    regression.merge_mode(new_regression)
+                    new_regression_merged = True
+                    break
+
+            # Add the new test to the list if not already appended
+            if not new_regression_merged:
+                regression_objs.append(new_regression)
+                Regression.item_names.append(new_regression.name)
+
+        # Pass 2: Process dependencies
+        build_modes = getattr(sim_cfg, "build_modes", [])
+        run_modes = getattr(sim_cfg, "run_modes", [])
+
+        for regression_obj in regression_objs:
+            # Unpack the sim modes
+            found_sim_mode_objs = find_and_merge_modes(
+                regression_obj, regression_obj.en_sim_modes, build_modes,
+                False)
+
+            for sim_mode_obj in found_sim_mode_objs:
+                if sim_mode_obj.is_sim_mode == 0:
+                    log.error(
+                        "Enabled mode \"%s\" within the regression \"%s\" is not a sim mode",
+                        sim_mode_obj.name, regression_obj.name)
+                    sys.exit(1)
+
+                # Check if sim_mode_obj's sub-modes are a part of regressions's
+                # sim modes- if yes, then it will cause duplication of cmds &
+                # opts. Throw an error and exit.
+                for sim_mode_obj_sub in sim_mode_obj.en_build_modes:
+                    if sim_mode_obj_sub in regression_obj.en_sim_modes:
+                        log.error(
+                            "Regression \"%s\" enables sim_modes \"%s\" and \"%s\". "
+                            "The former is already a sub_mode of the latter.",
+                            regression_obj.name, sim_mode_obj_sub,
+                            sim_mode_obj.name)
+                        sys.exit(1)
+
+                # Check if sim_mode_obj is also passed on the command line, in
+                # which case, skip
+                if sim_mode_obj.name in sim_cfg.en_build_modes:
+                    continue
+
+                # Merge the build and run cmds & opts from the sim modes
+                regression_obj.pre_build_cmds.extend(
+                    sim_mode_obj.pre_build_cmds)
+                regression_obj.post_build_cmds.extend(
+                    sim_mode_obj.post_build_cmds)
+                regression_obj.build_opts.extend(sim_mode_obj.build_opts)
+                regression_obj.pre_run_cmds.extend(sim_mode_obj.pre_run_cmds)
+                regression_obj.post_run_cmds.extend(sim_mode_obj.post_run_cmds)
+                regression_obj.run_opts.extend(sim_mode_obj.run_opts)
+
+            # Unpack the run_modes
+            # TODO: If there are other params other than run_opts throw an
+            # error and exit
+            found_run_mode_objs = find_and_merge_modes(
+                regression_obj, regression_obj.en_run_modes, run_modes, False)
+
+            # Only merge the pre_run_cmds, post_run_cmds & run_opts from the
+            # run_modes enabled
+            for run_mode_obj in found_run_mode_objs:
+                # Check if run_mode_obj is also passed on the command line, in
+                # which case, skip
+                if run_mode_obj.name in sim_cfg.en_run_modes:
+                    continue
+                regression_obj.pre_run_cmds.extend(run_mode_obj.pre_run_cmds)
+                regression_obj.post_run_cmds.extend(run_mode_obj.post_run_cmds)
+                regression_obj.run_opts.extend(run_mode_obj.run_opts)
+
+            # Unpack tests
+            # If `tests` member resolves to None, then we add ALL available
+            # tests for running the regression.
+            if regression_obj.tests is None:
+                log.log(VERBOSE,
+                        "Unpacking all tests in scope for regression \"%s\"",
+                        regression_obj.name)
+                regression_obj.tests = sim_cfg.tests
+                regression_obj.test_names = Test.item_names
+
+            else:
+                tests_objs = set()
+                regression_obj.test_names = regression_obj.tests
+                for test in regression_obj.tests:
+                    test_obj = find_mode(test, sim_cfg.tests)
+                    if test_obj is None:
+                        log.error(
+                            "Test \"%s\" added to regression \"%s\" not found!",
+                            test, regression_obj.name)
+                        continue
+                    tests_objs.add(test_obj)
+                regression_obj.tests = list(tests_objs)
+
+        # Return the list of tests
+        return regression_objs
+
+    def merge_regression_opts(self):
+        processed_build_modes = []
+        for test in self.tests:
+            if test.build_mode.name not in processed_build_modes:
+                test.build_mode.pre_build_cmds.extend(self.pre_build_cmds)
+                test.build_mode.post_build_cmds.extend(self.post_build_cmds)
+                test.build_mode.build_opts.extend(self.build_opts)
+                processed_build_modes.append(test.build_mode.name)
+            test.pre_run_cmds.extend(self.pre_run_cmds)
+            test.post_run_cmds.extend(self.post_run_cmds)
+            test.run_opts.extend(self.run_opts)
+
+            # Override reseed if available.
+            if self.reseed is not None:
+                test.reseed = self.reseed
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SGE.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SGE.py
index 2086b78e..15f8ba42 100755
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SGE.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SGE.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 # ----------------------------------
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Scheduler.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Scheduler.py
index 9249c435..2f767ad7 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Scheduler.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Scheduler.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SgeLauncher.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SgeLauncher.py
index a5d869af..c998b30a 100755
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SgeLauncher.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SgeLauncher.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 # ------------------------------------
@@ -23,9 +23,6 @@ class SgeLauncher(Launcher):
     Implementation of Launcher to launch jobs in the user's local workstation.
     """
 
-    # Misc common SgeLauncher settings.
-    max_odirs = 5
-
     def __init__(self, deploy):
         '''Initialize common class members.'''
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SimCfg.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SimCfg.py
index 31bd3a3c..83a2c25e 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SimCfg.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SimCfg.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""
@@ -19,10 +19,12 @@
 
 from Deploy import CompileSim, CovAnalyze, CovMerge, CovReport, CovUnr, RunTest
 from FlowCfg import FlowCfg
-from Modes import BuildModes, Modes, Regressions, RunModes, Tests
+from modes import BuildMode, Mode, RunMode, find_mode
+from Regression import Regression
 from results_server import ResultsServer
 from SimResults import SimResults
 from tabulate import tabulate
+from Test import Test
 from Testplan import Testplan
 from utils import TS_FORMAT, rm_path
 
@@ -42,7 +44,7 @@ class SimCfg(FlowCfg):
 
     # TODO: Find a way to set these in sim cfg instead
     ignored_wildcards = [
-        "build_mode", "index", "test", "seed", "uvm_test", "uvm_test_seq",
+        "build_mode", "index", "test", "seed", "svseed", "uvm_test", "uvm_test_seq",
         "cov_db_dirs", "sw_images", "sw_build_device", "sw_build_cmd",
         "sw_build_opts"
     ]
@@ -242,12 +244,12 @@ def _purge(self):
 
     def _create_objects(self):
         # Create build and run modes objects
-        self.build_modes = Modes.create_modes(BuildModes, self.build_modes)
-        self.run_modes = Modes.create_modes(RunModes, self.run_modes)
+        self.build_modes = Mode.create_modes(BuildMode, self.build_modes)
+        self.run_modes = Mode.create_modes(RunMode, self.run_modes)
 
         # Walk through build modes enabled on the CLI and append the opts
         for en_build_mode in self.en_build_modes:
-            build_mode_obj = Modes.find_mode(en_build_mode, self.build_modes)
+            build_mode_obj = find_mode(en_build_mode, self.build_modes)
             if build_mode_obj is not None:
                 self.pre_build_cmds.extend(build_mode_obj.pre_build_cmds)
                 self.post_build_cmds.extend(build_mode_obj.post_build_cmds)
@@ -265,7 +267,7 @@ def _create_objects(self):
 
         # Walk through run modes enabled on the CLI and append the opts
         for en_run_mode in self.en_run_modes:
-            run_mode_obj = Modes.find_mode(en_run_mode, self.run_modes)
+            run_mode_obj = find_mode(en_run_mode, self.run_modes)
             if run_mode_obj is not None:
                 self.pre_run_cmds.extend(run_mode_obj.pre_run_cmds)
                 self.post_run_cmds.extend(run_mode_obj.post_run_cmds)
@@ -279,7 +281,7 @@ def _create_objects(self):
                 sys.exit(1)
 
         # Create tests from given list of items
-        self.tests = Tests.create_tests(self.tests, self)
+        self.tests = Test.create_tests(self.tests, self)
 
         # Regressions
         # Parse testplan if provided.
@@ -293,18 +295,28 @@ def _create_objects(self):
             self.testplan = Testplan(None, name=self.name)
 
         # Create regressions
-        self.regressions = Regressions.create_regressions(
+        self.regressions = Regression.create_regressions(
             self.regressions, self, self.tests)
 
     def _print_list(self):
         for list_item in self.list_items:
             log.info("---- List of %s in %s ----", list_item, self.variant_name)
-            if hasattr(self, list_item):
-                items = getattr(self, list_item)
-                for item in items:
-                    log.info(item)
-            else:
-                log.error("Item %s does not exist!", list_item)
+            items = getattr(self, list_item, None)
+            if items is None:
+                log.error("No %s defined for %s.", list_item, self.variant_name)
+
+            for item in items:
+                # Convert the item into something that can be printed in the
+                # list. Some modes are specified as strings themselves (so
+                # there's no conversion needed). Others should be subclasses of
+                # Mode, which has a name field that we can use.
+                if isinstance(item, str):
+                    mode_name = item
+                else:
+                    assert isinstance(item, Mode)
+                    mode_name = item.name
+
+                log.info(mode_name)
 
     def _create_build_and_run_list(self):
         '''Generates a list of deployable objects from the provided items.
@@ -359,11 +371,11 @@ def _match_items(items: list, patterns: list):
                         f"tests in {self.flow_cfg_file}.")
 
         # Merge the global build and run opts
-        Tests.merge_global_opts(self.run_list, self.pre_build_cmds,
-                                self.post_build_cmds, self.build_opts,
-                                self.pre_run_cmds, self.post_run_cmds,
-                                self.run_opts, self.sw_images,
-                                self.sw_build_opts)
+        Test.merge_global_opts(self.run_list, self.pre_build_cmds,
+                               self.post_build_cmds, self.build_opts,
+                               self.pre_run_cmds, self.post_run_cmds,
+                               self.run_opts, self.sw_images,
+                               self.sw_build_opts)
 
         # Process reseed override and create the build_list
         build_list_names = []
@@ -466,7 +478,7 @@ def _create_deploy_objects(self):
         # Update all tests to use the updated (uniquified) build modes.
         for test in self.run_list:
             if test.build_mode.name != build_map[test.build_mode].name:
-                test.build_mode = Modes.find_mode(
+                test.build_mode = find_mode(
                     build_map[test.build_mode].name, self.build_modes)
 
         self.runs = ([]
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SimResults.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SimResults.py
index 0a035def..75a20314 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SimResults.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SimResults.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/StatusPrinter.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/StatusPrinter.py
index e9bf7f96..73d18edf 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/StatusPrinter.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/StatusPrinter.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SynCfg.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SynCfg.py
index f8b38548..a81e32d0 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SynCfg.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/SynCfg.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Test.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Test.py
new file mode 100644
index 00000000..3c80524b
--- /dev/null
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Test.py
@@ -0,0 +1,138 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+from copy import deepcopy
+import logging as log
+import sys
+
+from modes import RunMode, find_and_merge_modes
+
+
+class Test(RunMode):
+    """
+    Abstraction for a test. The RunMode abstraction can be reused here with a few
+    modifications.
+    """
+
+    # Maintain a list of tests str
+    item_names = []
+
+    # TODO: This info should be passed via hjson
+    defaults = {
+        "reseed": None,
+        "uvm_test": "",
+        "uvm_test_seq": "",
+        "build_mode": "",
+        "sw_images": [],
+        "sw_build_device": "",
+        "sw_build_opts": [],
+        "run_timeout_mins": None,
+        "run_timeout_multiplier": None
+    }
+
+    @staticmethod
+    def create_tests(tdicts, sim_cfg):
+        '''
+        Create Test objects from a given list of raw dicts.
+        TODO: enhance the raw dict to include file scoped defaults.
+        Process enabled run modes and the set build mode.
+        Return a list of test objects.
+        '''
+
+        def get_pruned_en_run_modes(test_en_run_modes, global_en_run_modes):
+            pruned_en_run_modes = []
+            for test_en_run_mode in test_en_run_modes:
+                if test_en_run_mode not in global_en_run_modes:
+                    pruned_en_run_modes.append(test_en_run_mode)
+            return pruned_en_run_modes
+
+        tests_objs = []
+        # Pass 1: Create unique set of tests by merging tests with the same name
+        for tdict in tdicts:
+            # Create a new item
+            new_test_merged = False
+            new_test = Test(tdict)
+            for test in tests_objs:
+                # Merge new one with existing if available
+                if test.name == new_test.name:
+                    test.merge_mode(new_test)
+                    new_test_merged = True
+                    break
+
+            # Add the new test to the list if not already appended
+            if not new_test_merged:
+                tests_objs.append(new_test)
+                Test.item_names.append(new_test.name)
+
+        # Pass 2: Process dependencies
+        build_modes = getattr(sim_cfg, "build_modes", [])
+        run_modes = getattr(sim_cfg, "run_modes", [])
+
+        attrs = Test.defaults
+        for test_obj in tests_objs:
+            # Unpack run_modes first
+            en_run_modes = get_pruned_en_run_modes(test_obj.en_run_modes,
+                                                   sim_cfg.en_run_modes)
+            find_and_merge_modes(test_obj, en_run_modes, run_modes)
+
+            # Find and set the missing attributes from sim_cfg
+            # If not found in sim_cfg either, then throw a warning
+            # TODO: These should be file-scoped
+            for attr in attrs.keys():
+                # Check if attr value is default
+                val = getattr(test_obj, attr)
+                default_val = attrs[attr]
+                if val == default_val:
+                    # If sim_cfg specifies a value for this attribute and this
+                    # value isn't equal to default_val, then copy the sim_cfg
+                    # value across to the test object.
+                    global_val = getattr(sim_cfg, attr, None)
+                    if global_val is not None and global_val != default_val:
+
+                        # TODO: This is a workaround for a memory usage bug
+                        # that triggered issue #20550. It's a pretty hacky
+                        # solution! We should probably tidy this up properly.
+                        setattr(test_obj, attr, deepcopy(global_val))
+
+            # Unpack the build mode for this test
+            build_mode_objs = find_and_merge_modes(test_obj,
+                                                   [test_obj.build_mode],
+                                                   build_modes,
+                                                   merge_modes=False)
+            test_obj.build_mode = build_mode_objs[0]
+
+            # Error if set build mode is actually a sim mode
+            if test_obj.build_mode.is_sim_mode is True:
+                log.error(
+                    "Test \"%s\" uses build_mode %s which is actually a sim mode",
+                    test_obj.name, test_obj.build_mode.name)
+                sys.exit(1)
+
+            # Merge build_mode's params with self
+            test_obj.pre_run_cmds.extend(test_obj.build_mode.pre_run_cmds)
+            test_obj.post_run_cmds.extend(test_obj.build_mode.post_run_cmds)
+            test_obj.run_opts.extend(test_obj.build_mode.run_opts)
+            test_obj.sw_images.extend(test_obj.build_mode.sw_images)
+            test_obj.sw_build_opts.extend(test_obj.build_mode.sw_build_opts)
+
+        # Return the list of tests
+        return tests_objs
+
+    @staticmethod
+    def merge_global_opts(tests, global_pre_build_cmds, global_post_build_cmds,
+                          global_build_opts, global_pre_run_cmds,
+                          global_post_run_cmds, global_run_opts,
+                          global_sw_images, global_sw_build_opts):
+        processed_build_modes = set()
+        for test in tests:
+            if test.build_mode.name not in processed_build_modes:
+                test.build_mode.pre_build_cmds.extend(global_pre_build_cmds)
+                test.build_mode.post_build_cmds.extend(global_post_build_cmds)
+                test.build_mode.build_opts.extend(global_build_opts)
+                processed_build_modes.add(test.build_mode.name)
+            test.pre_run_cmds.extend(global_pre_run_cmds)
+            test.post_run_cmds.extend(global_post_run_cmds)
+            test.run_opts.extend(global_run_opts)
+            test.sw_images.extend(global_sw_images)
+            test.sw_build_opts.extend(global_sw_build_opts)
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Testplan.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Testplan.py
index c69f68c5..056583e4 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Testplan.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Testplan.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""Testpoint and Testplan classes for maintaining the testplan
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Timer.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Timer.py
index 7447ceb1..a9b245ca 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Timer.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/Timer.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/ascentlint-report-parser.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/ascentlint-report-parser.py
index 6e977406..2edb2bf8 100755
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/ascentlint-report-parser.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/ascentlint-report-parser.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""Parses lint report and dump filtered messages in hjson format.
@@ -67,6 +67,7 @@ def main():
             ("flow_error", r"^Error: .*"),
             ("flow_error", r"^ERROR.*"),
             ("flow_error", r"^  ERR .*"),
+            ("flow_info", r"^Warning: License will expire.*"),
             ("flow_warning", r"^Warning: .*"),
             # TODO: struct assignment labels within concatenation
             # not supported. check with newer ascentlint version.
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/dvsim.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/dvsim.py
index dfab5334..3d591bc4 100755
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/dvsim.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/dvsim.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 """dvsim is a command line tool to deploy ASIC tool flows such as regressions
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/examples/testplanner/common_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/examples/testplanner/common_testplan.hjson
index 5207b2bc..a07cebe7 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/examples/testplanner/common_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/examples/testplanner/common_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/examples/testplanner/foo_sim_results.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/examples/testplanner/foo_sim_results.hjson
index d517242b..6c37d260 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/examples/testplanner/foo_sim_results.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/examples/testplanner/foo_sim_results.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/examples/testplanner/foo_testplan.hjson b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/examples/testplanner/foo_testplan.hjson
index 4a9b7108..c4e5c9ef 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/examples/testplanner/foo_testplan.hjson
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/examples/testplanner/foo_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/meridianrdc-report-parser.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/meridianrdc-report-parser.py
index c8c7999b..a8bd6fed 100755
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/meridianrdc-report-parser.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/meridianrdc-report-parser.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""Parses Meridian RDC report and dump filtered messages in hjson format.
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/modes.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/modes.py
new file mode 100644
index 00000000..d1e38e70
--- /dev/null
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/modes.py
@@ -0,0 +1,287 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+import logging as log
+import sys
+from typing import List, Optional
+
+
+class Mode:
+    """A collection of options that represents a single mode.
+
+    This might be a run mode (options for an EDA tool?), a build mode, a test
+    or a regression.
+    """
+
+    def __init__(self, type_name: str, mdict):
+        keys = mdict.keys()
+        attrs = self.__dict__.keys()
+
+        if 'name' not in keys:
+            log.error("Key \"name\" missing in mode %s", mdict)
+            sys.exit(1)
+
+        if not hasattr(self, "type"):
+            log.fatal("Key \"type\" is missing or invalid")
+            sys.exit(1)
+
+        for key in keys:
+            if key not in attrs:
+                log.error(f"Key {key} in {mdict} is invalid. Supported "
+                          f"attributes for a {type_name} are {attrs}")
+                sys.exit(1)
+            setattr(self, key, mdict[key])
+
+    def get_sub_modes(self):
+        return getattr(self, "en_" + self.type + "_modes", [])
+
+    def set_sub_modes(self, sub_modes):
+        setattr(self, "en_" + self.type + "_modes", sub_modes)
+
+    def merge_mode(self, mode: 'Mode') -> None:
+        '''Update this object by merging it with mode.'''
+
+        sub_modes = self.get_sub_modes()
+        is_sub_mode = mode.name in sub_modes
+
+        # If the mode to be merged in is not known as a sub-mode of this mode
+        # then something has gone wrong. Generate an error.
+        if mode.name != self.name and not is_sub_mode:
+            log.error(f"Cannot merge mode {self.name} with {mode.name}: "
+                      f"it is not a sub-mode and they are not equal.")
+            sys.exit(1)
+
+        # Merge attributes in self with attributes in mode arg, since they are
+        # the same mode but set in separate files, or a sub-mode.
+        for attr, self_attr_val in self.__dict__.items():
+            mode_attr_val = getattr(mode, attr, None)
+
+            # If sub-mode, skip the name: it could differ.
+            if is_sub_mode and attr == 'name':
+                continue
+
+            # If mode's value is None, then nothing to do here.
+            if mode_attr_val is None:
+                continue
+
+            # If self value is None, then replace with mode's value.
+            if self_attr_val is None:
+                setattr(self, attr, mode_attr_val)
+                continue
+
+            # If they are equal, then nothing to do here.
+            if self_attr_val == mode_attr_val:
+                continue
+
+            # Extend if they are both lists.
+            if isinstance(self_attr_val, list):
+                assert isinstance(mode_attr_val, list)
+                self_attr_val.extend(mode_attr_val)
+                continue
+
+            # If the current val is default, replace with new.
+            scalar_types = {str: "", int: -1}
+            default_val = scalar_types.get(type(self_attr_val))
+
+            if type(self_attr_val) in scalar_types.keys(
+            ) and self_attr_val == default_val:
+                setattr(self, attr, mode_attr_val)
+                continue
+
+            # Check if their types are compatible.
+            if type(self_attr_val) != type(mode_attr_val):
+                log.error(
+                    "Mode %s cannot be merged into %s due to a conflict "
+                    "(type mismatch): %s: {%s(%s), %s(%s)}", mode.name,
+                    self.name, attr, str(self_attr_val),
+                    str(type(self_attr_val)), str(mode_attr_val),
+                    str(type(mode_attr_val)))
+                sys.exit(1)
+
+            # Check if they are different non-default values.
+            if self_attr_val != default_val and mode_attr_val != default_val:
+                log.error(
+                    "Mode %s cannot be merged into %s due to a conflict "
+                    "(unable to pick one from different values): "
+                    "%s: {%s, %s}", mode.name, self.name, attr,
+                    str(self_attr_val), str(mode_attr_val))
+                sys.exit(1)
+
+        # Check newly appended sub_modes, remove 'self' and duplicates
+        sub_modes = self.get_sub_modes()
+
+        if sub_modes != []:
+            new_sub_modes = []
+            for sub_mode in sub_modes:
+                if self.name != sub_mode and sub_mode not in new_sub_modes:
+                    new_sub_modes.append(sub_mode)
+            self.set_sub_modes(new_sub_modes)
+        return True
+
+    @staticmethod
+    def create_modes(ModeType, mdicts):
+        '''
+        Create modes of type ModeType from a given list of raw dicts
+        Process dependencies.
+        Return a list of modes objects.
+        '''
+
+        def merge_sub_modes(mode, parent, objs):
+            # Check if there are modes available to merge
+            sub_modes = mode.get_sub_modes()
+            if sub_modes == []:
+                return
+
+            # Set parent if it is None. If not, check cyclic dependency
+            if parent is None:
+                parent = mode
+            else:
+                if mode.name == parent.name:
+                    log.error("Cyclic dependency when processing mode \"%s\"",
+                              mode.name)
+                    sys.exit(1)
+
+            for sub_mode in sub_modes:
+                # Find the sub_mode obj from str
+                found = False
+                for obj in objs:
+                    if sub_mode == obj.name:
+                        # First recursively merge the sub_modes
+                        merge_sub_modes(obj, parent, objs)
+
+                        # Now merge the sub mode with mode
+                        mode.merge_mode(obj)
+                        found = True
+                        break
+                if not found:
+                    log.error(
+                        "Sub mode \"%s\" added to mode \"%s\" was not found!",
+                        sub_mode, mode.name)
+                    sys.exit(1)
+
+        modes_objs = []
+        # create a default mode if available
+        default_mode = ModeType.get_default_mode()
+        if default_mode is not None:
+            modes_objs.append(default_mode)
+
+        # Process list of raw dicts that represent the modes
+        # Pass 1: Create unique set of modes by merging modes with the same name
+        for mdict in mdicts:
+            # Create a new item
+            new_mode_merged = False
+            new_mode = ModeType(mdict)
+            for mode in modes_objs:
+                # Merge new one with existing if available
+                if mode.name == new_mode.name:
+                    mode.merge_mode(new_mode)
+                    new_mode_merged = True
+                    break
+
+            # Add the new mode to the list if not already appended
+            if not new_mode_merged:
+                modes_objs.append(new_mode)
+                ModeType.item_names.append(new_mode.name)
+
+        # Pass 2: Recursively expand sub modes within parent modes
+        for mode in modes_objs:
+            merge_sub_modes(mode, None, modes_objs)
+
+        # Return the list of objects
+        return modes_objs
+
+    @staticmethod
+    def get_default_mode(ModeType):
+        return None
+
+
+def find_mode(mode_name: str, modes: List[Mode]) -> Optional[Mode]:
+    '''Search through a list of modes and return the one with the given name.
+
+    Return None if nothing was found.
+    '''
+    for mode in modes:
+        if mode_name == mode.name:
+            return mode
+    return None
+
+
+def find_and_merge_modes(mode: Mode,
+                         mode_names: List[str],
+                         modes: List[Mode],
+                         merge_modes: bool = True):
+    found_mode_objs = []
+    for mode_name in mode_names:
+        sub_mode = find_mode(mode_name, modes)
+        if sub_mode is not None:
+            found_mode_objs.append(sub_mode)
+            if merge_modes is True:
+                mode.merge_mode(sub_mode)
+        else:
+            log.error("Mode \"%s\" enabled within mode \"%s\" not found!",
+                      mode_name, mode.name)
+            sys.exit(1)
+    return found_mode_objs
+
+
+class BuildMode(Mode):
+    """
+    Build modes.
+    """
+
+    # Maintain a list of build_modes str
+    item_names = []
+
+    def __init__(self, bdict):
+        self.name = ""
+        self.type = "build"
+        self.is_sim_mode = 0
+        self.pre_build_cmds = []
+        self.post_build_cmds = []
+        self.en_build_modes = []
+        self.build_opts = []
+        self.build_timeout_mins = None
+        self.pre_run_cmds = []
+        self.post_run_cmds = []
+        self.run_opts = []
+        self.sw_images = []
+        self.sw_build_opts = []
+
+        super().__init__("build mode", bdict)
+        self.en_build_modes = list(set(self.en_build_modes))
+
+    @staticmethod
+    def get_default_mode():
+        return BuildMode({"name": "default"})
+
+
+class RunMode(Mode):
+    """A collection of options for running a test."""
+
+    # Maintain a list of run_modes str
+    item_names = []
+
+    def __init__(self, rdict):
+        self.name = ""
+        self.type = "run"
+        self.reseed = None
+        self.pre_run_cmds = []
+        self.post_run_cmds = []
+        self.en_run_modes = []
+        self.run_opts = []
+        self.uvm_test = ""
+        self.uvm_test_seq = ""
+        self.build_mode = ""
+        self.run_timeout_mins = None
+        self.run_timeout_multiplier = None
+        self.sw_images = []
+        self.sw_build_device = ""
+        self.sw_build_opts = []
+
+        super().__init__("run mode", rdict)
+        self.en_run_modes = list(set(self.en_run_modes))
+
+    @staticmethod
+    def get_default_mode():
+        return None
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/qsubopts.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/qsubopts.py
index c94c1c1e..409893bc 100755
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/qsubopts.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/qsubopts.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 # -*- coding: utf-8 -*-
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/results_server.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/results_server.py
index 00aa6486..e117beb9 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/results_server.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/results_server.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/sim_utils.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/sim_utils.py
index 66aa0c70..152bede0 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/sim_utils.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/sim_utils.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 """
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/style.css b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/style.css
index f89293ae..49c283fc 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/style.css
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/style.css
@@ -1,4 +1,4 @@
-/* Copyright lowRISC contributors. */
+/* Copyright lowRISC contributors (OpenTitan project). */
 /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
 /* SPDX-License-Identifier: Apache-2.0 */
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/testplanner.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/testplanner.py
index 707671a9..1f2bd405 100755
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/testplanner.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/testplanner.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""Command-line tool to parse and process testplan Hjson
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/utils.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/utils.py
index 2bff23f1..75680b31 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/utils.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/utils.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/utils_test.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/utils_test.py
index f3a01796..a06e7f80 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/utils_test.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/utils_test.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/veriblelint-report-parser.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/veriblelint-report-parser.py
index 6ed09b28..d7960e8d 100755
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/veriblelint-report-parser.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/veriblelint-report-parser.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""Parses lint report and dump filtered messages in hjson format.
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/verilator-report-parser.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/verilator-report-parser.py
index d57e16c6..8ff2a69b 100755
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/verilator-report-parser.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/verilator-report-parser.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""Parses lint report and dump filtered messages in hjson format.
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/verixcdc-report-parser.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/verixcdc-report-parser.py
index 1b176766..c3a18fc6 100755
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/verixcdc-report-parser.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/dvsim/verixcdc-report-parser.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""Parses cdc report and dump filtered messages in hjson format.
@@ -8,8 +8,6 @@
 import logging as log
 import re
 import sys
-import os
-import hjson
 
 from pathlib import Path
 from LintParser import LintParser
@@ -34,7 +32,6 @@ def extract_rule_patterns(file_path: Path):
     category = ''
     severity = ''
     known_rule_names = {}
-    total_msgs = 0
     # extract the summary table
     m = re.findall(
         r'^Summary of Policy: NEW((?:.|\n|\r\n)*)Rule Details of Policy: NEW',
@@ -43,10 +40,7 @@ def extract_rule_patterns(file_path: Path):
         # step through the table and identify rule names and their
         # category and severity
         for line in m[0].split('\n'):
-            if re.match(r'^POLICY\s+NEW', line):
-                total = re.findall(r'^POLICY\s+NEW\s+([0-9]+)', line)
-                total_msgs = int(total[0])
-            elif re.match(r'^ GROUP\s+SDC_ENV_LINT', line):
+            if re.match(r'^ GROUP\s+SDC_ENV_LINT', line):
                 category = 'sdc'
             elif re.match(r'^ GROUP\s+VCDC_SETUP_CHECKS', line):
                 category = 'setup'
@@ -66,7 +60,6 @@ def extract_rule_patterns(file_path: Path):
                 rule = re.findall(
                     r'^  INSTANCE\s+([a-zA-Z0-9\_]+)\s+([0-9\_]+)', line)
                 name = rule[0][0]
-                count = int(rule[0][1])
                 # a few rules produce messages with different severities but
                 # the same rule labels. for simplicity, we promote messages
                 # from lower severity buckets to the severity bucket where
@@ -163,19 +156,19 @@ def main():
     # Patterns for lint.log
     parser_args.update({
         args.repdir.joinpath('build.log'): [
-        # If lint warnings have been found, the lint tool will exit
-        # with a nonzero status code and fusesoc will always spit out
-        # an error like
-        #
-        #    ERROR: Failed to build ip:core:name:0.1 : 'make' exited with an error code
-        #
-        # If we found any other warnings or errors, there's no point in
-        # listing this too. BUT we want to make sure we *do* see this
-        # error if there are no other errors or warnings, since that
-        # shows something has come unstuck. (Probably the lint tool
-        # spat out a warning that we don't understand)
-        ("fusesoc-error",
-         r"^ERROR: Failed to build .* : 'make' exited with an error code")
+            # If lint warnings have been found, the lint tool will exit
+            # with a nonzero status code and fusesoc will always spit out
+            # an error like
+            #
+            #    ERROR: Failed to build ip:core:name:0.1 : 'make' exited with an error code
+            #
+            # If we found any other warnings or errors, there's no point in
+            # listing this too. BUT we want to make sure we *do* see this
+            # error if there are no other errors or warnings, since that
+            # shows something has come unstuck. (Probably the lint tool
+            # spat out a warning that we don't understand)
+            ("fusesoc-error",
+             r"^ERROR: Failed to build .* : 'make' exited with an error code")
         ]
     })
 
@@ -197,14 +190,14 @@ def main():
             # #39122: non-positive repeat
             # #39491: parameter in package
             ("flow_warning", r"^  "
-                             "(?!WARN \[#25010\])"
-                             "(?!WARN \[#25011\])"
-                             "(?!WARN \[#25012\])"
-                             "(?!WARN \[#25013\])"
-                             "(?!WARN \[#26038\])"
-                             "(?!WARN \[#39035\])"
-                             "(?!WARN \[#39122\])"
-                             "(?!WARN \[#39491\])"
+                             "(?!WARN \[#25010\])"  # noqa: W605
+                             "(?!WARN \[#25011\])"  # noqa: W605
+                             "(?!WARN \[#25012\])"  # noqa: W605
+                             "(?!WARN \[#25013\])"  # noqa: W605
+                             "(?!WARN \[#26038\])"  # noqa: W605
+                             "(?!WARN \[#39035\])"  # noqa: W605
+                             "(?!WARN \[#39122\])"  # noqa: W605
+                             "(?!WARN \[#39491\])"  # noqa: W605
                              "WARN .*"),
             ("flow_info", r"^  INFO .*")
         ]
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/README.md b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/README.md
index 4c85d336..14c965ce 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/README.md
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/README.md
@@ -104,7 +104,7 @@ IP. The following describes their contents in each source generated:
     This is the monitor component extended from `dv_base_monitor`. It provides
     the following items:
 
-    * `virtual protected task collect_trans(uvm_phase phase)`
+    * `virtual protected task collect_trans()`
 
         This is a shell task within which user is required to add logic to detect
         an event, sample the interface and create a transaction object and write
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent.core.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent.core.tpl
index ab4975ca..09ea94c3 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent.core.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent.core.tpl
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "${vendor}:dv:${name}_agent:0.1"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent.sv.tpl
index e4113586..685e0a2a 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent_cfg.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent_cfg.sv.tpl
index f693d577..39580154 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent_cfg.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent_cfg.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent_cov.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent_cov.sv.tpl
index 91e48d42..f0edb502 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent_cov.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent_cov.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent_pkg.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent_pkg.sv.tpl
index d8a64d95..40debbe2 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent_pkg.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/agent_pkg.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/base_seq.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/base_seq.sv.tpl
index bc4eea9b..3787244f 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/base_seq.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/base_seq.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/base_test.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/base_test.sv.tpl
index 177ee02e..7947d1f5 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/base_test.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/base_test.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/base_vseq.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/base_vseq.sv.tpl
index ce11bb9c..9601f1b9 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/base_vseq.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/base_vseq.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/bind.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/bind.sv.tpl
index 8440fad9..053a8980 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/bind.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/bind.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/common_vseq.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/common_vseq.sv.tpl
index 8a32d180..cc49f0bb 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/common_vseq.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/common_vseq.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/cov_excl.el.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/cov_excl.el.tpl
index 18be5a79..aca5bfa4 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/cov_excl.el.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/cov_excl.el.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/device_driver.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/device_driver.sv.tpl
index ae46511d..253a99ed 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/device_driver.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/device_driver.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/driver.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/driver.sv.tpl
index 35ac1435..7522f366 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/driver.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/driver.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env.core.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env.core.tpl
index 97f65ee5..4897900a 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env.core.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env.core.tpl
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "${vendor}:dv:${name}_env:0.1"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env.sv.tpl
index cb2f1853..c91ed05f 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env_cfg.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env_cfg.sv.tpl
index 879dc51c..24a1efd1 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env_cfg.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env_cfg.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env_cov.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env_cov.sv.tpl
index 18cd77c5..f7f9bbe0 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env_cov.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env_cov.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env_pkg.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env_pkg.sv.tpl
index af451a33..b589c634 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env_pkg.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/env_pkg.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/gen_agent.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/gen_agent.py
index 56d772b1..ee81ae14 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/gen_agent.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/gen_agent.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 """Generate SystemVerilog UVM agent extended freom our DV lib
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/gen_env.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/gen_env.py
index 98b59439..61c08b03 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/gen_env.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/gen_env.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 """Generate SystemVerilog UVM agent extended freom our DV lib
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/host_driver.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/host_driver.sv.tpl
index 08103e0b..a446593c 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/host_driver.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/host_driver.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/if.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/if.sv.tpl
index 5f15a32b..8b8100bd 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/if.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/if.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/index.md.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/index.md.tpl
index c06fc246..9de0c36e 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/index.md.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/index.md.tpl
@@ -41,7 +41,6 @@ In addition, it instantiates the following interfaces, connects them to the DUT
 * ${name.upper()} IOs
 * Interrupts ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}}))
 * Alerts ([`alert_esc_if`]({{< relref "hw/dv/sv/alert_esc_agent/doc" >}}))
-* Devmode ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}}))
 
 ${'###'} Common DV utility components
 The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/item.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/item.sv.tpl
index 715c6d15..7b1c6433 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/item.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/item.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/monitor.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/monitor.sv.tpl
index df3d6e61..d1b36025 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/monitor.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/monitor.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -25,7 +25,7 @@ class ${name}_monitor extends dv_base_monitor #(
   endtask
 
   // collect transactions forever - already forked in dv_base_monitor::run_phase
-  virtual protected task collect_trans(uvm_phase phase);
+  virtual protected task collect_trans();
     forever begin
       // TODO: detect event
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/scoreboard.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/scoreboard.sv.tpl
index d565c9d4..5cfbcf33 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/scoreboard.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/scoreboard.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/seq_list.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/seq_list.sv.tpl
index 9b515075..645dfa24 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/seq_list.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/seq_list.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/sim.core.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/sim.core.tpl
index c65dc35e..0d83b393 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/sim.core.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/sim.core.tpl
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "${vendor}:dv:${name}_sim:0.1"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/sim_cfg.hjson.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/sim_cfg.hjson.tpl
index 1aaa6047..879dc77e 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/sim_cfg.hjson.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/sim_cfg.hjson.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/smoke_vseq.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/smoke_vseq.sv.tpl
index aaf859c2..e78a24b9 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/smoke_vseq.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/smoke_vseq.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/sva.core.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/sva.core.tpl
index 9feae236..22dfffc1 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/sva.core.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/sva.core.tpl
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:${name}_sva:0.1"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/tb.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/tb.sv.tpl
index 9e8731d0..79e9b7f0 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/tb.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/tb.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -14,7 +14,6 @@ module tb;
   `include "dv_macros.svh"
 
   wire clk, rst_n;
-  wire devmode;
 % if is_cip:
 % if has_interrupts:
   wire [NUM_MAX_INTERRUPTS-1:0] interrupts;
@@ -27,7 +26,6 @@ module tb;
 % if has_interrupts:
   pins_if #(NUM_MAX_INTERRUPTS) intr_if(interrupts);
 % endif
-  pins_if #(1) devmode_if(devmode);
   tl_if tl_if(.clk(clk), .rst_n(rst_n));
 % endif
 % for agent in env_agents:
@@ -72,7 +70,6 @@ module tb;
 % if has_interrupts:
     uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
 % endif
-    uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if);
     uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if);
 % endif
 % for agent in env_agents:
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/test.core.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/test.core.tpl
index a247cd74..537da499 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/test.core.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/test.core.tpl
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "${vendor}:dv:${name}_test:0.1"
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/test_pkg.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/test_pkg.sv.tpl
index 3bd6ea56..7316e7ca 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/test_pkg.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/test_pkg.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/testplan.hjson.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/testplan.hjson.tpl
index d63ca28d..5a0fec8a 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/testplan.hjson.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/testplan.hjson.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/uvmdvgen.py b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/uvmdvgen.py
index 5cca559d..e804de6f 100755
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/uvmdvgen.py
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/uvmdvgen.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 r"""Command-line tool to generate boilerplate DV testbench.
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/virtual_sequencer.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/virtual_sequencer.sv.tpl
index e4cd3c42..3ca0809a 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/virtual_sequencer.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/virtual_sequencer.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/vseq_list.sv.tpl b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/vseq_list.sv.tpl
index 1c99c138..4bc7068e 100644
--- a/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/vseq_list.sv.tpl
+++ b/vendor/lowrisc_ibex/vendor/lowrisc_ip/util/uvmdvgen/vseq_list.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ibex/vendor/patches/lowrisc_ip/dv_tools/0001-Change-xcelium-cov_merge.tcl-to-pass-databases-in-ru.patch b/vendor/lowrisc_ibex/vendor/patches/lowrisc_ip/dv_tools/0002-Change-xcelium-cov_merge.tcl-to-pass-databases-in-ru.patch
similarity index 100%
rename from vendor/lowrisc_ibex/vendor/patches/lowrisc_ip/dv_tools/0001-Change-xcelium-cov_merge.tcl-to-pass-databases-in-ru.patch
rename to vendor/lowrisc_ibex/vendor/patches/lowrisc_ip/dv_tools/0002-Change-xcelium-cov_merge.tcl-to-pass-databases-in-ru.patch

From 3a84bd6667a31f6afe1cf1857525109eb9442ecf Mon Sep 17 00:00:00 2001
From: Marno van der Maas <mvdmaas+git@lowrisc.org>
Date: Fri, 11 Apr 2025 11:48:35 +0100
Subject: [PATCH 2/2] Update lowrisc_ip to lowRISC/opentitan@d268f271f4

Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
d268f271f4f75aeb8f3bf9624a497ae5bfb9c47e

* [rtl] MuBi encoding of iCache memory ctrl signals (Pascal Nasahl)
* [sram_ctrl] Add readback feature (Pascal Nasahl)
* [prim_pad_wrapper,rtl] Change input enable to active-high (Andreas
  Kurth)
* [hmac/rtl] Wait for digest of complete block when stopping (Martin
  Velay)
* [prim_sha2_pad,rtl] Signal msg feed complete also when stopping
  (Andreas Kurth)
* [prim_sha2_pad,rtl] Go to idle (without padding) when told to stop
  (Andreas Kurth)
* [prim_sha2_pad,rtl] Refactor comparison on tx_count and msg len into
  signal (Andreas Kurth)
* [prim_sha2_pad,rtl] Fix setting of digest mode when continuing
  (Andreas Kurth)
* [hmac/prim_2,rtl] Do not clear redundant digest values (Ghada
  Dessouky)
* [prim,fpv] Tweak how a parameter gets used in some assertions
  (Rupert Swarbrick)
* [prim,fpv] Fix trivial lint warning in prim_fifo_sync_assert_fpv
  (Rupert Swarbrick)
* [prim,rtl] Fix trivial lint warning in prim_fifo_sync (Rupert
  Swarbrick)
* [top_earlgrey,pinmux] Add input disable attribute for non-manual
  pads (Andreas Kurth)
* [ipgen,flash_ctrl] Fix core files (Guillermo Maturana)
* [prim,rtl] Avoid unnecessary check in prim_esc_receiver.sv (Rupert
  Swarbrick)
* [prim,fpv] Use PossibleActions param in prim_esc_receiver (Rupert
  Swarbrick)
* [prim_diff_decode] Use `prim_xnor2` to detect integrity issue
  (Andreas Kurth)
* [prim] Fix typo'd loop increment (James Wainwright)
* [hmac/prim_sha2,rtl] Implement SW error for invalid HMAC config
  (Ghada Dessouky)
* [prim_sha2,rtl/dv] Fix secret value wiping (Ghada Dessouky)
* [prim,rtl,fpv] Fix typo in assertion in prim_alert_receiver (Rupert
  Swarbrick)
* [fpv,prim] Drop prim_count_expected_failure.hjson (Rupert Swarbrick)
* [fpv,prim] Generalise from DecrNeverTrue to listing possible actions
  (Rupert Swarbrick)
* [prim,fpv] Correct assertions for commit_i input (Rupert Swarbrick)
* [prim,fpv] Rephrase some "backwards" assertions in prim_count
  (Rupert Swarbrick)
* [prim,fpv] Properly "waive" some unreachable prim_count assertions
  (Rupert Swarbrick)
* [prim,fpv] Fix width of FPV variable in prim_arbiter_ppc.sv (Rupert
  Swarbrick)
* [prim,fpv] Rephrase prim_count error assertions (Rupert Swarbrick)
* [prim,fpv] Fix port list in prim_count_tb (Rupert Swarbrick)
* [prim_ram_1p_scr] Align documentation with actual implementation
  (Pirmin Vogel)
* [prim, rom_ctrl] Increase number of PRINCE rounds for improved
  security (Pirmin Vogel)
* [prim,fpv] Make file structure slightly clearer (Rupert Swarbrick)
* [prim,fpv] Shorten a variable name (prim_hier -> hier) (Rupert
  Swarbrick)
* [prim,fpv] Tidy up and document some FPV macros (Rupert Swarbrick)
* [rtl,comments] Fix some comments (Guillermo Maturana)
* [dv,prim] Clarification of reset behavior (Adrian Lees)
* [ast] Add dependency in fileset_partner to select correct ast_pkg
  (Sharon Topaz)
* [prim,fpv] Only allow unconstrained counters in prim_count FPV
  (Rupert Swarbrick)
* [prim,dv] Tweak ASSERT_FINAL to be a no-op if FPV enabled (Rupert
  Swarbrick)
* [prim,tlul,rtl] Explicitly cast a "1" to specific number of bits
  (Rupert Swarbrick)
* Add the project name to the copyright header (Michael Munday)
* Remove trailing whitespaces (Pirmin Vogel)
* [hmac] Coding style and minor fixes (Ghada Dessouky)
* [prim_fifo_sync_cnt] Minor code cleanup (Andreas Kurth)
* [prim_fifo_sync_cnt] Fix signedness of Depth parameter (Andreas
  Kurth)
* [prim_fifo_sync] Keep wraparound pointers contained within
  `prim_fifo_sync_cnt` (Andreas Kurth)
* [prim_fifo_sync] Move pointer and depth calculation to
  `prim_fifo_sync_cnt` (Andreas Kurth)
* [prim_fifo_sync] Remove out-commented RTL code (Andreas Kurth)
* [prim_fifo_sync_cnt] Improve module and parameter documentation
  (Andreas Kurth)
* [lint] Demote licence warning in AscentLint parser (Rupert
  Swarbrick)
* [prim] Add support for MuBi's up to 32bit (Michael Schaffner)
* [otp_ctrl] Increase Hamming distance in OTP commands (Michael
  Schaffner)
* Make .core files pass FuseSoC 2 schema validator (Olof Kindgren)
* [prim_sha2,rtl] Add key_length type and change type encodings (Ghada
  Dessouky)
* [dv,sram_ctrl] Fix a few failing tests (Guillermo Maturana)
* [prim/lint] Fix long line lint error in prim_intr_hw (Alexander
  Williams)
* [doc,prim] Improve comments in prim_intr_hw (Harry Callahan)
* [prim_sha2] Add `hash_running_o` (Andreas Kurth)
* [prim_sha2] Add `hash_continue_i` (Andreas Kurth)
* [prim_sha2] Make digest writable from input while disabled (Andreas
  Kurth)
* [prim] Fix lint error in shadow register subreg primitive (Pirmin
  Vogel)
* [primgen] Fix parameters in a primgen template (Rupert Swarbrick)
* [prim] Avoid unnecessary Impl parameter in prim_onehot_check (Rupert
  Swarbrick)
* [hw,prim,sha2] Fix syntax error in waiver file (Robert Schilling)
* [prim_sha2,rtl] prim_sha2 minor RTL and styling fixes (Ghada
  Dessouky)
* [prim_sha2,rtl] Add RTL implementation + update core + lint waivers
  (Ghada Dessouky)
* [clkmgr] Restructure division clock feedback (Michael Schaffner)
* Revert "[edn] Move prim_edn_req out of prim" (Rupert Swarbrick)
* [rtl, prim] Add 'commit' functionality to prim_count (Greg Chadwick)
* [prim] Fix up 1r1w cores (Alexander Williams)
* [prim] Add two-port memory ECC wrappers (Michael Schaffner)
* [prim] Add two-port memory implementation (Michael Schaffner)
* [prim] Make copies of dual port memory files (Michael Schaffner)
* [otp_ctrl] Add option to disable integrity on a partition (Michael
  Schaffner)
* [prim_trivium] Allow dynamically disabling the lockup protection
  (Pirmin Vogel)
* [scrambling] Add reference to RFC issue (Michael Schaffner)
* [edn] Move prim_edn_req out of prim (Rupert Swarbrick)
* [reggen] Remove the devmode input (Michael Schaffner)
* [prim, rom_ctrl] Remove S&P layer from data scrambling (Michael
  Schaffner)
* [prim] Fix typo in Trivium/Bivium stream cipher primitives (Pirmin
  Vogel)

Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
---
 vendor/lowrisc_ip.lock.hjson                  |   2 +-
 vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.c    |   2 +-
 vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.core |   2 +-
 vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.h    |   2 +-
 vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.sv   |   2 +-
 .../lowrisc_ip/dv/dpi/uartdpi/uartdpi_sv.core |   2 +-
 vendor/lowrisc_ip/ip/prim/BUILD               |   2 +-
 .../lowrisc_ip/ip/prim/doc/prim_ram_1p_scr.md |  23 +-
 .../dv/prim_alert/data/prim_alert_cover.cfg   |   2 +-
 .../prim_alert/data/prim_alert_testplan.hjson |   2 +-
 .../ip/prim/dv/prim_alert/prim_alert_sim.core |   3 +-
 .../dv/prim_alert/prim_alert_sim_cfg.hjson    |   2 +-
 .../ip/prim/dv/prim_alert/tb/prim_alert_tb.sv |   2 +-
 .../prim/dv/prim_esc/data/prim_esc_cover.cfg  |   2 +-
 .../dv/prim_esc/data/prim_esc_testplan.hjson  |   2 +-
 .../ip/prim/dv/prim_esc/prim_esc_sim.core     |   2 +-
 .../prim/dv/prim_esc/prim_esc_sim_cfg.hjson   |   2 +-
 .../ip/prim/dv/prim_esc/tb/prim_esc_tb.sv     |   2 +-
 .../dv/prim_lfsr/data/prim_lfsr_cov_excl.el   |   2 +-
 .../dv/prim_lfsr/data/prim_lfsr_cover.cfg     |   2 +-
 .../ip/prim/dv/prim_lfsr/prim_lfsr_sim.core   |   2 +-
 .../prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson |   2 +-
 .../ip/prim/dv/prim_lfsr/prim_lfsr_tb.sv      |   2 +-
 .../crypto_dpi_present/crypto_dpi_present.cc  |   2 +-
 .../crypto_dpi_present.core                   |   2 +-
 .../crypto_dpi_present_pkg.sv                 |   2 +-
 .../prim_present/data/prim_present_cover.cfg  |   2 +-
 .../dv/prim_present/prim_present_sim.core     |   2 +-
 .../prim_present/prim_present_sim_cfg.hjson   |   2 +-
 .../dv/prim_present/tb/prim_present_tb.sv     |   2 +-
 .../crypto_dpi_prince/crypto_dpi_prince.c     |   2 +-
 .../crypto_dpi_prince/crypto_dpi_prince.core  |   2 +-
 .../crypto_dpi_prince_pkg.sv                  |   2 +-
 .../crypto_dpi_prince_sim_opts.hjson          |   2 +-
 .../crypto_dpi_prince/crypto_prince_ref.core  |   2 +-
 .../crypto_dpi_prince/prince_ref.h            |   2 +-
 .../dv/prim_prince/data/prim_prince_cover.cfg |   2 +-
 .../prim/dv/prim_prince/prim_prince_sim.core  |   2 +-
 .../dv/prim_prince/prim_prince_sim_cfg.hjson  |   2 +-
 .../prim/dv/prim_prince/tb/prim_prince_tb.sv  |   2 +-
 .../dv/prim_ram_scr/cpp/scramble_model.cc     |  34 +-
 .../dv/prim_ram_scr/cpp/scramble_model.core   |   2 +-
 .../prim/dv/prim_ram_scr/cpp/scramble_model.h |  14 +-
 .../ip/prim/dv/prim_secded/secded_enc.c       |   2 +-
 .../ip/prim/dv/prim_secded/secded_enc.core    |   2 +-
 .../ip/prim/dv/prim_secded/secded_enc.h       |   2 +-
 .../fpv/prim_alert_rxtx_async_fatal_fpv.core  |   2 +-
 .../prim/fpv/prim_alert_rxtx_async_fpv.core   |   2 +-
 .../prim/fpv/prim_alert_rxtx_fatal_fpv.core   |   2 +-
 .../ip/prim/fpv/prim_alert_rxtx_fpv.core      |   2 +-
 .../ip/prim/fpv/prim_arbiter_fixed_fpv.core   |   2 +-
 .../ip/prim/fpv/prim_arbiter_ppc_fpv.core     |   2 +-
 .../ip/prim/fpv/prim_arbiter_tree_fpv.core    |   2 +-
 .../fpv/prim_count_expected_failure.hjson     |  13 -
 .../ip/prim/fpv/prim_count_fpv.core           |   2 +-
 .../ip/prim/fpv/prim_esc_rxtx_fpv.core        |   2 +-
 .../fpv/prim_fifo_async_sram_adapter_fpv.core |   2 +-
 .../ip/prim/fpv/prim_fifo_sync_fpv.core       |   2 +-
 .../ip/prim/fpv/prim_keccak_fpv.core          |   2 +-
 .../lowrisc_ip/ip/prim/fpv/prim_lfsr_fpv.core |   2 +-
 .../ip/prim/fpv/prim_packer_fpv.core          |   2 +-
 .../ip/prim/fpv/prim_secded_22_16_fpv.core    |   3 +-
 .../ip/prim/fpv/prim_secded_28_22_fpv.core    |   3 +-
 .../ip/prim/fpv/prim_secded_39_32_fpv.core    |   3 +-
 .../ip/prim/fpv/prim_secded_64_57_fpv.core    |   3 +-
 .../ip/prim/fpv/prim_secded_72_64_fpv.core    |   3 +-
 .../fpv/prim_secded_hamming_22_16_fpv.core    |   3 +-
 .../fpv/prim_secded_hamming_39_32_fpv.core    |   3 +-
 .../fpv/prim_secded_hamming_72_64_fpv.core    |   3 +-
 .../fpv/prim_secded_hamming_76_68_fpv.core    |   3 +-
 .../prim/fpv/prim_secded_inv_22_16_fpv.core   |   3 +-
 .../prim/fpv/prim_secded_inv_28_22_fpv.core   |   3 +-
 .../prim/fpv/prim_secded_inv_39_32_fpv.core   |   3 +-
 .../prim/fpv/prim_secded_inv_64_57_fpv.core   |   3 +-
 .../prim/fpv/prim_secded_inv_72_64_fpv.core   |   3 +-
 .../prim_secded_inv_hamming_22_16_fpv.core    |   3 +-
 .../prim_secded_inv_hamming_39_32_fpv.core    |   3 +-
 .../prim_secded_inv_hamming_72_64_fpv.core    |   3 +-
 .../prim_secded_inv_hamming_76_68_fpv.core    |   3 +-
 .../fpv/tb/prim_alert_rxtx_async_bind_fpv.sv  |   2 +-
 .../prim_alert_rxtx_async_fatal_bind_fpv.sv   |   2 +-
 .../fpv/tb/prim_alert_rxtx_async_fatal_tb.sv  |   2 +-
 .../prim/fpv/tb/prim_alert_rxtx_async_tb.sv   |   2 +-
 .../prim/fpv/tb/prim_alert_rxtx_bind_fpv.sv   |   2 +-
 .../fpv/tb/prim_alert_rxtx_fatal_bind_fpv.sv  |   2 +-
 .../prim/fpv/tb/prim_alert_rxtx_fatal_tb.sv   |   2 +-
 .../ip/prim/fpv/tb/prim_alert_rxtx_tb.sv      |   2 +-
 .../ip/prim/fpv/tb/prim_arbiter_fixed_tb.sv   |   2 +-
 .../ip/prim/fpv/tb/prim_arbiter_ppc_tb.sv     |   2 +-
 .../ip/prim/fpv/tb/prim_arbiter_tree_tb.sv    |   2 +-
 .../ip/prim/fpv/tb/prim_count_tb.sv           |   8 +-
 .../ip/prim/fpv/tb/prim_esc_rxtx_bind_fpv.sv  |  29 +-
 .../ip/prim/fpv/tb/prim_esc_rxtx_tb.sv        |  10 +-
 .../fpv/tb/prim_fifo_async_sram_adapter_tb.sv |   2 +-
 .../ip/prim/fpv/tb/prim_fifo_sync_bind_fpv.sv |   2 +-
 .../ip/prim/fpv/tb/prim_fifo_sync_tb.sv       |   2 +-
 .../ip/prim/fpv/tb/prim_keccak_tb.sv          |   3 +-
 .../lowrisc_ip/ip/prim/fpv/tb/prim_lfsr_tb.sv |   2 +-
 .../ip/prim/fpv/tb/prim_packer_tb.sv          |   2 +-
 .../prim/fpv/tb/prim_secded_22_16_bind_fpv.sv |   2 +-
 .../ip/prim/fpv/tb/prim_secded_22_16_tb.sv    |   2 +-
 .../prim/fpv/tb/prim_secded_28_22_bind_fpv.sv |   2 +-
 .../ip/prim/fpv/tb/prim_secded_28_22_tb.sv    |   2 +-
 .../prim/fpv/tb/prim_secded_39_32_bind_fpv.sv |   2 +-
 .../ip/prim/fpv/tb/prim_secded_39_32_tb.sv    |   2 +-
 .../prim/fpv/tb/prim_secded_64_57_bind_fpv.sv |   2 +-
 .../ip/prim/fpv/tb/prim_secded_64_57_tb.sv    |   2 +-
 .../prim/fpv/tb/prim_secded_72_64_bind_fpv.sv |   2 +-
 .../ip/prim/fpv/tb/prim_secded_72_64_tb.sv    |   2 +-
 .../tb/prim_secded_hamming_22_16_bind_fpv.sv  |   2 +-
 .../fpv/tb/prim_secded_hamming_22_16_tb.sv    |   2 +-
 .../tb/prim_secded_hamming_39_32_bind_fpv.sv  |   2 +-
 .../fpv/tb/prim_secded_hamming_39_32_tb.sv    |   2 +-
 .../tb/prim_secded_hamming_72_64_bind_fpv.sv  |   2 +-
 .../fpv/tb/prim_secded_hamming_72_64_tb.sv    |   2 +-
 .../tb/prim_secded_hamming_76_68_bind_fpv.sv  |   2 +-
 .../fpv/tb/prim_secded_hamming_76_68_tb.sv    |   2 +-
 .../fpv/tb/prim_secded_inv_22_16_bind_fpv.sv  |   2 +-
 .../prim/fpv/tb/prim_secded_inv_22_16_tb.sv   |   2 +-
 .../fpv/tb/prim_secded_inv_28_22_bind_fpv.sv  |   2 +-
 .../prim/fpv/tb/prim_secded_inv_28_22_tb.sv   |   2 +-
 .../fpv/tb/prim_secded_inv_39_32_bind_fpv.sv  |   2 +-
 .../prim/fpv/tb/prim_secded_inv_39_32_tb.sv   |   2 +-
 .../fpv/tb/prim_secded_inv_64_57_bind_fpv.sv  |   2 +-
 .../prim/fpv/tb/prim_secded_inv_64_57_tb.sv   |   2 +-
 .../fpv/tb/prim_secded_inv_72_64_bind_fpv.sv  |   2 +-
 .../prim/fpv/tb/prim_secded_inv_72_64_tb.sv   |   2 +-
 .../prim_secded_inv_hamming_22_16_bind_fpv.sv |   2 +-
 .../tb/prim_secded_inv_hamming_22_16_tb.sv    |   2 +-
 .../prim_secded_inv_hamming_39_32_bind_fpv.sv |   2 +-
 .../tb/prim_secded_inv_hamming_39_32_tb.sv    |   2 +-
 .../prim_secded_inv_hamming_72_64_bind_fpv.sv |   2 +-
 .../tb/prim_secded_inv_hamming_72_64_tb.sv    |   2 +-
 .../prim_secded_inv_hamming_76_68_bind_fpv.sv |   2 +-
 .../tb/prim_secded_inv_hamming_76_68_tb.sv    |   2 +-
 .../fpv/vip/prim_alert_rxtx_assert_fpv.sv     |   2 +-
 .../vip/prim_alert_rxtx_async_assert_fpv.sv   |   2 +-
 .../prim/fpv/vip/prim_esc_rxtx_assert_fpv.sv  |  17 +-
 .../prim/fpv/vip/prim_fifo_sync_assert_fpv.sv |   6 +-
 .../fpv/vip/prim_secded_22_16_assert_fpv.sv   |   2 +-
 .../fpv/vip/prim_secded_28_22_assert_fpv.sv   |   2 +-
 .../fpv/vip/prim_secded_39_32_assert_fpv.sv   |   2 +-
 .../fpv/vip/prim_secded_64_57_assert_fpv.sv   |   2 +-
 .../fpv/vip/prim_secded_72_64_assert_fpv.sv   |   2 +-
 .../prim_secded_hamming_22_16_assert_fpv.sv   |   2 +-
 .../prim_secded_hamming_39_32_assert_fpv.sv   |   2 +-
 .../prim_secded_hamming_72_64_assert_fpv.sv   |   2 +-
 .../prim_secded_hamming_76_68_assert_fpv.sv   |   2 +-
 .../vip/prim_secded_inv_22_16_assert_fpv.sv   |   2 +-
 .../vip/prim_secded_inv_28_22_assert_fpv.sv   |   2 +-
 .../vip/prim_secded_inv_39_32_assert_fpv.sv   |   2 +-
 .../vip/prim_secded_inv_64_57_assert_fpv.sv   |   2 +-
 .../vip/prim_secded_inv_72_64_assert_fpv.sv   |   2 +-
 ...rim_secded_inv_hamming_22_16_assert_fpv.sv |   2 +-
 ...rim_secded_inv_hamming_39_32_assert_fpv.sv |   2 +-
 ...rim_secded_inv_hamming_72_64_assert_fpv.sv |   2 +-
 ...rim_secded_inv_hamming_76_68_assert_fpv.sv |   2 +-
 vendor/lowrisc_ip/ip/prim/lint/prim.vlt       |   2 +-
 vendor/lowrisc_ip/ip/prim/lint/prim.waiver    |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_and2.waiver  |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_arbiter.vlt  |   2 +-
 .../ip/prim/lint/prim_arbiter.waiver          |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_assert.vlt   |   2 +-
 .../ip/prim/lint/prim_assert.waiver           |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_buf.waiver   |   2 +-
 .../ip/prim/lint/prim_cdc_rand_delay.vlt      |   2 +-
 .../ip/prim/lint/prim_cdc_rand_delay.waiver   |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_cipher.vlt   |   2 +-
 .../ip/prim/lint/prim_cipher_pkg.waiver       |   2 +-
 .../ip/prim/lint/prim_clock_buf.waiver        |   2 +-
 .../ip/prim/lint/prim_clock_div.waiver        |   2 +-
 .../ip/prim/lint/prim_clock_gating.waiver     |   2 +-
 .../ip/prim/lint/prim_clock_inv.waiver        |   2 +-
 .../ip/prim/lint/prim_clock_mux2.waiver       |   2 +-
 vendor/lowrisc_ip/ip/prim/lint/prim_count.vlt |   5 +-
 .../lowrisc_ip/ip/prim/lint/prim_count.waiver |   8 +-
 vendor/lowrisc_ip/ip/prim/lint/prim_crc32.vlt |   2 +-
 .../ip/prim/lint/prim_double_lfsr.vlt         |   3 +-
 .../ip/prim/lint/prim_double_lfsr.waiver      |   2 +-
 vendor/lowrisc_ip/ip/prim/lint/prim_fifo.vlt  |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_fifo.waiver  |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_flash.waiver |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_flop.waiver  |   2 +-
 .../ip/prim/lint/prim_flop_2sync.waiver       |   2 +-
 .../ip/prim/lint/prim_flop_en.waiver          |   2 +-
 .../ip/prim/lint/prim_lc_sender.waiver        |   5 +-
 .../lowrisc_ip/ip/prim/lint/prim_lfsr.waiver  |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_max_tree.vlt |   2 +-
 .../ip/prim/lint/prim_max_tree.waiver         |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_mubi.waiver  |   5 +-
 .../ip/prim/lint/prim_onehot_check.vlt        |   2 +-
 .../ip/prim/lint/prim_onehot_check.waiver     |   2 +-
 .../ip/prim/lint/prim_onehot_mux.waiver       |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_otp.waiver   |   2 +-
 .../ip/prim/lint/prim_pad_attr.waiver         |   2 +-
 .../ip/prim/lint/prim_pad_wrapper.waiver      |   2 +-
 .../ip/prim/lint/prim_ram_1p.waiver           |   2 +-
 .../ip/prim/lint/prim_ram_1p_adv.waiver       |   2 +-
 .../ip/prim/lint/prim_ram_1p_scr.vlt          |   2 +-
 .../ip/prim/lint/prim_ram_1r1w.waiver         |   8 +
 .../ip/prim/lint/prim_ram_2p.waiver           |   2 +-
 .../ip/prim/lint/prim_reg_we_check.waiver     |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_rom.waiver   |   2 +-
 .../ip/prim/lint/prim_rst_sync.waiver         |   2 +-
 .../ip/prim/lint/prim_secded.waiver           |   2 +-
 vendor/lowrisc_ip/ip/prim/lint/prim_sha2.vbl  |   9 +
 vendor/lowrisc_ip/ip/prim/lint/prim_sha2.vlt  |  12 +
 .../lowrisc_ip/ip/prim/lint/prim_sha2.waiver  |  45 ++
 .../ip/prim/lint/prim_sparse_fsm_flop.vlt     |   2 +-
 .../ip/prim/lint/prim_sparse_fsm_flop.waiver  |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_subreg.vlt   |   2 +-
 .../ip/prim/lint/prim_subreg.waiver           |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_sum_tree.vlt |   2 +-
 .../ip/prim/lint/prim_sum_tree.waiver         |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_trivium.vlt  |   2 +-
 .../ip/prim/lint/prim_trivium.waiver          |   2 +-
 .../ip/prim/lint/prim_usb_diff_rx.waiver      |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_xnor2.waiver |   2 +-
 .../lowrisc_ip/ip/prim/lint/prim_xor2.waiver  |   2 +-
 .../ip/prim/lint/prim_xoshiro256pp.vlt        |   2 +-
 .../ip/prim/pre_dv/prim_crc32/expected_out.py |   2 +-
 .../prim/pre_dv/prim_crc32/prim_crc32_sim.cc  |   2 +-
 .../pre_dv/prim_crc32/prim_crc32_sim.core     |   2 +-
 .../prim/pre_dv/prim_crc32/prim_crc32_sim.sv  |   2 +-
 .../ip/prim/pre_dv/prim_crc32/run_predv.sh    |   2 +-
 .../prim_flop_2sync/prim_flop_2sync_sim.core  |   2 +-
 .../prim_flop_2sync_sim_cfg.hjson             |   2 +-
 .../ip/prim/pre_dv/prim_flop_2sync/tb.sv      |   2 +-
 .../cpp/prim_sync_reqack_tb.cc                |   2 +-
 .../prim_sync_reqack/prim_sync_reqack_tb.core |   2 +-
 .../rtl/prim_sync_reqack_tb.sv                |   2 +-
 .../prim_trivium/cpp/prim_trivium_tb.cc       |   2 +-
 .../pre_dv/prim_trivium/prim_trivium_tb.core  |   2 +-
 .../prim_trivium/rtl/prim_trivium_tb.sv       |  50 +-
 vendor/lowrisc_ip/ip/prim/prim.core           |   3 +-
 vendor/lowrisc_ip/ip/prim/prim_alert.core     |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_and2.core      |   3 +-
 vendor/lowrisc_ip/ip/prim/prim_arbiter.core   |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_assert.core    |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_blanker.core   |   6 +-
 vendor/lowrisc_ip/ip/prim/prim_buf.core       |   3 +-
 .../ip/prim/prim_cdc_rand_delay.core          |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_cipher.core    |   2 +-
 .../lowrisc_ip/ip/prim/prim_cipher_pkg.core   |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_clock_buf.core |   4 +-
 vendor/lowrisc_ip/ip/prim/prim_clock_div.core |   4 +-
 .../lowrisc_ip/ip/prim/prim_clock_gating.core |   4 +-
 .../ip/prim/prim_clock_gp_mux2.core           |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_clock_inv.core |   4 +-
 .../lowrisc_ip/ip/prim/prim_clock_meas.core   |   2 +-
 .../lowrisc_ip/ip/prim/prim_clock_mux2.core   |   4 +-
 vendor/lowrisc_ip/ip/prim/prim_count.core     |   3 +-
 vendor/lowrisc_ip/ip/prim/prim_crc32.core     |   2 +-
 .../lowrisc_ip/ip/prim/prim_diff_decode.core  |   3 +-
 .../ip/prim/prim_dom_and_2share.core          |   4 +-
 .../lowrisc_ip/ip/prim/prim_double_lfsr.core  |   2 +-
 .../ip/prim/prim_edge_detector.core           |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_edn_req.core   |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_esc.core       |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_fifo.core      |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_flash.core     |   4 +-
 vendor/lowrisc_ip/ip/prim/prim_flop.core      |   3 +-
 .../lowrisc_ip/ip/prim/prim_flop_2sync.core   |   3 +-
 vendor/lowrisc_ip/ip/prim/prim_flop_en.core   |   3 +-
 vendor/lowrisc_ip/ip/prim/prim_gf_mult.core   |   2 +-
 .../ip/prim/prim_lc_and_hardened.core         |   7 +-
 .../lowrisc_ip/ip/prim/prim_lc_combine.core   |   7 +-
 vendor/lowrisc_ip/ip/prim/prim_lc_dec.core    |   7 +-
 .../ip/prim/prim_lc_or_hardened.core          |   7 +-
 vendor/lowrisc_ip/ip/prim/prim_lc_sender.core |   4 +-
 vendor/lowrisc_ip/ip/prim/prim_lc_sync.core   |   5 +-
 vendor/lowrisc_ip/ip/prim/prim_lfsr.core      |   4 +-
 vendor/lowrisc_ip/ip/prim/prim_macros.core    |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_max_tree.core  |   5 +-
 .../lowrisc_ip/ip/prim/prim_msb_extend.core   |   3 +-
 vendor/lowrisc_ip/ip/prim/prim_mubi.core      |  16 +-
 .../ip/prim/prim_multibit_sync.core           |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_onehot.core    |   2 +-
 .../lowrisc_ip/ip/prim/prim_onehot_check.core |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_otp.core       |   4 +-
 vendor/lowrisc_ip/ip/prim/prim_otp_pkg.core   |   6 +-
 vendor/lowrisc_ip/ip/prim/prim_pad_attr.core  |   4 +-
 .../lowrisc_ip/ip/prim/prim_pad_wrapper.core  |   3 +-
 .../ip/prim/prim_pad_wrapper_pkg.core         |   6 +-
 vendor/lowrisc_ip/ip/prim/prim_pkg.core       |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_ram_1p.core    |   4 +-
 .../lowrisc_ip/ip/prim/prim_ram_1p_adv.core   |   4 +-
 .../lowrisc_ip/ip/prim/prim_ram_1p_pkg.core   |   3 +-
 .../lowrisc_ip/ip/prim/prim_ram_1p_scr.core   |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_ram_1r1w.core  |  48 ++
 .../lowrisc_ip/ip/prim/prim_ram_1r1w_adv.core |  19 +
 .../ip/prim/prim_ram_1r1w_async_adv.core      |  22 +
 vendor/lowrisc_ip/ip/prim/prim_ram_2p.core    |   4 +-
 .../lowrisc_ip/ip/prim/prim_ram_2p_adv.core   |   2 +-
 .../ip/prim/prim_ram_2p_async_adv.core        |   2 +-
 .../lowrisc_ip/ip/prim/prim_ram_2p_pkg.core   |   3 +-
 .../lowrisc_ip/ip/prim/prim_reg_we_check.core |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_rom.core       |   4 +-
 vendor/lowrisc_ip/ip/prim/prim_rom_adv.core   |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_rom_pkg.core   |   3 +-
 vendor/lowrisc_ip/ip/prim/prim_rst_sync.core  |   3 +-
 .../lowrisc_ip/ip/prim/prim_sec_anchor.core   |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_secded.core    |   5 +-
 vendor/lowrisc_ip/ip/prim/prim_sha2.core      |  46 ++
 vendor/lowrisc_ip/ip/prim/prim_sha2_pkg.core  |  38 ++
 .../lowrisc_ip/ip/prim/prim_sparse_fsm.core   |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_subreg.core    |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_sum_tree.core  |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_trivium.core   |   2 +-
 .../lowrisc_ip/ip/prim/prim_usb_diff_rx.core  |   3 +-
 vendor/lowrisc_ip/ip/prim/prim_util.core      |   2 +-
 .../prim/prim_util_get_scramble_params.core   |   2 +-
 .../lowrisc_ip/ip/prim/prim_util_memload.core |   2 +-
 vendor/lowrisc_ip/ip/prim/prim_xnor2.core     |   3 +-
 vendor/lowrisc_ip/ip/prim/prim_xor2.core      |   3 +-
 .../lowrisc_ip/ip/prim/prim_xoshiro256pp.core |   4 +-
 vendor/lowrisc_ip/ip/prim/primgen.core        |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_alert_pkg.sv  |   2 +-
 .../ip/prim/rtl/prim_alert_receiver.sv        |  12 +-
 .../ip/prim/rtl/prim_alert_sender.sv          |   2 +-
 .../ip/prim/rtl/prim_arbiter_fixed.sv         |   2 +-
 .../ip/prim/rtl/prim_arbiter_ppc.sv           |   4 +-
 .../ip/prim/rtl/prim_arbiter_tree.sv          |   2 +-
 .../ip/prim/rtl/prim_arbiter_tree_dup.sv      |   4 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv  |   2 +-
 .../ip/prim/rtl/prim_assert_dummy_macros.svh  |   2 +-
 .../ip/prim/rtl/prim_assert_sec_cm.svh        |  99 ++--
 .../prim/rtl/prim_assert_standard_macros.svh  |   6 +-
 .../ip/prim/rtl/prim_assert_yosys_macros.svh  |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_blanker.sv |   2 +-
 .../ip/prim/rtl/prim_cdc_rand_delay.sv        |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_cipher_pkg.sv |   2 +-
 .../ip/prim/rtl/prim_clock_gating_sync.sv     |   2 +-
 .../ip/prim/rtl/prim_clock_gp_mux2.sv         |   4 +-
 .../lowrisc_ip/ip/prim/rtl/prim_clock_meas.sv |   2 +-
 .../ip/prim/rtl/prim_clock_timeout.sv         |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_count.sv   | 235 ++++----
 .../lowrisc_ip/ip/prim/rtl/prim_count_pkg.sv  |  15 +
 vendor/lowrisc_ip/ip/prim/rtl/prim_crc32.sv   |   2 +-
 .../ip/prim/rtl/prim_diff_decode.sv           |  14 +-
 .../ip/prim/rtl/prim_dom_and_2share.sv        |   2 +-
 .../ip/prim/rtl/prim_double_lfsr.sv           |   2 +-
 .../ip/prim/rtl/prim_edge_detector.sv         |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_edn_req.sv |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_esc_pkg.sv |   2 +-
 .../ip/prim/rtl/prim_esc_receiver.sv          |  12 +-
 .../lowrisc_ip/ip/prim/rtl/prim_esc_sender.sv |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_fifo_async.sv |   2 +-
 .../ip/prim/rtl/prim_fifo_async_simple.sv     |   2 +-
 .../prim/rtl/prim_fifo_async_sram_adapter.sv  |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_fifo_sync.sv  |  80 +--
 .../ip/prim/rtl/prim_fifo_sync_cnt.sv         | 115 ++--
 vendor/lowrisc_ip/ip/prim/rtl/prim_filter.sv  |   3 +-
 .../lowrisc_ip/ip/prim/rtl/prim_filter_ctr.sv |   3 +-
 .../lowrisc_ip/ip/prim/rtl/prim_flop_2sync.sv |   2 +-
 .../ip/prim/rtl/prim_flop_macros.sv           |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_gate_gen.sv   |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_gf_mult.sv |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_intr_hw.sv |  51 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_keccak.sv  |   3 +-
 .../ip/prim/rtl/prim_lc_and_hardened.sv       |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_lc_combine.sv |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_lc_dec.sv  |   2 +-
 .../ip/prim/rtl/prim_lc_or_hardened.sv        |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_lc_sender.sv  |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_lc_sync.sv |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv    |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_macros.svh |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_max_tree.sv   |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_msb_extend.sv |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_mubi12_dec.sv |   2 +-
 .../ip/prim/rtl/prim_mubi12_sender.sv         |   2 +-
 .../ip/prim/rtl/prim_mubi12_sync.sv           |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_mubi16_dec.sv |   2 +-
 .../ip/prim/rtl/prim_mubi16_sender.sv         |   2 +-
 .../ip/prim/rtl/prim_mubi16_sync.sv           |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_mubi20_dec.sv |  48 ++
 .../ip/prim/rtl/prim_mubi20_sender.sv         |  94 ++++
 .../ip/prim/rtl/prim_mubi20_sync.sv           | 178 ++++++
 .../lowrisc_ip/ip/prim/rtl/prim_mubi24_dec.sv |  48 ++
 .../ip/prim/rtl/prim_mubi24_sender.sv         |  94 ++++
 .../ip/prim/rtl/prim_mubi24_sync.sv           | 178 ++++++
 .../lowrisc_ip/ip/prim/rtl/prim_mubi28_dec.sv |  48 ++
 .../ip/prim/rtl/prim_mubi28_sender.sv         |  94 ++++
 .../ip/prim/rtl/prim_mubi28_sync.sv           | 178 ++++++
 .../lowrisc_ip/ip/prim/rtl/prim_mubi32_dec.sv |  48 ++
 .../ip/prim/rtl/prim_mubi32_sender.sv         |  94 ++++
 .../ip/prim/rtl/prim_mubi32_sync.sv           | 178 ++++++
 .../lowrisc_ip/ip/prim/rtl/prim_mubi4_dec.sv  |   2 +-
 .../ip/prim/rtl/prim_mubi4_sender.sv          |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_mubi4_sync.sv |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_mubi8_dec.sv  |   2 +-
 .../ip/prim/rtl/prim_mubi8_sender.sv          |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_mubi8_sync.sv |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_mubi_pkg.sv   | 530 +++++++++++++++++-
 .../ip/prim/rtl/prim_multibit_sync.sv         |   2 +-
 .../ip/prim/rtl/prim_onehot_check.sv          |  31 +-
 .../lowrisc_ip/ip/prim/rtl/prim_onehot_enc.sv |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_onehot_mux.sv |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_otp_pkg.sv |  34 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_packer.sv  |  19 +-
 .../ip/prim/rtl/prim_packer_fifo.sv           |   9 +-
 .../ip/prim/rtl/prim_pad_wrapper_pkg.sv       |   3 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_present.sv |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_prince.sv  |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_pulse_sync.sv |   5 +-
 .../lowrisc_ip/ip/prim/rtl/prim_ram_1p_adv.sv | 147 ++++-
 .../lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_ram_1p_scr.sv | 173 ++++--
 .../ip/prim/rtl/prim_ram_1r1w_adv.sv          |  83 +++
 .../ip/prim/rtl/prim_ram_1r1w_async_adv.sv    | 264 +++++++++
 .../lowrisc_ip/ip/prim/rtl/prim_ram_2p_adv.sv |   2 +-
 .../ip/prim/rtl/prim_ram_2p_async_adv.sv      |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_ram_2p_pkg.sv |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_reg_cdc.sv |  21 +-
 .../ip/prim/rtl/prim_reg_cdc_arb.sv           |   5 +-
 .../ip/prim/rtl/prim_reg_we_check.sv          |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_rom_adv.sv |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_rom_pkg.sv |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_rst_sync.sv   |   2 +-
 .../ip/prim/rtl/prim_sec_anchor_buf.sv        |   2 +-
 .../ip/prim/rtl/prim_sec_anchor_flop.sv       |   2 +-
 .../ip/prim/rtl/prim_secded_22_16_dec.sv      |   2 +-
 .../ip/prim/rtl/prim_secded_22_16_enc.sv      |   2 +-
 .../ip/prim/rtl/prim_secded_28_22_dec.sv      |   2 +-
 .../ip/prim/rtl/prim_secded_28_22_enc.sv      |   2 +-
 .../ip/prim/rtl/prim_secded_39_32_dec.sv      |   2 +-
 .../ip/prim/rtl/prim_secded_39_32_enc.sv      |   2 +-
 .../ip/prim/rtl/prim_secded_64_57_dec.sv      |   2 +-
 .../ip/prim/rtl/prim_secded_64_57_enc.sv      |   2 +-
 .../ip/prim/rtl/prim_secded_72_64_dec.sv      |   2 +-
 .../ip/prim/rtl/prim_secded_72_64_enc.sv      |   2 +-
 .../prim/rtl/prim_secded_hamming_22_16_dec.sv |   2 +-
 .../prim/rtl/prim_secded_hamming_22_16_enc.sv |   2 +-
 .../prim/rtl/prim_secded_hamming_39_32_dec.sv |   2 +-
 .../prim/rtl/prim_secded_hamming_39_32_enc.sv |   2 +-
 .../prim/rtl/prim_secded_hamming_72_64_dec.sv |   2 +-
 .../prim/rtl/prim_secded_hamming_72_64_enc.sv |   2 +-
 .../prim/rtl/prim_secded_hamming_76_68_dec.sv |   2 +-
 .../prim/rtl/prim_secded_hamming_76_68_enc.sv |   2 +-
 .../ip/prim/rtl/prim_secded_inv_22_16_dec.sv  |   2 +-
 .../ip/prim/rtl/prim_secded_inv_22_16_enc.sv  |   2 +-
 .../ip/prim/rtl/prim_secded_inv_28_22_dec.sv  |   2 +-
 .../ip/prim/rtl/prim_secded_inv_28_22_enc.sv  |   2 +-
 .../ip/prim/rtl/prim_secded_inv_39_32_dec.sv  |   2 +-
 .../ip/prim/rtl/prim_secded_inv_39_32_enc.sv  |   2 +-
 .../ip/prim/rtl/prim_secded_inv_64_57_dec.sv  |   2 +-
 .../ip/prim/rtl/prim_secded_inv_64_57_enc.sv  |   2 +-
 .../ip/prim/rtl/prim_secded_inv_72_64_dec.sv  |   2 +-
 .../ip/prim/rtl/prim_secded_inv_72_64_enc.sv  |   2 +-
 .../rtl/prim_secded_inv_hamming_22_16_dec.sv  |   2 +-
 .../rtl/prim_secded_inv_hamming_22_16_enc.sv  |   2 +-
 .../rtl/prim_secded_inv_hamming_39_32_dec.sv  |   2 +-
 .../rtl/prim_secded_inv_hamming_39_32_enc.sv  |   2 +-
 .../rtl/prim_secded_inv_hamming_72_64_dec.sv  |   2 +-
 .../rtl/prim_secded_inv_hamming_72_64_enc.sv  |   2 +-
 .../rtl/prim_secded_inv_hamming_76_68_dec.sv  |   2 +-
 .../rtl/prim_secded_inv_hamming_76_68_enc.sv  |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_sha2.sv    | 487 ++++++++++++++++
 vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_32.sv | 267 +++++++++
 .../lowrisc_ip/ip/prim/rtl/prim_sha2_pad.sv   | 380 +++++++++++++
 .../lowrisc_ip/ip/prim/rtl/prim_sha2_pkg.sv   | 250 +++++++++
 vendor/lowrisc_ip/ip/prim/rtl/prim_slicer.sv  |   3 +-
 .../ip/prim/rtl/prim_sparse_fsm_flop.sv       |   2 +-
 .../ip/prim/rtl/prim_sram_arbiter.sv          |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_subreg.sv  |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_subreg_arb.sv |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_subreg_ext.sv |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_subreg_pkg.sv |   2 +-
 .../ip/prim/rtl/prim_subreg_shadow.sv         |   4 +-
 .../lowrisc_ip/ip/prim/rtl/prim_subst_perm.sv |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_sum_tree.sv   |   2 +-
 .../ip/prim/rtl/prim_sync_reqack.sv           |   6 +-
 .../ip/prim/rtl/prim_sync_reqack_data.sv      |   2 +-
 .../ip/prim/rtl/prim_sync_slow_fast.sv        |   2 +-
 vendor/lowrisc_ip/ip/prim/rtl/prim_trivium.sv |  36 +-
 .../ip/prim/rtl/prim_trivium_pkg.sv           |   8 +-
 .../rtl/prim_util_get_scramble_params.svh     |   2 +-
 .../ip/prim/rtl/prim_util_memload.svh         |   2 +-
 .../lowrisc_ip/ip/prim/rtl/prim_util_pkg.sv   |   2 +-
 .../ip/prim/rtl/prim_xoshiro256pp.sv          |   2 +-
 .../ip/prim/util/prim_crc32_table_gen.py      |   2 +-
 vendor/lowrisc_ip/ip/prim/util/primgen.py     |   2 +-
 .../ip/prim/util/primgen/abstract_prim.sv.tpl |   4 +-
 .../ip/prim/util/primgen/prim_pkg.core.tpl    |   2 +-
 .../ip/prim/util/primgen/prim_pkg.sv.tpl      |   2 +-
 ...oogle_verible_verilog_syntax_py.lock.hjson |   2 +-
 ...gle_verible_verilog_syntax_py.vendor.hjson |   2 +-
 vendor/lowrisc_ip/ip/prim_generic/BUILD       |   2 +-
 .../lint/prim_generic_clock_buf.vlt           |   2 +-
 .../lint/prim_generic_clock_buf.waiver        |   2 +-
 .../lint/prim_generic_clock_div.waiver        |   2 +-
 .../lint/prim_generic_clock_gating.vlt        |   2 +-
 .../lint/prim_generic_clock_gating.waiver     |   2 +-
 .../lint/prim_generic_clock_mux2.vlt          |   2 +-
 .../lint/prim_generic_clock_mux2.waiver       |   2 +-
 .../prim_generic/lint/prim_generic_flash.vlt  |   2 +-
 .../lint/prim_generic_flash.waiver            |   2 +-
 .../ip/prim_generic/lint/prim_generic_otp.vlt |   2 +-
 .../prim_generic/lint/prim_generic_otp.waiver |   2 +-
 .../lint/prim_generic_pad_wrapper.vlt         |   2 +-
 .../lint/prim_generic_pad_wrapper.waiver      |   2 +-
 .../prim_generic/lint/prim_generic_ram_1p.vlt |   2 +-
 .../lint/prim_generic_ram_1p.waiver           |   6 +-
 .../lint/prim_generic_ram_1r1w.vlt            |   6 +
 .../lint/prim_generic_ram_1r1w.waiver         |  12 +
 .../prim_generic/lint/prim_generic_ram_2p.vlt |   2 +-
 .../lint/prim_generic_ram_2p.waiver           |   8 +-
 .../ip/prim_generic/lint/prim_generic_rom.vlt |   2 +-
 .../prim_generic/lint/prim_generic_rom.waiver |   3 +-
 .../lint/prim_generic_usb_diff_rx.waiver      |   2 +-
 .../ip/prim_generic/prim_generic_and2.core    |   6 +-
 .../ip/prim_generic/prim_generic_buf.core     |   6 +-
 .../prim_generic/prim_generic_clock_buf.core  |   2 +-
 .../prim_generic/prim_generic_clock_div.core  |   2 +-
 .../prim_generic_clock_gating.core            |   2 +-
 .../prim_generic/prim_generic_clock_inv.core  |   8 +-
 .../prim_generic/prim_generic_clock_mux2.core |   2 +-
 .../ip/prim_generic/prim_generic_flash.core   |   4 +-
 .../ip/prim_generic/prim_generic_flop.core    |   6 +-
 .../ip/prim_generic/prim_generic_flop_en.core |   6 +-
 .../ip/prim_generic/prim_generic_otp.core     |   5 +-
 .../prim_generic/prim_generic_pad_attr.core   |   8 +-
 .../prim_generic_pad_wrapper.core             |   2 +-
 .../ip/prim_generic/prim_generic_ram_1p.core  |   2 +-
 .../prim_generic/prim_generic_ram_1r1w.core   |  45 ++
 .../ip/prim_generic/prim_generic_ram_2p.core  |   2 +-
 .../ip/prim_generic/prim_generic_rom.core     |   2 +-
 .../prim_generic_usb_diff_rx.core             |   5 +-
 .../ip/prim_generic/prim_generic_xnor2.core   |   6 +-
 .../ip/prim_generic/prim_generic_xor2.core    |   6 +-
 .../ip/prim_generic/rtl/prim_generic_and2.sv  |   2 +-
 .../ip/prim_generic/rtl/prim_generic_buf.sv   |   2 +-
 .../rtl/prim_generic_clock_buf.sv             |   2 +-
 .../rtl/prim_generic_clock_div.sv             |   7 +-
 .../rtl/prim_generic_clock_gating.sv          |   2 +-
 .../rtl/prim_generic_clock_inv.sv             |   2 +-
 .../rtl/prim_generic_clock_mux2.sv            |   2 +-
 .../ip/prim_generic/rtl/prim_generic_flash.sv |  11 +-
 .../rtl/prim_generic_flash_bank.sv            |   2 +-
 .../ip/prim_generic/rtl/prim_generic_flop.sv  |   2 +-
 .../prim_generic/rtl/prim_generic_flop_en.sv  |   2 +-
 .../ip/prim_generic/rtl/prim_generic_otp.sv   |  63 ++-
 .../prim_generic/rtl/prim_generic_pad_attr.sv |   9 +-
 .../rtl/prim_generic_pad_wrapper.sv           |  23 +-
 .../prim_generic/rtl/prim_generic_ram_1p.sv   |   2 +-
 .../prim_generic/rtl/prim_generic_ram_1r1w.sv |  84 +++
 .../prim_generic/rtl/prim_generic_ram_2p.sv   |   2 +-
 .../ip/prim_generic/rtl/prim_generic_rom.sv   |   2 +-
 .../rtl/prim_generic_usb_diff_rx.sv           |   2 +-
 .../ip/prim_generic/rtl/prim_generic_xnor2.sv |   2 +-
 .../ip/prim_generic/rtl/prim_generic_xor2.sv  |   2 +-
 vendor/lowrisc_ip/ip/prim_xilinx/BUILD        |   2 +-
 .../lint/prim_xilinx_clock_buf.vlt            |   2 +-
 .../lint/prim_xilinx_clock_buf.waiver         |   2 +-
 .../lint/prim_xilinx_clock_gating.vlt         |   2 +-
 .../lint/prim_xilinx_clock_gating.waiver      |   2 +-
 .../lint/prim_xilinx_clock_mux2.vlt           |   2 +-
 .../lint/prim_xilinx_clock_mux2.waiver        |   2 +-
 .../lint/prim_xilinx_pad_wrapper.vlt          |   2 +-
 .../lint/prim_xilinx_pad_wrapper.waiver       |   2 +-
 .../ip/prim_xilinx/prim_xilinx_and2.core      |   4 +-
 .../ip/prim_xilinx/prim_xilinx_buf.core       |   2 +-
 .../ip/prim_xilinx/prim_xilinx_clock_buf.core |   2 +-
 .../prim_xilinx/prim_xilinx_clock_gating.core |   2 +-
 .../prim_xilinx/prim_xilinx_clock_mux2.core   |   2 +-
 .../ip/prim_xilinx/prim_xilinx_flop.core      |   6 +-
 .../ip/prim_xilinx/prim_xilinx_flop_en.core   |   6 +-
 .../ip/prim_xilinx/prim_xilinx_pad_attr.core  |   8 +-
 .../prim_xilinx/prim_xilinx_pad_wrapper.core  |   2 +-
 .../ip/prim_xilinx/prim_xilinx_xor2.core      |   6 +-
 .../ip/prim_xilinx/rtl/prim_xilinx_and2.sv    |   2 +-
 .../ip/prim_xilinx/rtl/prim_xilinx_buf.sv     |   2 +-
 .../prim_xilinx/rtl/prim_xilinx_clock_buf.sv  |   2 +-
 .../rtl/prim_xilinx_clock_gating.sv           |   2 +-
 .../prim_xilinx/rtl/prim_xilinx_clock_mux2.sv |   2 +-
 .../ip/prim_xilinx/rtl/prim_xilinx_flop.sv    |   2 +-
 .../ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv |   2 +-
 .../prim_xilinx/rtl/prim_xilinx_pad_attr.sv   |   9 +-
 .../rtl/prim_xilinx_pad_wrapper.sv            |  47 +-
 .../ip/prim_xilinx/rtl/prim_xilinx_xor2.sv    |   2 +-
 vendor/lowrisc_ip/lint/common.core            |   2 +-
 vendor/lowrisc_ip/lint/comportable.core       |   4 +-
 .../tools/ascentlint/ascentlint-config.tcl    |   5 +-
 .../lint/tools/ascentlint/common.waiver       |   4 +-
 .../lint/tools/ascentlint/comportable.waiver  |   2 +-
 .../lint/tools/dvsim/ascentlint.hjson         |   2 +-
 .../lint/tools/dvsim/common_lint_cfg.hjson    |   5 +-
 vendor/lowrisc_ip/lint/tools/dvsim/lint.mk    |   2 +-
 .../lint/tools/dvsim/veriblelint.hjson        |   2 +-
 .../lint/tools/dvsim/verilator.hjson          |   2 +-
 .../lowrisc-styleguide.rules.verible_lint     |   2 +-
 .../lint/tools/verilator/common.vlt           |   2 +-
 .../lint/tools/verilator/comportable.vlt      |   3 +-
 595 files changed, 5471 insertions(+), 1259 deletions(-)
 delete mode 100644 vendor/lowrisc_ip/ip/prim/fpv/prim_count_expected_failure.hjson
 create mode 100644 vendor/lowrisc_ip/ip/prim/lint/prim_ram_1r1w.waiver
 create mode 100644 vendor/lowrisc_ip/ip/prim/lint/prim_sha2.vbl
 create mode 100644 vendor/lowrisc_ip/ip/prim/lint/prim_sha2.vlt
 create mode 100644 vendor/lowrisc_ip/ip/prim/lint/prim_sha2.waiver
 create mode 100644 vendor/lowrisc_ip/ip/prim/prim_ram_1r1w.core
 create mode 100644 vendor/lowrisc_ip/ip/prim/prim_ram_1r1w_adv.core
 create mode 100644 vendor/lowrisc_ip/ip/prim/prim_ram_1r1w_async_adv.core
 create mode 100644 vendor/lowrisc_ip/ip/prim/prim_sha2.core
 create mode 100644 vendor/lowrisc_ip/ip/prim/prim_sha2_pkg.core
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_count_pkg.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_mubi20_dec.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_mubi20_sender.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_mubi20_sync.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_mubi24_dec.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_mubi24_sender.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_mubi24_sync.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_mubi28_dec.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_mubi28_sender.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_mubi28_sync.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_mubi32_dec.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_mubi32_sender.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_mubi32_sync.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1r1w_adv.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1r1w_async_adv.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_sha2.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_32.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_pad.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_pkg.sv
 create mode 100644 vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1r1w.vlt
 create mode 100644 vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver
 create mode 100644 vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_1r1w.core
 create mode 100644 vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv

diff --git a/vendor/lowrisc_ip.lock.hjson b/vendor/lowrisc_ip.lock.hjson
index a730714b..a71602ae 100644
--- a/vendor/lowrisc_ip.lock.hjson
+++ b/vendor/lowrisc_ip.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/lowRISC/opentitan
-    rev: 042415198f3dc6b3bc387c669c7e9cf982d208e2
+    rev: d268f271f4f75aeb8f3bf9624a497ae5bfb9c47e
   }
 }
diff --git a/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.c b/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.c
index 6e8fa3f2..1c9ebf32 100644
--- a/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.c
+++ b/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.c
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.core b/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.core
index b11fd3c2..b17d31bc 100644
--- a/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.core
+++ b/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv_dpi_c:uartdpi:0.1"
diff --git a/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.h b/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.h
index e7b4b610..63834078 100644
--- a/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.h
+++ b/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.sv b/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.sv
index 3018e657..d476c519 100644
--- a/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.sv
+++ b/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi_sv.core b/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi_sv.core
index 9e33cb29..59a00d83 100644
--- a/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi_sv.core
+++ b/vendor/lowrisc_ip/dv/dpi/uartdpi/uartdpi_sv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv_dpi_sv:uartdpi:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/BUILD b/vendor/lowrisc_ip/ip/prim/BUILD
index c87fb863..f42854cd 100644
--- a/vendor/lowrisc_ip/ip/prim/BUILD
+++ b/vendor/lowrisc_ip/ip/prim/BUILD
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/doc/prim_ram_1p_scr.md b/vendor/lowrisc_ip/ip/prim/doc/prim_ram_1p_scr.md
index ffdaebcd..ad67d18f 100644
--- a/vendor/lowrisc_ip/ip/prim/doc/prim_ram_1p_scr.md
+++ b/vendor/lowrisc_ip/ip/prim/doc/prim_ram_1p_scr.md
@@ -2,9 +2,9 @@
 
 # Overview
 
-The scrambling primitive `prim_ram_1p_scr` employs a reduced-round (5 instead of 11) PRINCE block cipher in CTR mode to scramble the data.
+The scrambling primitive `prim_ram_1p_scr` employs a reduced-round (7 instead of 11) PRINCE block cipher in CTR mode to scramble the data.
 The PRINCE lightweight block cipher has been selected due to its low latency and low area characteristics, see also [prim_prince](./prim_prince.md) for more information on PRINCE.
-The number of rounds is reduced to 5 in order to ease timing pressure and ensure single cycle operation (the number of rounds can always be increased if it turns out that there is enough timing slack).
+The number of rounds is reduced to 7 in order to ease timing pressure and ensure single cycle operation (the number of rounds can always be increased if it turns out that there is enough timing slack).
 
 In [CTR mode](https://en.wikipedia.org/wiki/Block_cipher_mode_of_operation#Counter_(CTR)), the block cipher is used to encrypt a 64bit IV with the scrambling key in order to create a 64bit keystream block that is bitwise XOR'ed with the data in order to transform plaintext into ciphertext and vice versa.
 The IV is assembled by concatenating a nonce with the word address.
@@ -13,13 +13,16 @@ If the word width of the scrambled memory is smaller than 64bit, the keystream b
 If the word width is wider than 64bit, the scrambling primitive by default instantiates multiple PRINCE primitives in order to create a unique keystream for the full datawidth.
 For area constrained settings, the parameter `ReplicateKeyStream` in `prim_ram_1p_scr` can be set to 1 in order to replicate the keystream block generated by one single primitive instead of using multiple parallel PRINCE instances (but it should be understood that this lowers the level of security).
 
-Since plain CTR mode does not diffuse the data bits due to the bitwise XOR, the scheme is augmented by passing each individual word through a two-layer substitution-permutation (S&P) network implemented with the `prim_subst_perm` primitive (the diffusion chunk width can be parameterized via the `DiffWidth` parameter).
-The S&P network employed is similar to the one employed in PRESENT and will be explained in more detail [further below](#custom-substitution-permutation-network).
-Note that if individual bytes need to be writable without having to perform a read-modify-write operation, the diffusion chunk width should be set to 8.
+In order to break the linear address space, the CTR mode is augmented with an S&P network to non-linearly remap the SRAM address as shown in the block diagram above.
+The S&P network employed is similar to the one employed in PRESENT and is explained in more detail [further below](#custom-substitution-permutation-network).
+This particular address scrambling network additionally XOR's in a nonce that has the same width as the address.
 
-Another CTR mode augmentation that is aimed at breaking the linear address space is SRAM address scrambling.
-The same two-layer S&P network that is used for byte diffusion is leveraged to non-linearly remap the SRAM address as shown in the block diagram above.
-As opposed to the byte diffusion S&P networks, this particular address scrambling network additionally XOR's in a nonce that has the same width as the address.
+Optionally, the scheme can be augmented by passing each individual data word through a substitution-permutation (S&P) network implemented with the `prim_subst_perm` primitive to diffuse the data bits.
+The number of diffusion rounds and the diffusion chunk width can be parameterized via the `NumDiffRounds` and the `DiffWidth` parameter, respectively.
+The same S&P network that is used for address scrambling is leveraged for the data diffusion.
+For details, see [below](#custom-substitution-permutation-network).
+If individual bytes need to be writable without having to perform a read-modify-write operation, the diffusion chunk width should be set to 8.
+Note that since this optional data diffusion can affect end-to-end bus and memory integrity schemes, it is disabled by default.
 
 ## Parameters
 
@@ -33,8 +36,8 @@ Parameter                   | Default (Max)         | Top Earlgrey | Description
 `DataBitsPerMask`           | 8                     | 8            | Number of data bits per write mask.
 `EnableParity`              | 1                     | 1            | This parameter enables byte parity.
 `CfgWidth`                  | 8                     | 8            | Width of SRAM attributes field.
-`NumPrinceRoundsHalf`       | 2 (5)                 | 2            | Number of PRINCE half-rounds.
-`NumDiffRounds`             | 2                     | 2            | Number of additional diffusion rounds, set to 0 to disable.
+`NumPrinceRoundsHalf`       | 3 (5)                 | 3            | Number of PRINCE half-rounds.
+`NumDiffRounds`             | 0                     | 0            | Number of additional diffusion rounds, set to 0 to disable.
 `DiffWidth`                 | 8                     | 8            | Width of additional diffusion rounds, set to 8 for intra-byte diffusion.
 `NumAddrScrRounds`          | 2                     | 2            | Number of address scrambling rounds, set to 0 to disable.
 `ReplicateKeyStream`        | 0 (1)                 | 0            | If set to 1, the same 64bit key stream is replicated if the data port is wider than 64bit. Otherwise, multiple PRINCE primitives are employed to generate a unique keystream for the full data width.
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_alert/data/prim_alert_cover.cfg b/vendor/lowrisc_ip/ip/prim/dv/prim_alert/data/prim_alert_cover.cfg
index 597ed647..8d2b8962 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_alert/data/prim_alert_cover.cfg
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_alert/data/prim_alert_cover.cfg
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_alert/data/prim_alert_testplan.hjson b/vendor/lowrisc_ip/ip/prim/dv/prim_alert/data/prim_alert_testplan.hjson
index c0441715..e55ac1d4 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_alert/data/prim_alert_testplan.hjson
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_alert/data/prim_alert_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_alert/prim_alert_sim.core b/vendor/lowrisc_ip/ip/prim/dv/prim_alert/prim_alert_sim.core
index 19676375..b9dcc28e 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_alert/prim_alert_sim.core
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_alert/prim_alert_sim.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:prim_alert_sim:0.1"
@@ -29,4 +29,3 @@ targets:
 
   lint:
     <<: *sim_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_alert/prim_alert_sim_cfg.hjson b/vendor/lowrisc_ip/ip/prim/dv/prim_alert/prim_alert_sim_cfg.hjson
index b36d23b7..a3154db0 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_alert/prim_alert_sim_cfg.hjson
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_alert/prim_alert_sim_cfg.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_alert/tb/prim_alert_tb.sv b/vendor/lowrisc_ip/ip/prim/dv/prim_alert/tb/prim_alert_tb.sv
index 228ecd20..4f45cd2d 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_alert/tb/prim_alert_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_alert/tb/prim_alert_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_esc/data/prim_esc_cover.cfg b/vendor/lowrisc_ip/ip/prim/dv/prim_esc/data/prim_esc_cover.cfg
index 38463867..0ebe0b10 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_esc/data/prim_esc_cover.cfg
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_esc/data/prim_esc_cover.cfg
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_esc/data/prim_esc_testplan.hjson b/vendor/lowrisc_ip/ip/prim/dv/prim_esc/data/prim_esc_testplan.hjson
index 4a2a5ebc..29c3137f 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_esc/data/prim_esc_testplan.hjson
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_esc/data/prim_esc_testplan.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_esc/prim_esc_sim.core b/vendor/lowrisc_ip/ip/prim/dv/prim_esc/prim_esc_sim.core
index ef00ab6f..2216ff03 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_esc/prim_esc_sim.core
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_esc/prim_esc_sim.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:prim_esc_sim:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_esc/prim_esc_sim_cfg.hjson b/vendor/lowrisc_ip/ip/prim/dv/prim_esc/prim_esc_sim_cfg.hjson
index 6658a556..129c0446 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_esc/prim_esc_sim_cfg.hjson
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_esc/prim_esc_sim_cfg.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_esc/tb/prim_esc_tb.sv b/vendor/lowrisc_ip/ip/prim/dv/prim_esc/tb/prim_esc_tb.sv
index 592abeff..e3572df1 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_esc/tb/prim_esc_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_esc/tb/prim_esc_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/data/prim_lfsr_cov_excl.el b/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/data/prim_lfsr_cov_excl.el
index 45f15b45..10071291 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/data/prim_lfsr_cov_excl.el
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/data/prim_lfsr_cov_excl.el
@@ -1,3 +1,3 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/data/prim_lfsr_cover.cfg b/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/data/prim_lfsr_cover.cfg
index 533abbcd..5d98b184 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/data/prim_lfsr_cover.cfg
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/data/prim_lfsr_cover.cfg
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core b/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core
index ec82c167..3733ede7 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:prim_lfsr_sim:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson b/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson
index 4fb68ce8..b84ba65b 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_tb.sv b/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_tb.sv
index 98556155..d7bcc79d 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_present/crypto_dpi_present/crypto_dpi_present.cc b/vendor/lowrisc_ip/ip/prim/dv/prim_present/crypto_dpi_present/crypto_dpi_present.cc
index 782d0e18..25cfa42f 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_present/crypto_dpi_present/crypto_dpi_present.cc
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_present/crypto_dpi_present/crypto_dpi_present.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_present/crypto_dpi_present/crypto_dpi_present.core b/vendor/lowrisc_ip/ip/prim/dv/prim_present/crypto_dpi_present/crypto_dpi_present.core
index ed008555..59cf0a2f 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_present/crypto_dpi_present/crypto_dpi_present.core
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_present/crypto_dpi_present/crypto_dpi_present.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:crypto_dpi_present:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_present/crypto_dpi_present/crypto_dpi_present_pkg.sv b/vendor/lowrisc_ip/ip/prim/dv/prim_present/crypto_dpi_present/crypto_dpi_present_pkg.sv
index 2565512c..4f237dec 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_present/crypto_dpi_present/crypto_dpi_present_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_present/crypto_dpi_present/crypto_dpi_present_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_present/data/prim_present_cover.cfg b/vendor/lowrisc_ip/ip/prim/dv/prim_present/data/prim_present_cover.cfg
index 8789a92a..e2afdd87 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_present/data/prim_present_cover.cfg
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_present/data/prim_present_cover.cfg
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_present/prim_present_sim.core b/vendor/lowrisc_ip/ip/prim/dv/prim_present/prim_present_sim.core
index 5fcb3d42..0755f0a0 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_present/prim_present_sim.core
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_present/prim_present_sim.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:prim_present_sim:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_present/prim_present_sim_cfg.hjson b/vendor/lowrisc_ip/ip/prim/dv/prim_present/prim_present_sim_cfg.hjson
index 9b4b8282..64fc6286 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_present/prim_present_sim_cfg.hjson
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_present/prim_present_sim_cfg.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_present/tb/prim_present_tb.sv b/vendor/lowrisc_ip/ip/prim/dv/prim_present/tb/prim_present_tb.sv
index 4a80b183..e70ab69d 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_present/tb/prim_present_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_present/tb/prim_present_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince.c b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince.c
index fba3a5b4..833574e3 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince.c
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince.c
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince.core b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince.core
index 1ce81335..a8d14964 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince.core
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:crypto_dpi_prince:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_pkg.sv b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_pkg.sv
index 8535e988..5625cc67 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson
index 8c5b0f7c..9f2e9c6f 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_prince_ref.core b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_prince_ref.core
index 20868bc1..90728795 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_prince_ref.core
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_prince_ref.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:crypto_prince_ref:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/prince_ref.h b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/prince_ref.h
index a807869a..b1ada83e 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/prince_ref.h
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/crypto_dpi_prince/prince_ref.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Copyright 2016 Sebastien Riou
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/data/prim_prince_cover.cfg b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/data/prim_prince_cover.cfg
index 574da3b3..d61d0f01 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/data/prim_prince_cover.cfg
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/data/prim_prince_cover.cfg
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/prim_prince_sim.core b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/prim_prince_sim.core
index 38007c08..35169eb2 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/prim_prince_sim.core
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/prim_prince_sim.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:prim_prince_sim:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/prim_prince_sim_cfg.hjson b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/prim_prince_sim_cfg.hjson
index c1253abf..6b7504cd 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/prim_prince_sim_cfg.hjson
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/prim_prince_sim_cfg.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/tb/prim_prince_tb.sv b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/tb/prim_prince_tb.sv
index 4d54ba89..6a2bb7b3 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_prince/tb/prim_prince_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_prince/tb/prim_prince_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_ram_scr/cpp/scramble_model.cc b/vendor/lowrisc_ip/ip/prim/dv/prim_ram_scr/cpp/scramble_model.cc
index e8f7d7af..da3da525 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_ram_scr/cpp/scramble_model.cc
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_ram_scr/cpp/scramble_model.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -21,7 +21,7 @@ uint8_t PRESENT_SBOX4_INV[] = {0x5, 0xe, 0xf, 0x8, 0xc, 0x1, 0x2, 0xd,
 
 static const uint32_t kNumAddrSubstPermRounds = 2;
 static const uint32_t kNumDataSubstPermRounds = 2;
-static const uint32_t kNumPrinceHalfRounds = 2;
+static const uint32_t kNumPrinceHalfRounds = 3;
 
 static std::vector<uint8_t> byte_reverse_vector(
     const std::vector<uint8_t> &vec_in) {
@@ -322,7 +322,7 @@ std::vector<uint8_t> scramble_encrypt_data(
     const std::vector<uint8_t> &data_in, uint32_t data_width,
     uint32_t subst_perm_width, const std::vector<uint8_t> &addr,
     uint32_t addr_width, const std::vector<uint8_t> &nonce,
-    const std::vector<uint8_t> &key, bool repeat_keystream) {
+    const std::vector<uint8_t> &key, bool repeat_keystream, bool use_sp_layer) {
   assert(data_in.size() == ((data_width + 7) / 8));
   assert(addr.size() == ((addr_width + 7) / 8));
 
@@ -335,28 +335,32 @@ std::vector<uint8_t> scramble_encrypt_data(
 
   auto data_enc = xor_vectors(data_in, keystream);
 
-  return scramble_subst_perm_full_width(data_enc, data_width, subst_perm_width,
-                                        true);
+  if (use_sp_layer) {
+    return scramble_subst_perm_full_width(data_enc, data_width,
+                                          subst_perm_width, true);
+  } else {
+    return data_enc;
+  }
 }
 
 std::vector<uint8_t> scramble_decrypt_data(
     const std::vector<uint8_t> &data_in, uint32_t data_width,
     uint32_t subst_perm_width, const std::vector<uint8_t> &addr,
     uint32_t addr_width, const std::vector<uint8_t> &nonce,
-    const std::vector<uint8_t> &key, bool repeat_keystream) {
+    const std::vector<uint8_t> &key, bool repeat_keystream, bool use_sp_layer) {
   assert(data_in.size() == ((data_width + 7) / 8));
   assert(addr.size() == ((addr_width + 7) / 8));
 
-  // Data is decrypted by reversing substitution/permutation layer then XORing
-  // with keystream
-  auto data_sp_out = scramble_subst_perm_full_width(data_in, data_width,
-                                                    subst_perm_width, false);
-
   auto keystream =
       scramble_gen_keystream(addr, addr_width, nonce, key, data_width,
                              kNumPrinceHalfRounds, repeat_keystream);
-
-  auto data_dec = xor_vectors(data_sp_out, keystream);
-
-  return data_dec;
+  if (use_sp_layer) {
+    // Data is decrypted by reversing substitution/permutation layer then XORing
+    // with keystream
+    auto data_sp_out = scramble_subst_perm_full_width(data_in, data_width,
+                                                      subst_perm_width, false);
+    return xor_vectors(data_sp_out, keystream);
+  } else {
+    return xor_vectors(data_in, keystream);
+  }
 }
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_ram_scr/cpp/scramble_model.core b/vendor/lowrisc_ip/ip/prim/dv/prim_ram_scr/cpp/scramble_model.core
index 2ab96b8f..a7fe162a 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_ram_scr/cpp/scramble_model.core
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_ram_scr/cpp/scramble_model.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_ram_scr/cpp/scramble_model.h b/vendor/lowrisc_ip/ip/prim/dv/prim_ram_scr/cpp/scramble_model.h
index 4a3875d2..92a214fa 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_ram_scr/cpp/scramble_model.h
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_ram_scr/cpp/scramble_model.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -40,13 +40,17 @@ std::vector<uint8_t> scramble_addr(const std::vector<uint8_t> &addr_in,
  * @param repeat_keystream Repeat the keystream of one single PRINCE instance if
  *                         set to true. Otherwise multiple PRINCE instances are
  *                         used.
+ * @param use_sp_layer     Use the S&P layer for data diffusion. In HW this is
+ *                         disabled by default since it interacts adversely with
+ *                         the end-to-end integrity scheme. See #20788 for
+ *                         context.
  * @return Byte vector with decrypted data
  */
 std::vector<uint8_t> scramble_decrypt_data(
     const std::vector<uint8_t> &data_in, uint32_t data_width,
     uint32_t subst_perm_width, const std::vector<uint8_t> &addr,
     uint32_t addr_width, const std::vector<uint8_t> &nonce,
-    const std::vector<uint8_t> &key, bool repeat_keystream);
+    const std::vector<uint8_t> &key, bool repeat_keystream, bool use_sp_layer);
 
 /** Encrypt scrambled data
  * @param data_in          Byte vector of data to encrypt
@@ -60,12 +64,16 @@ std::vector<uint8_t> scramble_decrypt_data(
  * @param repeat_keystream Repeat the keystream of one single PRINCE instance if
  *                         set to true. Otherwise multiple PRINCE instances are
  *                         used.
+ * @param use_sp_layer     Use the S&P layer for data diffusion. In HW this is
+ *                         disabled by default since it interacts adversely with
+ *                         the end-to-end integrity scheme. See #20788 for
+ *                         context.
  * @return Byte vector with encrypted data
  */
 std::vector<uint8_t> scramble_encrypt_data(
     const std::vector<uint8_t> &data_in, uint32_t data_width,
     uint32_t subst_perm_width, const std::vector<uint8_t> &addr,
     uint32_t addr_width, const std::vector<uint8_t> &nonce,
-    const std::vector<uint8_t> &key, bool repeat_keystream);
+    const std::vector<uint8_t> &key, bool repeat_keystream, bool use_sp_layer);
 
 #endif  // OPENTITAN_HW_IP_PRIM_DV_PRIM_RAM_SCR_CPP_SCRAMBLE_MODEL_H_
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_secded/secded_enc.c b/vendor/lowrisc_ip/ip/prim/dv/prim_secded/secded_enc.c
index e61909f7..c4e447c9 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_secded/secded_enc.c
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_secded/secded_enc.c
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_secded/secded_enc.core b/vendor/lowrisc_ip/ip/prim/dv/prim_secded/secded_enc.core
index 702da678..f8d3641a 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_secded/secded_enc.core
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_secded/secded_enc.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/dv/prim_secded/secded_enc.h b/vendor/lowrisc_ip/ip/prim/dv/prim_secded/secded_enc.h
index 776dbc87..f046f1d9 100644
--- a/vendor/lowrisc_ip/ip/prim/dv/prim_secded/secded_enc.h
+++ b/vendor/lowrisc_ip/ip/prim/dv/prim_secded/secded_enc.h
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_async_fatal_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_async_fatal_fpv.core
index 677a3fef..bb423db9 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_async_fatal_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_async_fatal_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_alert_rxtx_async_fatal_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_async_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_async_fpv.core
index c1907fef..52fa7bc3 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_async_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_async_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_alert_rxtx_async_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_fatal_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_fatal_fpv.core
index 28a286cd..abb7ff04 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_fatal_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_fatal_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_alert_rxtx_fatal_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_fpv.core
index 8c879034..41525840 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_alert_rxtx_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_arbiter_fixed_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_arbiter_fixed_fpv.core
index e1334220..8388ce62 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_arbiter_fixed_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_arbiter_fixed_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_arbiter_fixed_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_arbiter_ppc_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_arbiter_ppc_fpv.core
index 48c88355..e6c85849 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_arbiter_ppc_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_arbiter_ppc_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_arbiter_ppc_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_arbiter_tree_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_arbiter_tree_fpv.core
index 684d5c3d..ecdff0cf 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_arbiter_tree_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_arbiter_tree_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_arbiter_tree_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_count_expected_failure.hjson b/vendor/lowrisc_ip/ip/prim/fpv/prim_count_expected_failure.hjson
deleted file mode 100644
index 30df389f..00000000
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_count_expected_failure.hjson
+++ /dev/null
@@ -1,13 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// These two assertions are unreachable in the prim_count environment unless the counters are
-// forced to have different output.
-{
-  unreachable:
-  [
-    prim_count_tb.u_counter.CntErrForward_A:precondition1
-    prim_count_tb.u_counter.CntErrBackward_A:precondition1
-  ]
-}
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_count_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_count_fpv.core
index dcd2bde3..2a2b9303 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_count_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_count_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_count_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_esc_rxtx_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_esc_rxtx_fpv.core
index 7538ca35..006e4ada 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_esc_rxtx_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_esc_rxtx_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_esc_rxtx_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_fifo_async_sram_adapter_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_fifo_async_sram_adapter_fpv.core
index 4c8c9241..55781215 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_fifo_async_sram_adapter_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_fifo_async_sram_adapter_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_fifo_async_sram_adapter_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_fifo_sync_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_fifo_sync_fpv.core
index d3f1baad..e3d1560d 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_fifo_sync_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_fifo_sync_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_fifo_sync_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_keccak_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_keccak_fpv.core
index b60df136..ae1a1cd8 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_keccak_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_keccak_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_keccak_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_lfsr_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_lfsr_fpv.core
index 824f2129..1b50392c 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_lfsr_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_lfsr_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_lfsr_fpv:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_packer_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_packer_fpv.core
index 3e147f7d..d05eb771 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_packer_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_packer_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_22_16_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_22_16_fpv.core
index 5d9ab391..cd4dfb98 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_22_16_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_22_16_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_22_16_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_28_22_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_28_22_fpv.core
index 97f4f4eb..2dadba87 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_28_22_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_28_22_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_28_22_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_39_32_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_39_32_fpv.core
index c2391519..fe938bb1 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_39_32_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_39_32_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_39_32_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_64_57_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_64_57_fpv.core
index 2ab02bcf..51f8ec68 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_64_57_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_64_57_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_64_57_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_72_64_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_72_64_fpv.core
index cc5aeb87..768459b8 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_72_64_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_72_64_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_72_64_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_22_16_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_22_16_fpv.core
index 49108040..93295d08 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_22_16_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_22_16_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_hamming_22_16_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_39_32_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_39_32_fpv.core
index b73f22b9..26328be4 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_39_32_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_39_32_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_hamming_39_32_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_72_64_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_72_64_fpv.core
index 5f9f1021..0d7d9f84 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_72_64_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_72_64_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_hamming_72_64_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_76_68_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_76_68_fpv.core
index 0ea18cb2..2b45f51e 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_76_68_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_76_68_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_hamming_76_68_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_22_16_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_22_16_fpv.core
index 4094c008..8f23957c 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_22_16_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_22_16_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_inv_22_16_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_28_22_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_28_22_fpv.core
index d68bb353..21c9627a 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_28_22_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_28_22_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_inv_28_22_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_39_32_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_39_32_fpv.core
index 07df9f13..953cb683 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_39_32_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_39_32_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_inv_39_32_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_64_57_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_64_57_fpv.core
index d5d7f57a..09919615 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_64_57_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_64_57_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_inv_64_57_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_72_64_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_72_64_fpv.core
index 755eaf01..78f6c76a 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_72_64_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_72_64_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_inv_72_64_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_22_16_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_22_16_fpv.core
index 9ab87ff2..77c801ea 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_22_16_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_22_16_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_inv_hamming_22_16_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_39_32_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_39_32_fpv.core
index 786a2898..e5a5b2a3 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_39_32_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_39_32_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_inv_hamming_39_32_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_72_64_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_72_64_fpv.core
index 08ef86aa..0046ce36 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_72_64_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_72_64_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_inv_hamming_72_64_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_76_68_fpv.core b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_76_68_fpv.core
index 750f67ac..1c7a6e21 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_76_68_fpv.core
+++ b/vendor/lowrisc_ip/ip/prim/fpv/prim_secded_inv_hamming_76_68_fpv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:fpv:prim_secded_inv_hamming_76_68_fpv:0.1"
@@ -30,4 +30,3 @@ targets:
 
   lint:
     <<: *default_target
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_bind_fpv.sv
index db33bf28..3a3254a0 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_bind_fpv.sv
index 3a66f270..796496e8 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_tb.sv
index 267a0ab4..e0bf1f2c 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_tb.sv
index 0327985f..d36700eb 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_bind_fpv.sv
index f3ac2efd..696dddda 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_fatal_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_fatal_bind_fpv.sv
index c3f33b65..958325f6 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_fatal_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_fatal_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_fatal_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_fatal_tb.sv
index 86376d2f..0e1b0eae 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_fatal_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_fatal_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_tb.sv
index a7575afe..a77f5829 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_arbiter_fixed_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_arbiter_fixed_tb.sv
index be7a5727..1ec1ffe0 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_arbiter_fixed_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_arbiter_fixed_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_arbiter_ppc_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_arbiter_ppc_tb.sv
index 087b2dd3..9de96877 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_arbiter_ppc_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_arbiter_ppc_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_arbiter_tree_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_arbiter_tree_tb.sv
index d37ea889..43fe0a6a 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_arbiter_tree_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_arbiter_tree_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_count_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_count_tb.sv
index a3cb8dae..83c7cd79 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_count_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_count_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -19,8 +19,9 @@ module prim_count_tb #(
   input incr_en_i,
   input decr_en_i,
   input [Width-1:0] step_i,
+  input commit_i,
   output logic [Width-1:0] cnt_o,
-  output logic [Width-1:0] cnt_next_o,
+  output logic [Width-1:0] cnt_after_commit_o,
   output logic err_o
 );
 
@@ -36,8 +37,9 @@ module prim_count_tb #(
     .incr_en_i,
     .decr_en_i,
     .step_i,
+    .commit_i,
     .cnt_o,
-    .cnt_next_o,
+    .cnt_after_commit_o,
     .err_o
   );
 
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_esc_rxtx_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_esc_rxtx_bind_fpv.sv
index 80c47bbd..34468ec3 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_esc_rxtx_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_esc_rxtx_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -6,18 +6,19 @@
 module prim_esc_rxtx_bind_fpv;
 
   bind prim_esc_rxtx_fpv
-        prim_esc_rxtx_assert_fpv prim_esc_rxtx_assert_fpv (
-    .clk_i       ,
-    .rst_ni      ,
-    .resp_err_pi ,
-    .resp_err_ni ,
-    .esc_err_pi  ,
-    .esc_err_ni  ,
-    .esc_req_i   ,
-    .ping_req_i  ,
-    .ping_ok_o   ,
-    .integ_fail_o,
-    .esc_req_o
-  );
+    prim_esc_rxtx_assert_fpv #(TimeoutCntDw(TimeoutCntDw))
+    prim_esc_rxtx_assert_fpv (
+      .clk_i       ,
+      .rst_ni      ,
+      .resp_err_pi ,
+      .resp_err_ni ,
+      .esc_err_pi  ,
+      .esc_err_ni  ,
+      .esc_req_i   ,
+      .ping_req_i  ,
+      .ping_ok_o   ,
+      .integ_fail_o,
+      .esc_req_o
+    );
 
 endmodule : prim_esc_rxtx_bind_fpv
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_esc_rxtx_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_esc_rxtx_tb.sv
index 7e27902e..f7d77ce5 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_esc_rxtx_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_esc_rxtx_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -23,6 +23,10 @@ module prim_esc_rxtx_tb
   output logic esc_req_o
 );
 
+  // This gets passed to the prim_esc_receiver that we instantiate below. Doing so reduces the state
+  // space for the counter from 2**24 to 2**6, speeding up convergence.
+  localparam int TimeoutCntDw = 6;
+
   esc_rx_t esc_rx_in, esc_rx_out;
   esc_tx_t esc_tx_in, esc_tx_out;
 
@@ -43,9 +47,7 @@ module prim_esc_rxtx_tb
   );
 
   prim_esc_receiver #(
-    // This reduces the state space for this counter
-    // from 2**24 to 2**6 to speed up convergence.
-    .TimeoutCntDw(6)
+    .TimeoutCntDw(TimeoutCntDw)
   ) u_prim_esc_receiver (
     .clk_i    ,
     .rst_ni   ,
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_tb.sv
index 889796ea..4faac749 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_fifo_sync_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_fifo_sync_bind_fpv.sv
index e734d980..895a9e28 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_fifo_sync_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_fifo_sync_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_fifo_sync_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_fifo_sync_tb.sv
index 5dfa5bc9..a879001e 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_fifo_sync_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_fifo_sync_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_keccak_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_keccak_tb.sv
index f5d0c3d5..dec2c83f 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_keccak_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_keccak_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -71,4 +71,3 @@ module prim_keccak_tb #(
   `ASSERT(DigestForData0TestSHA3_256_A, done_o |-> state_o[255:0] == digest_0)
 
 endmodule
-
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_lfsr_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_lfsr_tb.sv
index dd2c9eb5..362fb463 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_lfsr_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_lfsr_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_packer_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_packer_tb.sv
index 61469635..91ef8f06 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_packer_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_packer_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_22_16_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_22_16_bind_fpv.sv
index 1102d956..81f32a25 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_22_16_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_22_16_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_22_16_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_22_16_tb.sv
index e7da60e9..63adab83 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_22_16_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_22_16_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_28_22_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_28_22_bind_fpv.sv
index 06a0ab79..3d4ccd7f 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_28_22_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_28_22_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_28_22_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_28_22_tb.sv
index 6a6ff792..1774a700 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_28_22_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_28_22_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_39_32_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_39_32_bind_fpv.sv
index 1215d79e..b75a1696 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_39_32_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_39_32_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_39_32_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_39_32_tb.sv
index a497af98..b79de1aa 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_39_32_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_39_32_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_64_57_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_64_57_bind_fpv.sv
index 0acfbe8e..e1bbf483 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_64_57_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_64_57_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_64_57_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_64_57_tb.sv
index 9cc9ef36..fd338c14 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_64_57_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_64_57_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_72_64_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_72_64_bind_fpv.sv
index 31a1657c..5f205965 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_72_64_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_72_64_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_72_64_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_72_64_tb.sv
index f653524d..f20c24bc 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_72_64_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_72_64_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_22_16_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_22_16_bind_fpv.sv
index 8ecfc234..d036c6aa 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_22_16_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_22_16_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_22_16_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_22_16_tb.sv
index cffae6b6..8eb15271 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_22_16_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_22_16_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_39_32_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_39_32_bind_fpv.sv
index 35eb0bf2..141a4a2c 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_39_32_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_39_32_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_39_32_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_39_32_tb.sv
index 5a59e151..fcd7bc67 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_39_32_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_39_32_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_72_64_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_72_64_bind_fpv.sv
index bf09d376..90d73217 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_72_64_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_72_64_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_72_64_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_72_64_tb.sv
index 5f4c8e3b..2e222631 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_72_64_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_72_64_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_76_68_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_76_68_bind_fpv.sv
index 4962eb1a..44a8a1da 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_76_68_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_76_68_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_76_68_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_76_68_tb.sv
index a599ce1d..bef37cfa 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_76_68_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_76_68_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_22_16_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_22_16_bind_fpv.sv
index 96d0c95a..404c4649 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_22_16_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_22_16_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_22_16_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_22_16_tb.sv
index aaa51230..6f6ef0a5 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_22_16_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_22_16_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_28_22_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_28_22_bind_fpv.sv
index 5b114b2c..27eb0cbb 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_28_22_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_28_22_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_28_22_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_28_22_tb.sv
index ff4caf40..cc70790b 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_28_22_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_28_22_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_39_32_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_39_32_bind_fpv.sv
index a1159648..03a366e6 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_39_32_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_39_32_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_39_32_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_39_32_tb.sv
index b1c5af62..71ec6b0f 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_39_32_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_39_32_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_64_57_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_64_57_bind_fpv.sv
index 81bb663f..311459b6 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_64_57_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_64_57_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_64_57_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_64_57_tb.sv
index fd0751dd..34799d5f 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_64_57_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_64_57_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_72_64_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_72_64_bind_fpv.sv
index 3a37a45b..2aa9b436 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_72_64_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_72_64_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_72_64_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_72_64_tb.sv
index 1d2c6d8d..700e92bf 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_72_64_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_72_64_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_22_16_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_22_16_bind_fpv.sv
index 07e95af1..f7afc99c 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_22_16_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_22_16_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_22_16_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_22_16_tb.sv
index 6397d77b..b572bbc8 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_22_16_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_22_16_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_39_32_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_39_32_bind_fpv.sv
index a364b15d..2be0b2af 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_39_32_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_39_32_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_39_32_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_39_32_tb.sv
index 7d1fcdf5..fd4b03a1 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_39_32_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_39_32_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_72_64_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_72_64_bind_fpv.sv
index 4c4bc3a3..0d5e275d 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_72_64_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_72_64_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_72_64_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_72_64_tb.sv
index 52acaddb..561e53c7 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_72_64_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_72_64_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_76_68_bind_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_76_68_bind_fpv.sv
index 8c2bac91..fb716146 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_76_68_bind_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_76_68_bind_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_76_68_tb.sv b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_76_68_tb.sv
index c635bb11..2f7275d2 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_76_68_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_76_68_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_alert_rxtx_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_alert_rxtx_assert_fpv.sv
index ebdaf704..22d21941 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_alert_rxtx_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_alert_rxtx_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_alert_rxtx_async_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_alert_rxtx_async_assert_fpv.sv
index eaa8c035..486c5f6f 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_alert_rxtx_async_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_alert_rxtx_async_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_esc_rxtx_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_esc_rxtx_assert_fpv.sv
index 165f85ee..d39fae3f 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_esc_rxtx_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_esc_rxtx_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -7,7 +7,11 @@
 
 `include "prim_assert.sv"
 
-module prim_esc_rxtx_assert_fpv (
+module prim_esc_rxtx_assert_fpv
+#(
+  // Specialise this as part of the binding to shrink the state space that we expect in the counter.
+  parameter int TimeoutCntDw = 32
+) (
   input        clk_i,
   input        rst_ni,
   // for sigint error injection only
@@ -138,13 +142,18 @@ module prim_esc_rxtx_assert_fpv (
       rst_ni ||
       error_present)
 
+  // The assertions below use TimeoutCntDw to bound some sequence lengths. Add an assertion to check
+  // it matches the parameter in the design.
+  `ASSERT(TimeoutCntDwConsistent_A,
+          TimeoutCntDw == prim_esc_rxtx_fpv.u_prim_esc_receiver.TimeoutCntDw)
+
   // check that auto escalation timeout does not trigger prematurely.
   // this requires that no errors have been present so far.
   `ASSERT(AutoEscalation0_A,
       ping_req_i &&
       ping_ok_o &&
       !esc_req_o ##1
-      !ping_req_i [*0 : 2**prim_esc_rxtx_fpv.u_prim_esc_receiver.TimeoutCntDw - 4]
+      !ping_req_i [*0 : 2**TimeoutCntDw - 4]
       |->
       !esc_req_o,
       clk_i,
@@ -158,7 +167,7 @@ module prim_esc_rxtx_assert_fpv (
       ping_req_i &&
       ping_ok_o &&
       !esc_req_o ##1
-      !ping_req_i [* 2**prim_esc_rxtx_fpv.u_prim_esc_receiver.TimeoutCntDw - 3 : $]
+      !ping_req_i [* 2**TimeoutCntDw - 3 : $]
       |->
       esc_req_o,
       clk_i,
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_fifo_sync_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_fifo_sync_assert_fpv.sv
index 8cd7a3f4..7dd9bfa8 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_fifo_sync_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_fifo_sync_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -63,9 +63,9 @@ module prim_fifo_sync_assert_fpv #(
               fifo <= wdata_i;
             end else if (wvalid_i && wready_o) begin
               fifo <= wdata_i;
-              ref_depth <= ref_depth + 1;
+              ref_depth <= ref_depth + (DepthW+2)'(1);
             end else if (rvalid_o && rready_i) begin
-              ref_depth <= ref_depth - 1;
+              ref_depth <= ref_depth - (DepthW+2)'(1);
             end
           end
         end
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_22_16_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_22_16_assert_fpv.sv
index 8e654743..aa7629c3 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_22_16_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_22_16_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_28_22_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_28_22_assert_fpv.sv
index 31da73c9..cd697b25 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_28_22_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_28_22_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_39_32_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_39_32_assert_fpv.sv
index ba927d97..c06972da 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_39_32_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_39_32_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_64_57_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_64_57_assert_fpv.sv
index 746d1816..836129fb 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_64_57_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_64_57_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_72_64_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_72_64_assert_fpv.sv
index 5313f5dc..182b9b72 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_72_64_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_72_64_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_22_16_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_22_16_assert_fpv.sv
index 6e0a0790..d42cf38e 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_22_16_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_22_16_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_39_32_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_39_32_assert_fpv.sv
index 9bd5e30d..eb37711f 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_39_32_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_39_32_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_72_64_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_72_64_assert_fpv.sv
index c3eadf4b..f9071ae4 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_72_64_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_72_64_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_76_68_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_76_68_assert_fpv.sv
index 748a0910..36486b8d 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_76_68_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_76_68_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_22_16_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_22_16_assert_fpv.sv
index 2e9cb54a..2d73f706 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_22_16_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_22_16_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_28_22_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_28_22_assert_fpv.sv
index 42632ed3..450e4aa3 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_28_22_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_28_22_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_39_32_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_39_32_assert_fpv.sv
index 0d0b7d74..1e9f89c8 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_39_32_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_39_32_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_64_57_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_64_57_assert_fpv.sv
index 6c7e8ac4..7d775383 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_64_57_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_64_57_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_72_64_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_72_64_assert_fpv.sv
index 625af527..43a2f699 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_72_64_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_72_64_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_22_16_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_22_16_assert_fpv.sv
index 30b9bfea..8914863f 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_22_16_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_22_16_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_39_32_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_39_32_assert_fpv.sv
index 05a414ae..10c81b9b 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_39_32_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_39_32_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_72_64_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_72_64_assert_fpv.sv
index 229ae7c2..74d33689 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_72_64_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_72_64_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_76_68_assert_fpv.sv b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_76_68_assert_fpv.sv
index 41024b95..734d078e 100644
--- a/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_76_68_assert_fpv.sv
+++ b/vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_inv_hamming_76_68_assert_fpv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim.vlt
index bff544e5..75516923 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim.waiver
index 1a495fe9..877ff831 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_and2.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_and2.waiver
index 25e90e76..0bb3867d 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_and2.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_and2.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_arbiter.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_arbiter.vlt
index 42e44b2b..5bd76efb 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_arbiter.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_arbiter.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_arbiter.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_arbiter.waiver
index 278740ca..466aae2b 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_arbiter.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_arbiter.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_assert.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_assert.vlt
index affe7509..ed01d25f 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_assert.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_assert.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_assert.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_assert.waiver
index 83286a7c..a8e89a4d 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_assert.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_assert.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_buf.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_buf.waiver
index ea04aab8..99697a04 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_buf.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_buf.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_cdc_rand_delay.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_cdc_rand_delay.vlt
index 6416525d..bf1b6d9e 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_cdc_rand_delay.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_cdc_rand_delay.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_cdc_rand_delay.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_cdc_rand_delay.waiver
index db67e540..ebbcda59 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_cdc_rand_delay.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_cdc_rand_delay.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_cipher.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_cipher.vlt
index 533b1cd9..ff6555c0 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_cipher.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_cipher.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_cipher_pkg.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_cipher_pkg.waiver
index faf69add..3c1acb10 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_cipher_pkg.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_cipher_pkg.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_clock_buf.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_clock_buf.waiver
index 9e030adb..ec243529 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_clock_buf.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_clock_buf.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_clock_div.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_clock_div.waiver
index c62bfacc..ed3b1237 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_clock_div.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_clock_div.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_clock_gating.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_clock_gating.waiver
index 0e10939d..25776680 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_clock_gating.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_clock_gating.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_clock_inv.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_clock_inv.waiver
index 0893e786..c0db17f2 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_clock_inv.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_clock_inv.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_clock_mux2.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_clock_mux2.waiver
index 6a82aaa6..4e7c35b7 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_clock_mux2.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_clock_mux2.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_count.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_count.vlt
index b47f59e7..d06d166e 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_count.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_count.vlt
@@ -1,8 +1,9 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
 `verilator_config
 
-// This parameter is only used in DV/FPV.
+// These parameters are only used in DV/FPV.
 lint_off -rule UNUSED -file "*/rtl/prim_count.sv" -match "*EnableAlertTriggerSVA*"
+lint_off -rule UNUSED -file "*/rtl/prim_count.sv" -match "*PossibleActions*"
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_count.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_count.waiver
index c0b59c97..0d8b75e0 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_count.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_count.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -6,6 +6,8 @@
 
 waive -rules {PARAM_NOT_USED} -location {prim_count.sv} -regexp {.*EnableAlertTriggerSVA.*} \
       -comment "The disable parameter is used only during DV / FPV."
+waive -rules {PARAM_NOT_USED} -location {prim_count.sv} -regexp {.*PossibleActions.*} \
+      -comment "The parameter is just used to control assertions in DV / FPV."
 
-waive -rules {IFDEF_CODE} -location {prim_count.sv} -msg {Assignment to 'fpv_force' contained within `ifndef 'FPV_SEC_CM_ON' block at} \
-      -comment "This ifdef segment is ok, since it is used to provide the tool with a symbolic variable for error injection during FPV."
+waive -rules {IFDEF_CODE} -location {prim_count.sv} -msg {Assignment to 'fpv_force' contained within `ifndef 'PrimCountFpv' block at} \
+      -comment "This ifdef segment allows us to allow error injection during prim_count FPV."
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_crc32.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_crc32.vlt
index 85805e66..7878b654 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_crc32.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_crc32.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_double_lfsr.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_double_lfsr.vlt
index fe7645de..369f0660 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_double_lfsr.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_double_lfsr.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -7,4 +7,3 @@
 // The EnableAlertTriggerSVA parameter is only used by modules bound
 // in for DV testing. Waive the warning that we don't read it.
 lint_off -rule UNUSED -file "*/rtl/prim_double_lfsr.sv" -match "*EnableAlertTriggerSVA*"
-
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_double_lfsr.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_double_lfsr.waiver
index 5cbfa7ec..01bcef0f 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_double_lfsr.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_double_lfsr.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_fifo.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_fifo.vlt
index a05e9372..63cb7410 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_fifo.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_fifo.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_fifo.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_fifo.waiver
index bf1bb227..b8c503a3 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_fifo.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_fifo.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_flash.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_flash.waiver
index 3833a524..3cb57f8e 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_flash.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_flash.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_flop.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_flop.waiver
index 8659dddb..412b43b8 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_flop.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_flop.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_flop_2sync.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_flop_2sync.waiver
index ea071eba..1f654438 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_flop_2sync.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_flop_2sync.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_flop_en.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_flop_en.waiver
index 3ccaaa79..3fe276d4 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_flop_en.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_flop_en.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_lc_sender.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_lc_sender.waiver
index e1b921ec..337643ee 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_lc_sender.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_lc_sender.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -6,6 +6,3 @@
 
 waive -rules {SAME_NAME_TYPE} -location {prim_lc_sender.sv} -regexp {'ResetValue' is used as an enumeration value here, and as a parameter at prim.*} \
       -comment "Parameter name reuse"
-
-
-
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_lfsr.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_lfsr.waiver
index 0ce77e4c..69901528 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_lfsr.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_lfsr.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_max_tree.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_max_tree.vlt
index fe2485c8..a05e5984 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_max_tree.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_max_tree.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_max_tree.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_max_tree.waiver
index 87080201..39c947b4 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_max_tree.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_max_tree.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_mubi.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_mubi.waiver
index c7527fbc..e168a801 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_mubi.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_mubi.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -6,6 +6,3 @@
 
 waive -rules {SAME_NAME_TYPE} -location {prim_mubi*.sv} -regexp {'ResetValue' is used as an enumeration value here, and as a parameter at prim.*} \
       -comment "Parameter name reuse"
-
-
-
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_onehot_check.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_onehot_check.vlt
index d7d927ba..15cc9719 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_onehot_check.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_onehot_check.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_onehot_check.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_onehot_check.waiver
index 65d5b0b3..f78c4210 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_onehot_check.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_onehot_check.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_onehot_mux.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_onehot_mux.waiver
index f4b38e2b..47c88c55 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_onehot_mux.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_onehot_mux.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_otp.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_otp.waiver
index 593bbc53..5257870c 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_otp.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_otp.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_pad_attr.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_pad_attr.waiver
index e7bbc692..ab5fcaf3 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_pad_attr.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_pad_attr.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_pad_wrapper.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_pad_wrapper.waiver
index c03e0390..9c1371d5 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_pad_wrapper.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_pad_wrapper.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1p.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1p.waiver
index 5e3de12f..0ed0b687 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1p.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1p.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1p_adv.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1p_adv.waiver
index 6e49dff4..dfd8d6f4 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1p_adv.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1p_adv.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1p_scr.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1p_scr.vlt
index 3397d483..19b12dc0 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1p_scr.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1p_scr.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1r1w.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1r1w.waiver
new file mode 100644
index 00000000..df081fc0
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_ram_1r1w.waiver
@@ -0,0 +1,8 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for prim_ram_1r1w
+
+waive -rules {STAR_PORT_CONN_USE} -location {prim_ram_1r1w.sv} -regexp {.*wild card port connection encountered on instance.*} \
+      -comment "Generated prims may have wildcard connections."
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_ram_2p.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_ram_2p.waiver
index 474975e4..127ba791 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_ram_2p.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_ram_2p.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_reg_we_check.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_reg_we_check.waiver
index 0c13a949..d4306c33 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_reg_we_check.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_reg_we_check.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_rom.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_rom.waiver
index 5b588b41..ac01674d 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_rom.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_rom.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_rst_sync.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_rst_sync.waiver
index e05268b2..157e36c5 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_rst_sync.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_rst_sync.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_secded.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_secded.waiver
index ace5295c..f419c535 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_secded.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_secded.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_sha2.vbl b/vendor/lowrisc_ip/ip/prim/lint/prim_sha2.vbl
new file mode 100644
index 00000000..f1e966a1
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_sha2.vbl
@@ -0,0 +1,9 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for prim_sha2 pre_dv Verilator testbenches
+
+# waive long line violations in test vectors feeding
+waive --rule=line-length --location="prim_sha_multimode32_tb.sv"
+waive --rule=line-length --location="prim_sha_tb.sv"
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_sha2.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_sha2.vlt
new file mode 100644
index 00000000..93833401
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_sha2.vlt
@@ -0,0 +1,12 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// waiver file for sha-2
+
+`verilator_config
+
+// The wipe_secret and wipe_v inputs to hmac_core and sha2_pad are not
+// currently used, but we're keeping them attached for future use.
+lint_off -rule UNUSED -file "*/rtl/prim_sha2_pad.sv" -match "Signal is not used: 'wipe_secret'"
+lint_off -rule UNUSED -file "*/rtl/prim_sha2_pad.sv" -match "Signal is not used: 'wipe_v'"
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_sha2.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_sha2.waiver
new file mode 100644
index 00000000..cb5b908e
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_sha2.waiver
@@ -0,0 +1,45 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for SHA-2: prim_sha2, prim_sha2_pad, prim_sha2_32, prim_sha2_pkg
+
+waive -rules {CONST_FF RESET_ONLY PARTIAL_CONST_ASSIGN} -location {prim_sha2.sv} -regexp {processed_length\[8:0\]} \
+      -comment "lower 512bits of message are aligned. So ignoring txcount for lower 9 bits"
+waive -rules {CONST_FF RESET_ONLY PARTIAL_CONST_ASSIGN} -location {prim_sha2_pad.sv} -regexp {tx_count\[4:0\]} \
+      -comment "lower 32bits of message are aligned. So ignoring txcount for lower 5 bits"
+waive -rules {NOT_READ HIER_NET_NOT_READ CONST_OUTPUT} -location {prim_sha2_pad.sv prim_sha2.sv} \
+      -regexp {padded_length\[8:0\]} \
+      -comment "lower 512bits of padded message are 0 (always aligned message)"
+
+waive -rules {EXPLICIT_BITLEN} -location {prim_sha2.sv} -regexp {.*(0|1)} \
+      -comment "Added or subtracted by 1"
+
+waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {prim_sha2_pad.sv} -regexp {wipe_(secret|v)} \
+      -comment "Not used but remained for future use"
+
+waive -rules {NOT_READ} -location {*_reg_top.sv} -regexp {(address|param|user)} \
+      -comment "Register module waiver"
+
+# ARITH_CONTEXT
+waive -rules {ARITH_CONTEXT} -location {prim_sha2.sv}     -regexp {Bitlength of arithmetic operation '.processed_length.63:9. \+ 1'b1.'} \
+      -comment "Bitwidth overflow is intended"
+waive -rules {ARITH_CONTEXT} -location {prim_sha2_pad.sv} -regexp {Bitlength of arithmetic operation 'tx_count.63:5. \+ 2'd1'} \
+      -comment "Bitwidth overflow is intended"
+waive -rules {ARITH_CONTEXT} -location {prim_sha2_pad.sv} -regexp {Bitlength of arithmetic operation 'message_length.63:9. \+ (1'b1|2'b10)'} \
+      -comment "Bitwidth overflow is intended"
+waive -rules {ARITH_CONTEXT} -location {prim_sha2_pkg.sv} -regexp {Bitlength of arithmetic operation 'h_i\[3\]\[31:0\] \+ temp1' is self-determined in this context} \
+      -comment "Bitwidth overflow is intended"
+waive -rules {ARITH_CONTEXT} -location {prim_sha2_pkg.sv} -regexp {Bitlength of arithmetic operation '\(temp1 \+ temp2\)' is self-determined in this context} \
+      -comment "Bitwidth overflow is intended"
+
+# INPUT_NOT_READ
+waive -rules {INPUT_NOT_READ} -location {prim_sha2_pkg.sv} -regexp {Input port 'h_i\[0:7\]\[63:32\]' is not read from in function 'compress_multi_256'}
+      -comment "Upper bits are only used in SHA2-384/512"
+
+# INTEGER
+waive -rules {INTEGER}        -location {prim_sha2_pkg.sv} -regexp {'amt' of type int used as a}
+waive -rules {TWO_STATE_TYPE} -location {prim_sha2_pkg.sv} -regexp {'amt' is of two state type 'int'} \
+      -comment "shift function behaves as static, it is called with constant in the design"
+waive -rules {INTEGER}        -location {prim_sha2_pkg.sv} -regexp {'amt' of type integer used as a non-constant value} \
+      -comment "rotate function behaves as static function - it is called with a constant value in the design"
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_sparse_fsm_flop.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_sparse_fsm_flop.vlt
index 1ae4299a..3c2a8465 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_sparse_fsm_flop.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_sparse_fsm_flop.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_sparse_fsm_flop.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_sparse_fsm_flop.waiver
index 03a5ee86..c9c9ad49 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_sparse_fsm_flop.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_sparse_fsm_flop.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_subreg.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_subreg.vlt
index 620f1d23..689134ef 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_subreg.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_subreg.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_subreg.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_subreg.waiver
index fe378348..d66498b7 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_subreg.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_subreg.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_sum_tree.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_sum_tree.vlt
index bb990bd7..77919bb6 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_sum_tree.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_sum_tree.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_sum_tree.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_sum_tree.waiver
index 7f2fa7c9..60736ce3 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_sum_tree.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_sum_tree.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_trivium.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_trivium.vlt
index d6149e32..d8d9af56 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_trivium.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_trivium.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_trivium.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_trivium.waiver
index 5f6dec1d..71819a5f 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_trivium.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_trivium.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_usb_diff_rx.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_usb_diff_rx.waiver
index 30c0bdbc..ed04584b 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_usb_diff_rx.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_usb_diff_rx.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_xnor2.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_xnor2.waiver
index 77f1c6a0..37962c55 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_xnor2.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_xnor2.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_xor2.waiver b/vendor/lowrisc_ip/ip/prim/lint/prim_xor2.waiver
index c2625ae0..28da4f0f 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_xor2.waiver
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_xor2.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/lint/prim_xoshiro256pp.vlt b/vendor/lowrisc_ip/ip/prim/lint/prim_xoshiro256pp.vlt
index 4fa210f9..be4fbfe6 100644
--- a/vendor/lowrisc_ip/ip/prim/lint/prim_xoshiro256pp.vlt
+++ b/vendor/lowrisc_ip/ip/prim/lint/prim_xoshiro256pp.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/expected_out.py b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/expected_out.py
index 62a27eef..ee474a32 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/expected_out.py
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/expected_out.py
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.cc b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.cc
index 9403703d..1be56fac 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.cc
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.core b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.core
index 7c6e9d4d..23118823 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.core
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:prim:crc32_sim"
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.sv b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.sv
index 041da16a..a736ca41 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.sv
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/prim_crc32_sim.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/run_predv.sh b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/run_predv.sh
index d10fe46c..3f5a7aeb 100755
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/run_predv.sh
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_crc32/run_predv.sh
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_flop_2sync/prim_flop_2sync_sim.core b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_flop_2sync/prim_flop_2sync_sim.core
index e2b9c593..a716d774 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_flop_2sync/prim_flop_2sync_sim.core
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_flop_2sync/prim_flop_2sync_sim.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv:prim_flop_2sync_sim:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_flop_2sync/prim_flop_2sync_sim_cfg.hjson b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_flop_2sync/prim_flop_2sync_sim_cfg.hjson
index 660a6e30..4e460838 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_flop_2sync/prim_flop_2sync_sim_cfg.hjson
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_flop_2sync/prim_flop_2sync_sim_cfg.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_flop_2sync/tb.sv b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_flop_2sync/tb.sv
index 4d91ce51..1ee95004 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_flop_2sync/tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_flop_2sync/tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/cpp/prim_sync_reqack_tb.cc b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/cpp/prim_sync_reqack_tb.cc
index 1b8adf21..34032ac0 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/cpp/prim_sync_reqack_tb.cc
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/cpp/prim_sync_reqack_tb.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/prim_sync_reqack_tb.core b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/prim_sync_reqack_tb.core
index 99f272e2..21fd9adc 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/prim_sync_reqack_tb.core
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/prim_sync_reqack_tb.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv_verilator:prim_sync_reqack_tb"
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/rtl/prim_sync_reqack_tb.sv b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/rtl/prim_sync_reqack_tb.sv
index 36b881c5..b7e0cf73 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/rtl/prim_sync_reqack_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_sync_reqack/rtl/prim_sync_reqack_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_trivium/cpp/prim_trivium_tb.cc b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_trivium/cpp/prim_trivium_tb.cc
index df0a8c64..3b0201c7 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_trivium/cpp/prim_trivium_tb.cc
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_trivium/cpp/prim_trivium_tb.cc
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_trivium/prim_trivium_tb.core b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_trivium/prim_trivium_tb.core
index 6c942c51..f86d00c8 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_trivium/prim_trivium_tb.core
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_trivium/prim_trivium_tb.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:dv_verilator:prim_trivium_tb"
diff --git a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_trivium/rtl/prim_trivium_tb.sv b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_trivium/rtl/prim_trivium_tb.sv
index 9541fa03..653d263f 100644
--- a/vendor/lowrisc_ip/ip/prim/pre_dv/prim_trivium/rtl/prim_trivium_tb.sv
+++ b/vendor/lowrisc_ip/ip/prim/pre_dv/prim_trivium/rtl/prim_trivium_tb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -137,14 +137,15 @@ module prim_trivium_tb (
     .rst_ni(rst_ni),
 
     .en_i                (trivium_en),
+    .allow_lockup_i      (1'b0),
     .seed_en_i           (trivium_seed_en),
     .seed_done_o         (trivium_seed_done_seed_key_iv),
     .seed_req_o          (),
     .seed_ack_i          (trivium_seed_en),
     .seed_key_i          (seed_key),
     .seed_iv_i           (seed_iv),
-    .seed_state_full_i   (),
-    .seed_state_partial_i(),
+    .seed_state_full_i   ('0), // unused
+    .seed_state_partial_i('0), // unused
 
     .key_o(key_seed_key_iv),
     .err_o()
@@ -159,14 +160,15 @@ module prim_trivium_tb (
     .rst_ni(rst_ni),
 
     .en_i                (trivium_en),
+    .allow_lockup_i      (1'b0),
     .seed_en_i           (trivium_seed_en),
     .seed_done_o         (trivium_seed_done_seed_state_full),
     .seed_req_o          (),
     .seed_ack_i          (trivium_seed_en),
-    .seed_key_i          (),
-    .seed_iv_i           (),
+    .seed_key_i          ('0), // unused
+    .seed_iv_i           ('0), // unused
     .seed_state_full_i   (seed_state_full),
-    .seed_state_partial_i(),
+    .seed_state_partial_i('0), // unused
 
     .key_o(key_seed_state_full),
     .err_o()
@@ -182,13 +184,14 @@ module prim_trivium_tb (
     .rst_ni(rst_ni),
 
     .en_i                (trivium_en),
+    .allow_lockup_i      (1'b0),
     .seed_en_i           (trivium_seed_en),
     .seed_done_o         (trivium_seed_done_seed_state_partial),
     .seed_req_o          (),
     .seed_ack_i          (trivium_seed_ack_seed_state_partial),
-    .seed_key_i          (),
-    .seed_iv_i           (),
-    .seed_state_full_i   (),
+    .seed_key_i          ('0), // unused
+    .seed_iv_i           ('0), // unused
+    .seed_state_full_i   ('0), // unused
     .seed_state_partial_i(trivium_seed_state_partial),
 
     .key_o(key_seed_state_partial),
@@ -315,14 +318,15 @@ module prim_trivium_tb (
     .rst_ni(rst_ni),
 
     .en_i                (bivium_en),
+    .allow_lockup_i      (1'b0),
     .seed_en_i           (bivium_seed_en),
     .seed_done_o         (bivium_seed_done_seed_key_iv),
     .seed_req_o          (),
     .seed_ack_i          (bivium_seed_en),
     .seed_key_i          (seed_key),
     .seed_iv_i           (seed_iv),
-    .seed_state_full_i   (),
-    .seed_state_partial_i(),
+    .seed_state_full_i   ('0), // unused
+    .seed_state_partial_i('0), // unused
 
     .key_o(key_seed_key_iv),
     .err_o()
@@ -337,37 +341,39 @@ module prim_trivium_tb (
     .rst_ni(rst_ni),
 
     .en_i                (bivium_en),
+    .allow_lockup_i      (1'b0),
     .seed_en_i           (bivium_seed_en),
     .seed_done_o         (bivium_seed_done_seed_state_full),
     .seed_req_o          (),
     .seed_ack_i          (bivium_seed_en),
-    .seed_key_i          (),
-    .seed_iv_i           (),
+    .seed_key_i          ('0), // unused
+    .seed_iv_i           ('0), // unused
     .seed_state_full_i   (seed_state_full[BiviumStateWidth-1:0]),
-    .seed_state_partial_i(),
+    .seed_state_partial_i('0), // unused
 
     .key_o(key_seed_state_full),
     .err_o()
   );
 
   prim_trivium #(
-    .BiviumVariant   (1),
-    .OutputWidth     (OutputWidth),
-    .LockupProtection(0),
-    .SeedType        (SeedTypeStatePartial),
-    .PartialSeedWidth(PartialSeedWidth)
+    .BiviumVariant         (1),
+    .OutputWidth           (OutputWidth),
+    .StrictLockupProtection(0),
+    .SeedType              (SeedTypeStatePartial),
+    .PartialSeedWidth      (PartialSeedWidth)
   ) u_prim_bivium_seed_state_partial (
     .clk_i (clk_i),
     .rst_ni(rst_ni),
 
     .en_i                (bivium_en),
+    .allow_lockup_i      (1'b1),
     .seed_en_i           (bivium_seed_en_seed_state_partial),
     .seed_done_o         (bivium_seed_done_seed_state_partial),
     .seed_req_o          (),
     .seed_ack_i          (bivium_seed_ack_seed_state_partial),
-    .seed_key_i          (),
-    .seed_iv_i           (),
-    .seed_state_full_i   (),
+    .seed_key_i          ('0), // unused
+    .seed_iv_i           ('0), // unused
+    .seed_state_full_i   ('0), // unused
     .seed_state_partial_i(bivium_seed_state_partial),
 
     .key_o(),
diff --git a/vendor/lowrisc_ip/ip/prim/prim.core b/vendor/lowrisc_ip/ip/prim/prim.core
index 7d701c8f..5aa7a57c 100644
--- a/vendor/lowrisc_ip/ip/prim/prim.core
+++ b/vendor/lowrisc_ip/ip/prim/prim.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -31,6 +31,7 @@ filesets:
       - lowrisc:prim:xnor2
       - lowrisc:prim:and2
       - lowrisc:prim:reg_we_check
+      - lowrisc:prim:sha2
     files:
       - rtl/prim_clock_gating_sync.sv
       - rtl/prim_sram_arbiter.sv
diff --git a/vendor/lowrisc_ip/ip/prim/prim_alert.core b/vendor/lowrisc_ip/ip/prim/prim_alert.core
index c92db58a..8574c8b5 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_alert.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_alert.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_and2.core b/vendor/lowrisc_ip/ip/prim/prim_and2.core
index 92654431..10cfee5c 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_and2.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_and2.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -16,7 +16,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: vlt
 
   files_ascentlint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_arbiter.core b/vendor/lowrisc_ip/ip/prim/prim_arbiter.core
index a15386d4..784de057 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_arbiter.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_arbiter.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_assert.core b/vendor/lowrisc_ip/ip/prim/prim_assert.core
index 26e88e43..8c7c79b1 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_assert.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_assert.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_blanker.core b/vendor/lowrisc_ip/ip/prim/prim_blanker.core
index c8b7a9a0..3d7121c1 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_blanker.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_blanker.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -17,15 +17,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_buf.core b/vendor/lowrisc_ip/ip/prim/prim_buf.core
index 648fcec3..9f10e8d6 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_buf.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_buf.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -16,7 +16,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: vlt
 
   files_ascentlint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_cdc_rand_delay.core b/vendor/lowrisc_ip/ip/prim/prim_cdc_rand_delay.core
index 38fb5382..5ae1c71a 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_cdc_rand_delay.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_cdc_rand_delay.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:prim:cdc_rand_delay"
diff --git a/vendor/lowrisc_ip/ip/prim/prim_cipher.core b/vendor/lowrisc_ip/ip/prim/prim_cipher.core
index a32c1d8b..780b386d 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_cipher.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_cipher.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_cipher_pkg.core b/vendor/lowrisc_ip/ip/prim/prim_cipher_pkg.core
index cdc3a296..24911ebf 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_cipher_pkg.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_cipher_pkg.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_clock_buf.core b/vendor/lowrisc_ip/ip/prim/prim_clock_buf.core
index 4f571fbf..54b95ae1 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_clock_buf.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_clock_buf.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -16,8 +16,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_clock_div.core b/vendor/lowrisc_ip/ip/prim/prim_clock_div.core
index 755f17d5..954f08d1 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_clock_div.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_clock_div.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,8 +15,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_clock_gating.core b/vendor/lowrisc_ip/ip/prim/prim_clock_gating.core
index 20be1209..04cf68bd 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_clock_gating.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_clock_gating.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -16,8 +16,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_clock_gp_mux2.core b/vendor/lowrisc_ip/ip/prim/prim_clock_gp_mux2.core
index 3918b322..2c9894d4 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_clock_gp_mux2.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_clock_gp_mux2.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_clock_inv.core b/vendor/lowrisc_ip/ip/prim/prim_clock_inv.core
index 97119199..a6dcab93 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_clock_inv.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_clock_inv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -16,8 +16,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_clock_meas.core b/vendor/lowrisc_ip/ip/prim/prim_clock_meas.core
index 45106751..af4c8656 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_clock_meas.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_clock_meas.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_clock_mux2.core b/vendor/lowrisc_ip/ip/prim/prim_clock_mux2.core
index 68566ac9..5f703ade 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_clock_mux2.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_clock_mux2.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -16,8 +16,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_count.core b/vendor/lowrisc_ip/ip/prim/prim_count.core
index f65bc6a9..5ceca227 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_count.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_count.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -10,6 +10,7 @@ filesets:
     depend:
       - lowrisc:prim:assert
     files:
+      - rtl/prim_count_pkg.sv
       - rtl/prim_count.sv
     file_type: systemVerilogSource
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_crc32.core b/vendor/lowrisc_ip/ip/prim/prim_crc32.core
index 178b68c7..51f3eaf2 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_crc32.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_crc32.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_diff_decode.core b/vendor/lowrisc_ip/ip/prim/prim_diff_decode.core
index a91367f7..996c37dd 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_diff_decode.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_diff_decode.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -10,6 +10,7 @@ filesets:
     depend:
       - lowrisc:prim:assert
       - lowrisc:prim:flop_2sync
+      - lowrisc:prim:xnor2
     files:
       - rtl/prim_diff_decode.sv
     file_type: systemVerilogSource
diff --git a/vendor/lowrisc_ip/ip/prim/prim_dom_and_2share.core b/vendor/lowrisc_ip/ip/prim/prim_dom_and_2share.core
index 9376d665..d2f5b46f 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_dom_and_2share.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_dom_and_2share.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -47,5 +47,3 @@ targets:
     filesets:
       - files_rtl
     toplevel: prim_dom_and_2share
-
-
diff --git a/vendor/lowrisc_ip/ip/prim/prim_double_lfsr.core b/vendor/lowrisc_ip/ip/prim/prim_double_lfsr.core
index 5edcb08b..28b632b4 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_double_lfsr.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_double_lfsr.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_edge_detector.core b/vendor/lowrisc_ip/ip/prim/prim_edge_detector.core
index 1d6d52fb..f0b1437d 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_edge_detector.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_edge_detector.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim/prim_edn_req.core b/vendor/lowrisc_ip/ip/prim/prim_edn_req.core
index 8c07aabd..6727b6a0 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_edn_req.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_edn_req.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_esc.core b/vendor/lowrisc_ip/ip/prim/prim_esc.core
index d796bbb5..d9b891ed 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_esc.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_esc.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_fifo.core b/vendor/lowrisc_ip/ip/prim/prim_fifo.core
index 002f96c9..dd0fc7eb 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_fifo.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_fifo.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_flash.core b/vendor/lowrisc_ip/ip/prim/prim_flash.core
index 849506b2..7e293a1d 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_flash.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_flash.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -21,8 +21,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_flop.core b/vendor/lowrisc_ip/ip/prim/prim_flop.core
index ced2c180..b707f1c4 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_flop.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_flop.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -16,7 +16,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: vlt
 
   files_ascentlint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_flop_2sync.core b/vendor/lowrisc_ip/ip/prim/prim_flop_2sync.core
index 82f99fe2..dc1fdb6f 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_flop_2sync.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_flop_2sync.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -21,7 +21,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: vlt
 
   files_ascentlint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_flop_en.core b/vendor/lowrisc_ip/ip/prim/prim_flop_en.core
index 3dc1c888..608384d1 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_flop_en.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_flop_en.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,7 +15,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: vlt
 
   files_ascentlint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_gf_mult.core b/vendor/lowrisc_ip/ip/prim/prim_gf_mult.core
index 361fb27e..ccc94bb1 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_gf_mult.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_gf_mult.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_lc_and_hardened.core b/vendor/lowrisc_ip/ip/prim/prim_lc_and_hardened.core
index a44be205..329259f3 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_lc_and_hardened.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_lc_and_hardened.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -19,16 +19,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      # - lint/prim_lc_and_hardened.waiver
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_lc_combine.core b/vendor/lowrisc_ip/ip/prim/prim_lc_combine.core
index 1437edc2..94a7602f 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_lc_combine.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_lc_combine.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -17,16 +17,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      # - lint/prim_lc_combine.waiver
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_lc_dec.core b/vendor/lowrisc_ip/ip/prim/prim_lc_dec.core
index c22e4b6d..2559e9b7 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_lc_dec.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_lc_dec.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -18,16 +18,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      # - lint/prim_lc_sync.waiver
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_lc_or_hardened.core b/vendor/lowrisc_ip/ip/prim/prim_lc_or_hardened.core
index 47bfb43b..9dbafef5 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_lc_or_hardened.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_lc_or_hardened.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -19,16 +19,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      # - lint/prim_lc_or_hardened.waiver
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_lc_sender.core b/vendor/lowrisc_ip/ip/prim/prim_lc_sender.core
index 378b9abe..9ebb4cc1 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_lc_sender.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_lc_sender.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -19,8 +19,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_lc_sync.core b/vendor/lowrisc_ip/ip/prim/prim_lc_sync.core
index 0a8d4491..05a6b5f7 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_lc_sync.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_lc_sync.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -20,15 +20,12 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      # - lint/prim_lc_sync.waiver
     file_type: waiver
 
   files_veriblelint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_lfsr.core b/vendor/lowrisc_ip/ip/prim/prim_lfsr.core
index 417e8183..752bd82a 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_lfsr.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_lfsr.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -18,8 +18,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_macros.core b/vendor/lowrisc_ip/ip/prim/prim_macros.core
index 70b9debd..67df40c2 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_macros.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_macros.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_max_tree.core b/vendor/lowrisc_ip/ip/prim/prim_max_tree.core
index 891da179..583714bd 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_max_tree.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_max_tree.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -41,9 +41,8 @@ targets:
       - tool_ascentlint  ? (files_ascentlint_waiver)
       - tool_veriblelint ? (files_veriblelint_waiver)
       - files_rtl
-  
+
   formal:
     filesets:
       - files_rtl
     toplevel: prim_max_tree
-    
\ No newline at end of file
diff --git a/vendor/lowrisc_ip/ip/prim/prim_msb_extend.core b/vendor/lowrisc_ip/ip/prim/prim_msb_extend.core
index 57388544..2895792b 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_msb_extend.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_msb_extend.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -22,7 +22,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: waiver
 
   files_veriblelint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_mubi.core b/vendor/lowrisc_ip/ip/prim/prim_mubi.core
index f51e4550..45aa85f7 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_mubi.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_mubi.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -30,14 +30,24 @@ filesets:
       - rtl/prim_mubi16_sender.sv
       - rtl/prim_mubi16_sync.sv
       - rtl/prim_mubi16_dec.sv
+      - rtl/prim_mubi20_sender.sv
+      - rtl/prim_mubi20_sync.sv
+      - rtl/prim_mubi20_dec.sv
+      - rtl/prim_mubi24_sender.sv
+      - rtl/prim_mubi24_sync.sv
+      - rtl/prim_mubi24_dec.sv
+      - rtl/prim_mubi28_sender.sv
+      - rtl/prim_mubi28_sync.sv
+      - rtl/prim_mubi28_dec.sv
+      - rtl/prim_mubi32_sender.sv
+      - rtl/prim_mubi32_sync.sv
+      - rtl/prim_mubi32_dec.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_multibit_sync.core b/vendor/lowrisc_ip/ip/prim/prim_multibit_sync.core
index 9ce56ee3..8cc4fd07 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_multibit_sync.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_multibit_sync.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_onehot.core b/vendor/lowrisc_ip/ip/prim/prim_onehot.core
index 2e5a52d7..f2ab8a1e 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_onehot.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_onehot.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_onehot_check.core b/vendor/lowrisc_ip/ip/prim/prim_onehot_check.core
index f62943d7..ed8a7aaf 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_onehot_check.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_onehot_check.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_otp.core b/vendor/lowrisc_ip/ip/prim/prim_otp.core
index 87cb491f..90d0eca4 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_otp.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_otp.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -19,8 +19,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_otp_pkg.core b/vendor/lowrisc_ip/ip/prim/prim_otp_pkg.core
index 9b603ec4..58c26309 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_otp_pkg.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_otp_pkg.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,15 +15,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_pad_attr.core b/vendor/lowrisc_ip/ip/prim/prim_pad_attr.core
index 6ac83a15..10219fbf 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_pad_attr.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_pad_attr.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -17,8 +17,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_pad_wrapper.core b/vendor/lowrisc_ip/ip/prim/prim_pad_wrapper.core
index 05a35938..e700faf1 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_pad_wrapper.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_pad_wrapper.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -17,7 +17,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: vlt
 
   files_ascentlint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_pad_wrapper_pkg.core b/vendor/lowrisc_ip/ip/prim/prim_pad_wrapper_pkg.core
index 76816d8b..17c79385 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_pad_wrapper_pkg.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_pad_wrapper_pkg.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,15 +15,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_pkg.core b/vendor/lowrisc_ip/ip/prim/prim_pkg.core
index f054f666..eea83269 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_pkg.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_pkg.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:prim:prim_pkg:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/prim_ram_1p.core b/vendor/lowrisc_ip/ip/prim/prim_ram_1p.core
index cedb5e10..b12882c6 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_ram_1p.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_ram_1p.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -17,8 +17,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_ram_1p_adv.core b/vendor/lowrisc_ip/ip/prim/prim_ram_1p_adv.core
index e0bed14a..ed465ba7 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_ram_1p_adv.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_ram_1p_adv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -19,8 +19,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_ram_1p_pkg.core b/vendor/lowrisc_ip/ip/prim/prim_ram_1p_pkg.core
index c1d9324d..8f66fbb0 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_ram_1p_pkg.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_ram_1p_pkg.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -7,7 +7,6 @@ name: "lowrisc:prim:ram_1p_pkg"
 description: "Ram 1p package"
 filesets:
   files_rtl:
-    depend:
     files:
       - rtl/prim_ram_1p_pkg.sv
     file_type: systemVerilogSource
diff --git a/vendor/lowrisc_ip/ip/prim/prim_ram_1p_scr.core b/vendor/lowrisc_ip/ip/prim/prim_ram_1p_scr.core
index fa96c76b..dea8ca67 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_ram_1p_scr.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_ram_1p_scr.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_ram_1r1w.core b/vendor/lowrisc_ip/ip/prim/prim_ram_1r1w.core
new file mode 100644
index 00000000..18acb862
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/prim_ram_1r1w.core
@@ -0,0 +1,48 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim:ram_1r1w"
+description: "Random-access memory with 1 read-only port and 1 write-only port"
+filesets:
+  primgen_dep:
+    depend:
+      - lowrisc:prim:prim_pkg
+      - lowrisc:prim:ram_2p_pkg
+      - lowrisc:prim:primgen
+
+
+  files_verilator_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+      - lint/prim_ram_1r1w.waiver
+    file_type: waiver
+
+  files_veriblelint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+generate:
+  impl:
+    generator: primgen
+    parameters:
+      prim_name: ram_1r1w
+
+targets:
+  default:
+    filesets:
+      - tool_verilator   ? (files_verilator_waiver)
+      - tool_ascentlint  ? (files_ascentlint_waiver)
+      - tool_veriblelint ? (files_veriblelint_waiver)
+      - primgen_dep
+    generate:
+      - impl
diff --git a/vendor/lowrisc_ip/ip/prim/prim_ram_1r1w_adv.core b/vendor/lowrisc_ip/ip/prim/prim_ram_1r1w_adv.core
new file mode 100644
index 00000000..33e0f91e
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/prim_ram_1r1w_adv.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim:ram_1r1w_adv:0.1"
+description: "Two-port (1 read-only port, 1 write-only port) RAM primitive with advanced features"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:ram_1r1w_async_adv
+    files:
+      - rtl/prim_ram_1r1w_adv.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_rtl
diff --git a/vendor/lowrisc_ip/ip/prim/prim_ram_1r1w_async_adv.core b/vendor/lowrisc_ip/ip/prim/prim_ram_1r1w_async_adv.core
new file mode 100644
index 00000000..6a4c3543
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/prim_ram_1r1w_async_adv.core
@@ -0,0 +1,22 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim:ram_1r1w_async_adv:0.1"
+description: "Asynchronous two-port (1 read-only port, 1 write-only port) RAM primitive with advanced features"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:assert
+      - lowrisc:prim:util
+      - lowrisc:prim:secded
+      - lowrisc:prim:ram_1r1w
+    files:
+      - rtl/prim_ram_1r1w_async_adv.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_rtl
diff --git a/vendor/lowrisc_ip/ip/prim/prim_ram_2p.core b/vendor/lowrisc_ip/ip/prim/prim_ram_2p.core
index e265b838..696c2248 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_ram_2p.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_ram_2p.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -17,8 +17,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_ram_2p_adv.core b/vendor/lowrisc_ip/ip/prim/prim_ram_2p_adv.core
index 3ff2dcd8..7a301db0 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_ram_2p_adv.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_ram_2p_adv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_ram_2p_async_adv.core b/vendor/lowrisc_ip/ip/prim/prim_ram_2p_async_adv.core
index e5eda9d0..54b5e8e1 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_ram_2p_async_adv.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_ram_2p_async_adv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_ram_2p_pkg.core b/vendor/lowrisc_ip/ip/prim/prim_ram_2p_pkg.core
index 34b3ad2f..074bc6c3 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_ram_2p_pkg.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_ram_2p_pkg.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -7,7 +7,6 @@ name: "lowrisc:prim:ram_2p_pkg"
 description: "Ram 2p package"
 filesets:
   files_rtl:
-    depend:
     files:
       - rtl/prim_ram_2p_pkg.sv
     file_type: systemVerilogSource
diff --git a/vendor/lowrisc_ip/ip/prim/prim_reg_we_check.core b/vendor/lowrisc_ip/ip/prim/prim_reg_we_check.core
index 47616643..87e56402 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_reg_we_check.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_reg_we_check.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_rom.core b/vendor/lowrisc_ip/ip/prim/prim_rom.core
index 86f188c9..0aa76a4e 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_rom.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_rom.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -17,8 +17,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_rom_adv.core b/vendor/lowrisc_ip/ip/prim/prim_rom_adv.core
index 249d6dd0..fea85f95 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_rom_adv.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_rom_adv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_rom_pkg.core b/vendor/lowrisc_ip/ip/prim/prim_rom_pkg.core
index 73f4c6c1..f8a827ce 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_rom_pkg.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_rom_pkg.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -7,7 +7,6 @@ name: "lowrisc:prim:rom_pkg"
 description: "Rom package"
 filesets:
   files_rtl:
-    depend:
     files:
       - rtl/prim_rom_pkg.sv
     file_type: systemVerilogSource
diff --git a/vendor/lowrisc_ip/ip/prim/prim_rst_sync.core b/vendor/lowrisc_ip/ip/prim/prim_rst_sync.core
index 7d207004..9657f877 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_rst_sync.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_rst_sync.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -22,7 +22,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: vlt
 
   files_ascentlint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_sec_anchor.core b/vendor/lowrisc_ip/ip/prim/prim_sec_anchor.core
index 28252848..12f57492 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_sec_anchor.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_sec_anchor.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_secded.core b/vendor/lowrisc_ip/ip/prim/prim_secded.core
index 13f89c20..38cb2d36 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_secded.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_secded.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -51,8 +51,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      # - lint/prim_secded.vlt
     file_type: vlt
 
   files_ascentlint_waiver:
@@ -75,4 +73,3 @@ targets:
       - tool_ascentlint  ? (files_ascentlint_waiver)
       - tool_veriblelint ? (files_veriblelint_waiver)
       - files_rtl
-
diff --git a/vendor/lowrisc_ip/ip/prim/prim_sha2.core b/vendor/lowrisc_ip/ip/prim/prim_sha2.core
new file mode 100644
index 00000000..18b27cb4
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/prim_sha2.core
@@ -0,0 +1,46 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim:sha2"
+description: "SHA-2 (configurable multi-mode and 256) engine"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:sha2_pkg
+    files:
+      - rtl/prim_sha2_pad.sv
+      - rtl/prim_sha2.sv
+      - rtl/prim_sha2_32.sv
+    file_type: systemVerilogSource
+
+  files_verilator_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+      - lint/prim_sha2.vlt
+    file_type: vlt
+
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+      - lint/prim_sha2.waiver
+
+  files_veriblelint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+      - lint/prim_sha2.vbl
+
+targets:
+  default:
+    filesets:
+      - tool_verilator   ? (files_verilator_waiver)
+      - tool_ascentlint  ? (files_ascentlint_waiver)
+      - tool_veriblelint ? (files_veriblelint_waiver)
+      - files_rtl
diff --git a/vendor/lowrisc_ip/ip/prim/prim_sha2_pkg.core b/vendor/lowrisc_ip/ip/prim/prim_sha2_pkg.core
new file mode 100644
index 00000000..c0e95b4b
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/prim_sha2_pkg.core
@@ -0,0 +1,38 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim:sha2_pkg"
+description: "HMAC and SHA-2 package"
+filesets:
+  files_rtl:
+    files:
+      - rtl/prim_sha2_pkg.sv
+    file_type: systemVerilogSource
+
+  files_verilator_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+      - lint/prim_sha2.waiver
+    file_type: waiver
+
+  files_veriblelint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+targets:
+  default:
+    filesets:
+      - tool_verilator   ? (files_verilator_waiver)
+      - tool_ascentlint  ? (files_ascentlint_waiver)
+      - tool_veriblelint ? (files_veriblelint_waiver)
+      - files_rtl
diff --git a/vendor/lowrisc_ip/ip/prim/prim_sparse_fsm.core b/vendor/lowrisc_ip/ip/prim/prim_sparse_fsm.core
index 385a9f56..4334c945 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_sparse_fsm.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_sparse_fsm.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_subreg.core b/vendor/lowrisc_ip/ip/prim/prim_subreg.core
index 9f326c2b..45d2a040 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_subreg.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_subreg.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_sum_tree.core b/vendor/lowrisc_ip/ip/prim/prim_sum_tree.core
index d984bd1d..fff6ce1e 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_sum_tree.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_sum_tree.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_trivium.core b/vendor/lowrisc_ip/ip/prim/prim_trivium.core
index 0c191502..eb05a453 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_trivium.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_trivium.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:prim:trivium:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/prim_usb_diff_rx.core b/vendor/lowrisc_ip/ip/prim/prim_usb_diff_rx.core
index f62fc029..c323df0a 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_usb_diff_rx.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_usb_diff_rx.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -16,7 +16,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: vlt
 
   files_ascentlint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_util.core b/vendor/lowrisc_ip/ip/prim/prim_util.core
index 5f224118..1af57c66 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_util.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_util.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_util_get_scramble_params.core b/vendor/lowrisc_ip/ip/prim/prim_util_get_scramble_params.core
index 57dc1ece..a6262872 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_util_get_scramble_params.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_util_get_scramble_params.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_util_memload.core b/vendor/lowrisc_ip/ip/prim/prim_util_memload.core
index 0371bd83..44af599d 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_util_memload.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_util_memload.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/prim_xnor2.core b/vendor/lowrisc_ip/ip/prim/prim_xnor2.core
index 360cb2c2..becb3067 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_xnor2.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_xnor2.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -16,7 +16,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: vlt
 
   files_ascentlint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_xor2.core b/vendor/lowrisc_ip/ip/prim/prim_xor2.core
index 07f486d5..7bf51d9f 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_xor2.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_xor2.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -16,7 +16,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: vlt
 
   files_ascentlint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim/prim_xoshiro256pp.core b/vendor/lowrisc_ip/ip/prim/prim_xoshiro256pp.core
index 258a4749..ff74e23c 100644
--- a/vendor/lowrisc_ip/ip/prim/prim_xoshiro256pp.core
+++ b/vendor/lowrisc_ip/ip/prim/prim_xoshiro256pp.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -25,8 +25,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim/primgen.core b/vendor/lowrisc_ip/ip/prim/primgen.core
index 3a143ee6..167f7965 100644
--- a/vendor/lowrisc_ip/ip/prim/primgen.core
+++ b/vendor/lowrisc_ip/ip/prim/primgen.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:prim:primgen:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_alert_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_alert_pkg.sv
index a3594b61..394c2bdb 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_alert_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_alert_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_alert_receiver.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_alert_receiver.sv
index 24631172..5ffc4a97 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_alert_receiver.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_alert_receiver.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -286,9 +286,13 @@ module prim_alert_receiver
   `ASSERT(InitReq_A, mubi4_test_true_strict(init_trig_i) &&
           !(state_q inside {InitReq, InitAckWait}) |=> send_init)
 
-  // ping request at input -> need to see encoded ping request
-  `ASSERT(PingRequest0_A, ##1 $rose(ping_req_i) && !state_q inside {InitReq, InitAckWait}
-      |=> $changed(alert_rx_o.ping_p))
+  // If there is a ping request on the input then we should see an encoded ping request. This is
+  // squashed if we are in state InitReq or InitAckWait (because we are still initialising), or if
+  // we see the init_trig_i signal go high (because it will start an initialisation).
+  `ASSERT(PingRequest0_A,
+          $rose(ping_req_i) |=> $changed(alert_rx_o.ping_p),
+          clk_i, !rst_ni || init_trig_i || state_q inside {InitReq, InitAckWait})
+
   // ping response implies it has been requested
   `ASSERT(PingResponse0_A, ping_ok_o |-> ping_pending_q)
   // correctly latch ping request
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_alert_sender.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_alert_sender.sv
index 88249b54..92887587 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_alert_sender.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_alert_sender.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_fixed.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_fixed.sv
index d9677dd2..efe122e2 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_fixed.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_fixed.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_ppc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_ppc.sv
index 17f3e19a..ddd70173 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_ppc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_ppc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -177,7 +177,7 @@ end
 // FPV-only assertions with symbolic variables
 `ifdef FPV_ON
   // symbolic variables
-  int unsigned k;
+  bit [IdxW-1:0] k;
   bit ReadyIsStable;
   bit ReqsAreStable;
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_tree.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_tree.sv
index 93d809e9..712eb8bf 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_tree.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_tree.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_tree_dup.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_tree_dup.sv
index 8ed2a7c2..79652a62 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_tree_dup.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_arbiter_tree_dup.sv
@@ -1,8 +1,8 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
-// This is a wrapper module that instantiates two prim_aribter_tree modules.
+// This is a wrapper module that instantiates two prim_arbiter_tree modules.
 // The reason for two is similar to modules such as prim_count/prim_lfsr where
 // we use spatial redundancy to ensure the arbitration results are not altered.
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv
index 540808b1..94c31188 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_dummy_macros.svh b/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_dummy_macros.svh
index c2a53133..c4421093 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_dummy_macros.svh
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_dummy_macros.svh
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_sec_cm.svh b/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_sec_cm.svh
index b9f077fa..a2fe824b 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_sec_cm.svh
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_sec_cm.svh
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -9,54 +9,75 @@
 
 `define _SEC_CM_ALERT_MAX_CYC 30
 
-// Helper macros
-`define ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, ERR_NAME_) \
-  `ASSERT(FpvSecCm``NAME_``, \
-          $rose(PRIM_HIER_.ERR_NAME_) && !(GATE_) \
-          |-> ##[0:MAX_CYCLES_] (ALERT_.alert_p)) \
-  `ifdef INC_ASSERT \
-  assign PRIM_HIER_.unused_assert_connected = 1'b1; \
-  `endif \
-  `ASSUME_FPV(``NAME_``TriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> \
-              PRIM_HIER_.ERR_NAME_ == 0 [*10])
-
-`define ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, ERR_NAME_, CLK_, RST_) \
-  `ASSERT(FpvSecCm``NAME_``, \
-          $rose(PRIM_HIER_.ERR_NAME_) && !(GATE_) \
-          |-> ##[0:MAX_CYCLES_] (ERR_), CLK_, RST_) \
-  `ifdef INC_ASSERT \
-  assign PRIM_HIER_.unused_assert_connected = 1'b1; \
+// When a named error signal rises, expect to see an associated error in at most MAX_CYCLES_ cycles.
+//
+// The NAME_ argument gets included in the name of the generated assertion, following an FpSecCm
+// prefix. The error signal should be at HIER_.ERR_NAME_ and the posedge is ignored if GATE_ is
+// true.
+//
+// This macro drives a magic "unused_assert_connected" signal, which is used for a static check to
+// ensure the assertions are in place.
+`define ASSERT_ERROR_TRIGGER_ERR(NAME_, HIER_, ERR_, GATE_, MAX_CYCLES_, ERR_NAME_, CLK_, RST_) \
+  `ASSERT(FpvSecCm``NAME_``,                                                                    \
+          $rose(HIER_.ERR_NAME_) && !(GATE_) |-> ##[0:MAX_CYCLES_] (ERR_),                      \
+          CLK_, RST_)                                                                           \
+  `ifdef INC_ASSERT                                                                             \
+    assign HIER_.unused_assert_connected = 1'b1;                                                \
   `endif
 
-// macros for security countermeasures that will trigger alert
-`define ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
-  `ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o)
-
-`define ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
-  `ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o)
-
-`define ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
-  `ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, unused_err_o)
-
-`define ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
-  `ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o)
+// When an error signal rises, expect to see the associated alert in at most MAX_CYCLE_ cycles.
+//
+// The NAME_, HIER_, GATE_, MAX_CYCLES_ and ERR_NAME_ arguments are the same as for
+// `ASSERT_ERROR_TRIGGER_ERR. The ALERT_ argument is the name of the alert that we expect to be
+// asserted.
+//
+// This macro adds an assumption that says the named error signal will stay low for the first 10
+// cycles after reset.
+`define ASSERT_ERROR_TRIGGER_ALERT(NAME_, HIER_, ALERT_, GATE_, MAX_CYCLES_, ERR_NAME_)    \
+  `ASSERT_ERROR_TRIGGER_ERR(NAME_, HIER_, (ALERT_.alert_p), GATE_, MAX_CYCLES_, ERR_NAME_, \
+                            `ASSERT_DEFAULT_CLK, `ASSERT_DEFAULT_RST)                      \
+  `ASSUME_FPV(``NAME_``TriggerAfterAlertInit_S,                                            \
+              $stable(rst_ni) == 0 |-> HIER_.ERR_NAME_ == 0 [*10])
+
+////////////////////////////////////////////////////////////////////////////////
+//
+// Assertions for CMs that trigger alerts
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`define ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(NAME_, HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
+  `ASSERT_ERROR_TRIGGER_ALERT(NAME_, HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o)
+
+`define ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ALERT(NAME_, HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
+  `ASSERT_ERROR_TRIGGER_ALERT(NAME_, HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o)
+
+`define ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(NAME_, HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
+  `ASSERT_ERROR_TRIGGER_ALERT(NAME_, HIER_, ALERT_, GATE_, MAX_CYCLES_, unused_err_o)
+
+`define ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
+  `ASSERT_ERROR_TRIGGER_ALERT(NAME_, HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o)
 
 `define ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, REG_TOP_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC) \
   `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, \
     REG_TOP_HIER_.u_prim_reg_we_check.u_prim_onehot_check, ALERT_, GATE_, MAX_CYCLES_)
 
-// macros for security countermeasures that will trigger other errors
-`define ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \
-  `ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, unused_err_o, CLK_, RST_)
+////////////////////////////////////////////////////////////////////////////////
+//
+// Assertions for CMs that trigger some other form of error
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`define ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(NAME_, HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \
+  `ASSERT_ERROR_TRIGGER_ERR(NAME_, HIER_, ERR_, GATE_, MAX_CYCLES_, unused_err_o, CLK_, RST_)
 
-`define ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \
-  `ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)
+`define ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(NAME_, HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \
+  `ASSERT_ERROR_TRIGGER_ERR(NAME_, HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)
 
-`define ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \
-  `ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)
+`define ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR(NAME_, HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \
+  `ASSERT_ERROR_TRIGGER_ERR(NAME_, HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)
 
-`define ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \
-  `ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)
+`define ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \
+  `ASSERT_ERROR_TRIGGER_ERR(NAME_, HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)
 
 `define ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(NAME_, REG_TOP_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \
   `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, \
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_standard_macros.svh b/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_standard_macros.svh
index bfa07380..9dead6cf 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_standard_macros.svh
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_standard_macros.svh
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -41,12 +41,14 @@
   end                                                                                \
 
 `define ASSERT_FINAL(__name, __prop)                                         \
+`ifndef FPV_ON                                                               \
   final begin                                                                \
     __name: assert (__prop || $test$plusargs("disable_assert_final_checks")) \
       else begin                                                             \
         `ASSERT_ERROR(__name)                                                \
       end                                                                    \
-  end
+  end                                                                        \
+`endif
 
 `define ASSERT_AT_RESET(__name, __prop, __rst = `ASSERT_DEFAULT_RST)         \
   // `__rst` is active-high for these macros, so trigger on its posedge.     \
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_yosys_macros.svh b/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_yosys_macros.svh
index 81102ec8..48a0473d 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_yosys_macros.svh
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_yosys_macros.svh
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_blanker.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_blanker.sv
index 2253da31..1589b7ba 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_blanker.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_blanker.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_cdc_rand_delay.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_cdc_rand_delay.sv
index 0318e2c1..acb79ae3 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_cdc_rand_delay.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_cdc_rand_delay.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_cipher_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_cipher_pkg.sv
index 742c9253..3c48f397 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_cipher_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_cipher_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_gating_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_gating_sync.sv
index bcc8f75f..76dd6eb0 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_gating_sync.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_gating_sync.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_gp_mux2.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_gp_mux2.sv
index f4d78602..ac259ab8 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_gp_mux2.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_gp_mux2.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -28,7 +28,7 @@ assign stage_d = {sel_i & !stage_q[0], !sel_i & !stage_q[1]};
 
 generate
   genvar i;
-  for (i = 0; i < 2; i = i++) begin: gen_two_flops
+  for (i = 0; i < 2; i++) begin: gen_two_flops
     always_ff @(posedge clk_gp[i] or negedge rst_ni) begin: stage1
       if (!rst_ni) begin
         intq[i] <= 1'b0;
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_meas.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_meas.sv
index e2c2b7f2..45c0ec2e 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_meas.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_meas.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_timeout.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_timeout.sv
index 4b02ee3b..b4c972bb 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_timeout.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_clock_timeout.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_count.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_count.sv
index a485d7fd..c0e77647 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_count.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_count.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -16,31 +16,47 @@
 //        (i.e. 2**Width-1-set_cnt_i). Set has priority over increment and decrement.
 // incr_en_i: Increments the primary counter by step_i, and decrements the secondary by step_i.
 // decr_en_i: Decrements the primary counter by step_i, and increments the secondary by step_i.
+// commit_i: Counter changes only take effect when `commit_i` is set. This does not effect the
+//           `cnt_after_commit_o` output which gives the next counter state if the change is
+//           committed.
 //
 // Note that if both incr_en_i and decr_en_i are asserted at the same time, the counter remains
 // unchanged. The counter is also protected against under- and overflows.
 
 `include "prim_assert.sv"
 
-module prim_count #(
-  parameter int Width = 2,
+module prim_count
+  import prim_count_pkg::*;
+#(
+  parameter int               Width = 2,
   // Can be used to reset the counter to a different value than 0, for example when
   // the counter is used as a down-counter.
   parameter logic [Width-1:0] ResetValue = '0,
   // This should only be disabled in special circumstances, for example
   // in non-comportable IPs where an error does not trigger an alert.
-  parameter bit EnableAlertTriggerSVA = 1
+  parameter bit               EnableAlertTriggerSVA = 1,
+
+  // We have some assertions below with preconditions that depend on particular input actions
+  // (clear, set, incr, decr). If the design has instantiated prim_count with one of these actions
+  // tied to zero, the preconditions for the associated assertions will not be satisfiable. The
+  // result is an unreachable item, which we treat as a failed assertion in the report.
+  //
+  // To avoid this, we the instantiation to specify the actions which might happen. If this is not
+  // '1, we will have an assertion which assert the corresponding action is never triggered. We can
+  // then use this to avoid the unreachable assertions.
+  parameter action_mask_t     PossibleActions = {$bits(action_mask_t){1'b1}}
 ) (
   input clk_i,
   input rst_ni,
   input clr_i,
   input set_i,
-  input [Width-1:0] set_cnt_i,         // Set value for the counter.
+  input [Width-1:0] set_cnt_i,                 // Set value for the counter.
   input incr_en_i,
   input decr_en_i,
-  input [Width-1:0] step_i,            // Increment/decrement step when enabled.
-  output logic [Width-1:0] cnt_o,      // Current counter state
-  output logic [Width-1:0] cnt_next_o, // Next counter state
+  input [Width-1:0] step_i,                    // Increment/decrement step when enabled.
+  input commit_i,
+  output logic [Width-1:0] cnt_o,              // Current counter state
+  output logic [Width-1:0] cnt_after_commit_o, // Next counter state if committed
   output logic err_o
 );
 
@@ -53,10 +69,14 @@ module prim_count #(
   localparam logic [NumCnt-1:0][Width-1:0] ResetValues = {{Width{1'b1}} - ResetValue, // secondary
                                                           ResetValue};                // primary
 
-  logic [NumCnt-1:0][Width-1:0] cnt_d, cnt_q, fpv_force;
+  logic [NumCnt-1:0][Width-1:0] cnt_d, cnt_d_committed, cnt_q;
 
-`ifndef FPV_SEC_CM_ON
-  // This becomes a free variable in FPV.
+  // The fpv_force signal can be used in FPV runs to make the internal counters (cnt_q) jump
+  // unexpectedly. We only want to use this mechanism when we're doing FPV on prim_count itself. In
+  // that situation, we will have the PrimCountFpv define and wish to leave fpv_force undriven so
+  // that it becomes a free variable in FPV. In any other situation, we drive the signal with zero.
+  logic [NumCnt-1:0][Width-1:0] fpv_force;
+`ifndef PrimCountFpv
   assign fpv_force = '0;
 `endif
 
@@ -100,6 +120,8 @@ module prim_count #(
                       (set_i)  ? set_val        :
                       (cnt_en) ? cnt_sat        : cnt_q[k];
 
+    assign cnt_d_committed[k] = commit_i ? cnt_d[k] : cnt_q[k];
+
     logic [Width-1:0] cnt_unforced_q;
     prim_flop #(
       .Width(Width),
@@ -107,7 +129,7 @@ module prim_count #(
     ) u_cnt_flop (
       .clk_i,
       .rst_ni,
-      .d_i(cnt_d[k]),
+      .d_i(cnt_d_committed[k]),
       .q_o(cnt_unforced_q)
     );
 
@@ -121,8 +143,8 @@ module prim_count #(
   assign err_o = (sum != {1'b0, {Width{1'b1}}});
 
   // Output count values
-  assign cnt_o      = cnt_q[0];
-  assign cnt_next_o = cnt_d[0];
+  assign cnt_o              = cnt_q[0];
+  assign cnt_after_commit_o = cnt_d[0];
 
   ////////////////
   // Assertions //
@@ -150,105 +172,120 @@ module prim_count #(
   //VCS coverage on
   // pragma coverage on
 
+  if (!(PossibleActions & Clr)) begin : g_check_no_clr
+    `ASSERT(ClrNeverTrue_A, clr_i !== 1'b1)
+  end
+  if (!(PossibleActions & Set)) begin : g_check_no_set
+    `ASSERT(SetNeverTrue_A, set_i !== 1'b1)
+  end
+  if (!(PossibleActions & Incr)) begin : g_check_no_incr
+    `ASSERT(IncrNeverTrue_A, incr_en_i !== 1'b1)
+  end
+  if (!(PossibleActions & Decr)) begin : g_check_no_decr
+    `ASSERT(DecrNeverTrue_A, decr_en_i !== 1'b1)
+  end
+
   // Cnt next
   `ASSERT(CntNext_A,
       rst_ni
       |=>
-      cnt_o == $past(cnt_next_o),
+      $past(!commit_i) || (cnt_o == $past(cnt_after_commit_o)),
       clk_i, err_o || fpv_err_present || !rst_ni)
 
   // Clear
-  `ASSERT(ClrFwd_A,
-      rst_ni && clr_i
-      |=>
-      (cnt_o == ResetValue) &&
-      (cnt_q[1] == ({Width{1'b1}} - ResetValue)),
-      clk_i, err_o || fpv_err_present || !rst_ni)
-  `ASSERT(ClrBkwd_A,
-      rst_ni && !(incr_en_i || decr_en_i || set_i) ##1
-      $changed(cnt_o) && $changed(cnt_q[1])
-      |->
-      $past(clr_i),
-      clk_i, err_o || fpv_err_present || !rst_ni)
+  if (PossibleActions & Clr) begin : g_check_clr_fwd_a
+    `ASSERT(ClrFwd_A,
+            rst_ni && commit_i && clr_i
+            |=>
+            (cnt_o == ResetValue) &&
+            (cnt_q[1] == ({Width{1'b1}} - ResetValue)),
+            clk_i, err_o || fpv_err_present || !rst_ni)
+  end
 
   // Set
-  `ASSERT(SetFwd_A,
-      rst_ni && set_i && !clr_i
-      |=>
-      (cnt_o == $past(set_cnt_i)) &&
-      (cnt_q[1] == ({Width{1'b1}} - $past(set_cnt_i))),
-      clk_i, err_o || fpv_err_present || !rst_ni)
-  `ASSERT(SetBkwd_A,
-      rst_ni && !(incr_en_i || decr_en_i || clr_i) ##1
-      $changed(cnt_o) && $changed(cnt_q[1])
-      |->
-      $past(set_i),
-      clk_i, err_o || fpv_err_present || !rst_ni)
+  if (PossibleActions & Set) begin : g_check_set_fwd_a
+    `ASSERT(SetFwd_A,
+        rst_ni && commit_i && set_i && !clr_i
+        |=>
+        (cnt_o == $past(set_cnt_i)) &&
+        (cnt_q[1] == ({Width{1'b1}} - $past(set_cnt_i))),
+        clk_i, err_o || fpv_err_present || !rst_ni)
+  end
 
   // Do not count if both increment and decrement are asserted.
-  `ASSERT(IncrDecrUpDnCnt_A,
-      rst_ni && incr_en_i && decr_en_i && !(clr_i || set_i)
-      |=>
-      $stable(cnt_o) && $stable(cnt_q[1]),
-      clk_i, err_o || fpv_err_present || !rst_ni)
+  if ((PossibleActions & Incr) && (PossibleActions & Decr)) begin : g_check_inc_and_dec
+    `ASSERT(IncrDecrUpDnCnt_A,
+        rst_ni && incr_en_i && decr_en_i && !(clr_i || set_i)
+        |=>
+        $stable(cnt_o) && $stable(cnt_q[1]),
+        clk_i, err_o || fpv_err_present || !rst_ni)
+  end
 
-  // Up counter
-  `ASSERT(IncrUpCnt_A,
-      rst_ni && incr_en_i && !(clr_i || set_i || decr_en_i)
-      |=>
-      cnt_o == min($past(cnt_o) + $past({2'b0, step_i}), {2'b0, {Width{1'b1}}}),
-      clk_i, err_o || fpv_err_present || !rst_ni)
-  `ASSERT(IncrDnCnt_A,
-      rst_ni && incr_en_i && !(clr_i || set_i || decr_en_i)
-      |=>
-      cnt_q[1] == max($past(signed'({2'b0, cnt_q[1]})) - $past({2'b0, step_i}), '0),
-      clk_i, err_o || fpv_err_present || !rst_ni)
-  `ASSERT(UpCntIncrStable_A,
-      incr_en_i && !(clr_i || set_i || decr_en_i) &&
-      cnt_o == {Width{1'b1}}
-      |=>
-      $stable(cnt_o),
-      clk_i, err_o || fpv_err_present || !rst_ni)
-  `ASSERT(UpCntDecrStable_A,
-      decr_en_i && !(clr_i || set_i || incr_en_i) &&
-      cnt_o == '0
-      |=>
-      $stable(cnt_o),
-      clk_i, err_o || fpv_err_present || !rst_ni)
+  // Increment
+  if ((PossibleActions & Incr)) begin : g_check_incr
+    `ASSERT(IncrUpCnt_A,
+        rst_ni && incr_en_i && !(clr_i || set_i || decr_en_i) && commit_i
+        |=>
+        cnt_o == min($past(cnt_o) + $past({2'b0, step_i}), {2'b0, {Width{1'b1}}}),
+        clk_i, err_o || fpv_err_present || !rst_ni)
+    `ASSERT(IncrDnCnt_A,
+        rst_ni && incr_en_i && !(clr_i || set_i || decr_en_i) && commit_i
+        |=>
+        cnt_q[1] == max($past(signed'({2'b0, cnt_q[1]})) - $past({2'b0, step_i}), '0),
+        clk_i, err_o || fpv_err_present || !rst_ni)
+    `ASSERT(UpCntIncrStable_A,
+        incr_en_i && !(clr_i || set_i || decr_en_i) &&
+        cnt_o == {Width{1'b1}}
+        |=>
+        $stable(cnt_o),
+        clk_i, err_o || fpv_err_present || !rst_ni)
+    `ASSERT(DnCntIncrStable_A,
+        rst_ni && incr_en_i && !(clr_i || set_i || decr_en_i) &&
+        cnt_q[1] == '0
+        |=>
+        $stable(cnt_q[1]),
+        clk_i, err_o || fpv_err_present || !rst_ni)
+  end
 
-  // Down counter
-  `ASSERT(DecrUpCnt_A,
-      rst_ni && decr_en_i && !(clr_i || set_i || incr_en_i)
-      |=>
-      cnt_o == max($past(signed'({2'b0, cnt_o})) - $past({2'b0, step_i}), '0),
-      clk_i, err_o || fpv_err_present || !rst_ni)
-  `ASSERT(DecrDnCnt_A,
-      rst_ni && decr_en_i && !(clr_i || set_i || incr_en_i)
-      |=>
-      cnt_q[1] == min($past(cnt_q[1]) + $past({2'b0, step_i}), {2'b0, {Width{1'b1}}}),
-      clk_i, err_o || fpv_err_present || !rst_ni)
-  `ASSERT(DnCntIncrStable_A,
-      rst_ni && incr_en_i && !(clr_i || set_i || decr_en_i) &&
-      cnt_q[1] == '0
-      |=>
-      $stable(cnt_q[1]),
-      clk_i, err_o || fpv_err_present || !rst_ni)
-  `ASSERT(DnCntDecrStable_A,
-      rst_ni && decr_en_i && !(clr_i || set_i || incr_en_i) &&
-      cnt_q[1] == {Width{1'b1}}
-      |=>
-      $stable(cnt_q[1]),
-      clk_i, err_o || fpv_err_present || !rst_ni)
+  // Decrement
+  if ((PossibleActions & Decr)) begin : g_check_decr
+    `ASSERT(DecrUpCnt_A,
+        rst_ni && decr_en_i && !(clr_i || set_i || incr_en_i) && commit_i
+        |=>
+        cnt_o == max($past(signed'({2'b0, cnt_o})) - $past({2'b0, step_i}), '0),
+        clk_i, err_o || fpv_err_present || !rst_ni)
+    `ASSERT(DecrDnCnt_A,
+        rst_ni && decr_en_i && !(clr_i || set_i || incr_en_i) && commit_i
+        |=>
+        cnt_q[1] == min($past(cnt_q[1]) + $past({2'b0, step_i}), {2'b0, {Width{1'b1}}}),
+        clk_i, err_o || fpv_err_present || !rst_ni)
+    `ASSERT(UpCntDecrStable_A,
+        decr_en_i && !(clr_i || set_i || incr_en_i) &&
+        cnt_o == '0
+        |=>
+        $stable(cnt_o),
+        clk_i, err_o || fpv_err_present || !rst_ni)
+    `ASSERT(DnCntDecrStable_A,
+        rst_ni && decr_en_i && !(clr_i || set_i || incr_en_i) &&
+        cnt_q[1] == {Width{1'b1}}
+        |=>
+        $stable(cnt_q[1]),
+        clk_i, err_o || fpv_err_present || !rst_ni)
+  end
+
+  // A backwards check for count changes. This asserts that the count only changes if one of the
+  // inputs that should tell it to change (clear, set, increment, decrement) does so.
+  `ASSERT(ChangeBackward_A,
+          rst_ni ##1 $changed(cnt_o) && $changed(cnt_q[1])
+          |->
+          $past(clr_i || set_i || (commit_i && (incr_en_i || decr_en_i))),
+          clk_i, err_o || fpv_err_present || !rst_ni)
 
-  // Error
-  `ASSERT(CntErrForward_A,
-      (cnt_q[1] + cnt_q[0]) != {Width{1'b1}}
-      |->
-      err_o)
-  `ASSERT(CntErrBackward_A,
-      err_o
-      |->
-      (cnt_q[1] + cnt_q[0]) != {Width{1'b1}})
+  // Check that count errors are reported properly in err_o
+  `ASSERT(CntErrReported_A, ((cnt_q[1] + cnt_q[0]) != {Width{1'b1}}) == err_o)
+ `ifdef PrimCountFpv
+  `COVER(CntErr_C, err_o)
+ `endif
 
   // This logic that will be assign to one, when user adds macro
   // ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT to check the error with alert, in case that prim_count
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_count_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_count_pkg.sv
new file mode 100644
index 00000000..f87139fc
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_count_pkg.sv
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package prim_count_pkg;
+
+  // An enum that names the possible actions that the inputs might ask for. See the PossibleActions
+  // parameter in prim_count for how this is used.
+  typedef logic [3:0] action_mask_t;
+  typedef enum action_mask_t {Clr  = 4'h1,
+                              Set  = 4'h2,
+                              Incr = 4'h4,
+                              Decr = 4'h8} action_e;
+
+endpackage : prim_count_pkg
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_crc32.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_crc32.sv
index 762fd48c..f077c077 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_crc32.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_crc32.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_diff_decode.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_diff_decode.sv
index caf32199..8c2804cb 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_diff_decode.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_diff_decode.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -182,8 +182,16 @@ module prim_diff_decode #(
     // one reg for edge detection
     assign diff_pd = diff_pi;
 
-    // incorrect encoding -> signal integrity issue
-    assign sigint_o = ~(diff_pi ^ diff_ni);
+    // Raise a signal integrity error when the differential signals have equal values.  This is
+    // implemented with a `prim_xnor2` instead of behavioral code to prevent the synthesis tool from
+    // optimizing away combinational logic on the complementary differential signals.
+    prim_xnor2 #(
+      .Width (1)
+    ) u_xnor2_sigint (
+      .in0_i (diff_pi),
+      .in1_i (diff_ni),
+      .out_o (sigint_o)
+    );
 
     assign level_o = (sigint_o) ? level_q : diff_pi;
     assign level_d = level_o;
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_dom_and_2share.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_dom_and_2share.sv
index b45db9ae..ac3c5dd9 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_dom_and_2share.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_dom_and_2share.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_double_lfsr.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_double_lfsr.sv
index 8fce7b76..68cc98de 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_double_lfsr.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_double_lfsr.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_edge_detector.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_edge_detector.sv
index 2b0a92fb..94b45cd7 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_edge_detector.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_edge_detector.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_edn_req.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_edn_req.sv
index 70efb2e5..f0d79ffd 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_edn_req.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_edn_req.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_pkg.sv
index 8cd9c4ec..721b0d48 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv
index 24aeb4ca..2f01b93f 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_receiver.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -97,13 +97,16 @@ module prim_esc_receiver
   logic timeout_cnt_set, timeout_cnt_en;
   logic [TimeoutCntDw-1:0] timeout_cnt;
   assign timeout_cnt_set = (ping_en && !(&timeout_cnt));
-  assign timeout_cnt_en = ((timeout_cnt > '0) && !(&timeout_cnt));
+  assign timeout_cnt_en = (timeout_cnt > '0);
 
   prim_count #(
     .Width(TimeoutCntDw),
     // The escalation receiver behaves differently than other comportable IP. I.e., instead of
     // sending out an alert signal, this condition is handled internally in the alert handler.
-    .EnableAlertTriggerSVA(0)
+    .EnableAlertTriggerSVA(0),
+    // Pass a parameter to disable coverage for some assertions that are unreachable because
+    // clr_i and decr_en_i are tied to zero.
+    .PossibleActions(prim_count_pkg::Set | prim_count_pkg::Incr)
   ) u_prim_count (
     .clk_i,
     .rst_ni,
@@ -113,8 +116,9 @@ module prim_esc_receiver
     .incr_en_i(timeout_cnt_en),
     .decr_en_i(1'b0),
     .step_i(TimeoutCntDw'(1)),
+    .commit_i(1'b1),
     .cnt_o(timeout_cnt),
-    .cnt_next_o(),
+    .cnt_after_commit_o(),
     .err_o(timeout_cnt_error)
   );
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_sender.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_sender.sv
index 7987e6cc..fba0bab8 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_sender.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_esc_sender.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_async.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_async.sv
index 0edebc76..bbdfcf90 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_async.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_async.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_async_simple.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_async_simple.sv
index 5dbeed03..76ee140d 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_async_simple.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_async_simple.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_async_sram_adapter.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_async_sram_adapter.sv
index 4d4911c9..5d6462d7 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_async_sram_adapter.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_async_sram_adapter.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_sync.sv
index 5e9ee9c3..6fc3560c 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_sync.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_sync.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -40,7 +40,7 @@ module prim_fifo_sync #(
 
     assign depth_o = 1'b0; //output is meaningless
 
-    // devie facing
+    // device facing
     assign rvalid_o = wvalid_i;
     assign rdata_o = wdata_i;
 
@@ -58,11 +58,10 @@ module prim_fifo_sync #(
   // Normal FIFO construction
   end else begin : gen_normal_fifo
 
-    localparam int unsigned PTRV_W    = prim_util_pkg::vbits(Depth);
-    localparam int unsigned PTR_WIDTH = PTRV_W+1;
+    localparam int unsigned PtrW = prim_util_pkg::vbits(Depth);
 
-    logic [PTR_WIDTH-1:0] fifo_wptr, fifo_rptr;
-    logic                 fifo_incr_wptr, fifo_incr_rptr, fifo_empty;
+    logic [PtrW-1:0] fifo_wptr, fifo_rptr;
+    logic            fifo_incr_wptr, fifo_incr_rptr, fifo_empty;
 
     // module under reset flag
     logic under_rst;
@@ -74,33 +73,15 @@ module prim_fifo_sync #(
       end
     end
 
-    // create the write and read pointers
-    logic  full, empty;
-    logic  wptr_msb;
-    logic  rptr_msb;
-    logic  [PTRV_W-1:0] wptr_value;
-    logic  [PTRV_W-1:0] rptr_value;
-
-    assign wptr_msb = fifo_wptr[PTR_WIDTH-1];
-    assign rptr_msb = fifo_rptr[PTR_WIDTH-1];
-    assign wptr_value = fifo_wptr[0+:PTRV_W];
-    assign rptr_value = fifo_rptr[0+:PTRV_W];
-    assign depth_o = (full)                 ? DepthW'(Depth) :
-                     (wptr_msb == rptr_msb) ? DepthW'(wptr_value) - DepthW'(rptr_value) :
-                     (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_value)) ;
-
-    assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
-    assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
+    logic empty;
 
     // full and not ready for write are two different concepts.
     // The latter can be '0' when under reset, while the former is an indication that no more
     // entries can be written.
-    assign wready_o = ~full & ~under_rst;
-    assign full_o   = full;
+    assign wready_o = ~full_o & ~under_rst;
     assign rvalid_o = ~empty & ~under_rst;
 
     prim_fifo_sync_cnt #(
-      .Width(PTR_WIDTH),
       .Depth(Depth),
       .Secure(Secure)
     ) u_fifo_cnt (
@@ -111,40 +92,13 @@ module prim_fifo_sync #(
       .incr_rptr_i(fifo_incr_rptr),
       .wptr_o(fifo_wptr),
       .rptr_o(fifo_rptr),
+      .full_o,
+      .empty_o(fifo_empty),
+      .depth_o,
       .err_o
     );
-
-    //always_ff @(posedge clk_i or negedge rst_ni) begin
-    //  if (!rst_ni) begin
-    //    fifo_wptr <= {(PTR_WIDTH){1'b0}};
-    //  end else if (clr_i) begin
-    //    fifo_wptr <= {(PTR_WIDTH){1'b0}};
-    //  end else if (fifo_incr_wptr) begin
-    //    if (fifo_wptr[PTR_WIDTH-2:0] == (PTR_WIDTH-1)'(Depth-1)) begin
-    //      fifo_wptr <= {~fifo_wptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}};
-    //    end else begin
-    //      fifo_wptr <= fifo_wptr + {{(PTR_WIDTH-1){1'b0}},1'b1};
-    //    end
-    //  end
-    //end
-    //
-    //always_ff @(posedge clk_i or negedge rst_ni) begin
-    //  if (!rst_ni) begin
-    //    fifo_rptr <= {(PTR_WIDTH){1'b0}};
-    //  end else if (clr_i) begin
-    //    fifo_rptr <= {(PTR_WIDTH){1'b0}};
-    //  end else if (fifo_incr_rptr) begin
-    //    if (fifo_rptr[PTR_WIDTH-2:0] == (PTR_WIDTH-1)'(Depth-1)) begin
-    //      fifo_rptr <= {~fifo_rptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}};
-    //    end else begin
-    //      fifo_rptr <= fifo_rptr + {{(PTR_WIDTH-1){1'b0}},1'b1};
-    //    end
-    //  end
-    //end
-
-    assign  full       = (fifo_wptr == (fifo_rptr ^ {1'b1,{(PTR_WIDTH-1){1'b0}}}));
-    assign  fifo_empty = (fifo_wptr ==  fifo_rptr);
-
+    assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
+    assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
 
     // the generate blocks below are needed to avoid lint errors due to array indexing
     // in the where the fifo only has one storage element
@@ -157,13 +111,17 @@ module prim_fifo_sync #(
         if (fifo_incr_wptr) begin
           storage[0] <= wdata_i;
         end
+
+      logic unused_ptrs;
+      assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
+
     // fifo with more than one storage element
     end else begin : gen_depth_gt1
-      assign storage_rdata = storage[fifo_rptr[PTR_WIDTH-2:0]];
+      assign storage_rdata = storage[fifo_rptr];
 
       always_ff @(posedge clk_i)
         if (fifo_incr_wptr) begin
-          storage[fifo_wptr[PTR_WIDTH-2:0]] <= wdata_i;
+          storage[fifo_wptr] <= wdata_i;
         end
     end
 
@@ -177,7 +135,7 @@ module prim_fifo_sync #(
     end
 
     if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
-      assign rdata_o = empty ? 'b0 : rdata_int;
+      assign rdata_o = empty ? Width'(0) : rdata_int;
     end else begin : gen_no_output_zero
       assign rdata_o = rdata_int;
     end
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_sync_cnt.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_sync_cnt.sv
index ec69515b..1f0670dd 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_sync_cnt.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_fifo_sync_cnt.sv
@@ -1,69 +1,108 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
-// Generic synchronous fifo for use in a variety of devices.
+// Read and write pointer logic for synchronous FIFOs
 
 `include "prim_assert.sv"
 
 module prim_fifo_sync_cnt #(
-  parameter int Depth = 4,
-  parameter int Width = 16,
-  parameter bit Secure = 1'b0
+  // Depth of the FIFO, i.e., maximum number of entries the FIFO can contain
+  parameter int unsigned Depth = 4,
+  // Whether to instantiate hardened counters
+  parameter bit Secure = 1'b0,
+  // Width of the read and write pointers for the FIFO
+  localparam int unsigned PtrW = prim_util_pkg::vbits(Depth),
+  // Width of the 'current depth' output
+  localparam int unsigned DepthW = prim_util_pkg::vbits(Depth+1)
 ) (
   input clk_i,
   input rst_ni,
   input clr_i,
   input incr_wptr_i,
   input incr_rptr_i,
-  output logic [Width-1:0] wptr_o,
-  output logic [Width-1:0] rptr_o,
+  // Write and read pointers.  Value range: [0, Depth-1]
+  output logic [PtrW-1:0] wptr_o,
+  output logic [PtrW-1:0] rptr_o,
+  output logic full_o,
+  output logic empty_o,
+  // Current depth of the FIFO, i.e., number of entries the FIFO currently contains.
+  // Value range: [0, Depth]
+  output logic [DepthW-1:0] depth_o,
   output logic err_o
 );
 
-  logic wptr_wrap;
-  logic [Width-1:0] wptr_wrap_cnt;
-  logic rptr_wrap;
-  logic [Width-1:0] rptr_wrap_cnt;
+  // Internal 'wrap' pointers that have an extra leading bit to account for wraparounds.
+  localparam int unsigned WrapPtrW = PtrW + 1;
+  logic [WrapPtrW-1:0] wptr_wrap_cnt_q, wptr_wrap_set_cnt,
+                       rptr_wrap_cnt_q, rptr_wrap_set_cnt;
 
-  assign wptr_wrap = incr_wptr_i & (wptr_o[Width-2:0] == unsigned'((Width-1)'(Depth-1)));
-  assign rptr_wrap = incr_rptr_i & (rptr_o[Width-2:0] == unsigned'((Width-1)'(Depth-1)));
+  // Derive real read and write pointers by truncating the internal 'wrap' pointers.
+  assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
+  assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
 
-  assign wptr_wrap_cnt = {~wptr_o[Width-1],{(Width-1){1'b0}}};
-  assign rptr_wrap_cnt = {~rptr_o[Width-1],{(Width-1){1'b0}}};
+  // Extract the MSB of the 'wrap' pointers.
+  logic wptr_wrap_msb, rptr_wrap_msb;
+  assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
+  assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
+
+  // Wrap pointers when they have reached the maximum value and are about to get incremented.
+  logic wptr_wrap_set, rptr_wrap_set;
+  assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
+  assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
+
+  // When wrapping, invert the MSB and reset all lower bits to zero.
+  assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
+  assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
+
+  // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
+  assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
+  // Empty when both 'wrap' counters are equal in all bits including the MSB.
+  assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
+
+  // The current depth is equal to:
+  // - when full: the maximum depth;
+  // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
+  // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
+  //   of the real pointers.
+  assign depth_o = full_o                         ? DepthW'(Depth) :
+                   wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
+                   DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
 
   if (Secure) begin : gen_secure_ptrs
     logic wptr_err;
     prim_count #(
-      .Width(Width)
+      .Width(WrapPtrW)
     ) u_wptr (
       .clk_i,
       .rst_ni,
       .clr_i,
-      .set_i(wptr_wrap),
-      .set_cnt_i(wptr_wrap_cnt),
+      .set_i(wptr_wrap_set),
+      .set_cnt_i(wptr_wrap_set_cnt),
       .incr_en_i(incr_wptr_i),
       .decr_en_i(1'b0),
-      .step_i(Width'(1'b1)),
-      .cnt_o(wptr_o),
-      .cnt_next_o(),
+      .step_i(WrapPtrW'(1'b1)),
+      .commit_i(1'b1),
+      .cnt_o(wptr_wrap_cnt_q),
+      .cnt_after_commit_o(),
       .err_o(wptr_err)
     );
 
     logic rptr_err;
     prim_count #(
-      .Width(Width)
+      .Width(WrapPtrW)
     ) u_rptr (
       .clk_i,
       .rst_ni,
       .clr_i,
-      .set_i(rptr_wrap),
-      .set_cnt_i(rptr_wrap_cnt),
+      .set_i(rptr_wrap_set),
+      .set_cnt_i(rptr_wrap_set_cnt),
       .incr_en_i(incr_rptr_i),
       .decr_en_i(1'b0),
-      .step_i(Width'(1'b1)),
-      .cnt_o(rptr_o),
-      .cnt_next_o(),
+      .step_i(WrapPtrW'(1'b1)),
+      .commit_i(1'b1),
+      .cnt_o(rptr_wrap_cnt_q),
+      .cnt_after_commit_o(),
       .err_o(rptr_err)
     );
 
@@ -72,31 +111,29 @@ module prim_fifo_sync_cnt #(
   end else begin : gen_normal_ptrs
     always_ff @(posedge clk_i or negedge rst_ni) begin
       if (!rst_ni) begin
-        wptr_o <= {(Width){1'b0}};
+        wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
       end else if (clr_i) begin
-        wptr_o <= {(Width){1'b0}};
-      end else if (wptr_wrap) begin
-        wptr_o <= wptr_wrap_cnt;
+        wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
+      end else if (wptr_wrap_set) begin
+        wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
       end else if (incr_wptr_i) begin
-        wptr_o <= wptr_o + {{(Width-1){1'b0}},1'b1};
+        wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
       end
     end
 
     always_ff @(posedge clk_i or negedge rst_ni) begin
       if (!rst_ni) begin
-        rptr_o <= {(Width){1'b0}};
+        rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
       end else if (clr_i) begin
-        rptr_o <= {(Width){1'b0}};
-      end else if (rptr_wrap) begin
-         rptr_o <= rptr_wrap_cnt;
+        rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
+      end else if (rptr_wrap_set) begin
+        rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
       end else if (incr_rptr_i) begin
-         rptr_o <= rptr_o + {{(Width-1){1'b0}},1'b1};
+        rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
       end
     end
 
     assign err_o = '0;
   end
 
-
-
 endmodule // prim_fifo_sync_cnt
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_filter.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_filter.sv
index a9d5dcdc..9878e5a8 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_filter.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_filter.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -70,4 +70,3 @@ module prim_filter #(
   assign filter_o = enable_i ? stored_value_q : filter_synced;
 
 endmodule
-
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_filter_ctr.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_filter_ctr.sv
index 435b1615..1a392057 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_filter_ctr.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_filter_ctr.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -79,4 +79,3 @@ module prim_filter_ctr #(
   assign filter_o = enable_i ? stored_value_q : filter_synced;
 
 endmodule
-
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_flop_2sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_flop_2sync.sv
index 7ff3c76a..5b469286 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_flop_2sync.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_flop_2sync.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_flop_macros.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_flop_macros.sv
index edae459a..ce59bb29 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_flop_macros.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_flop_macros.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_gate_gen.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_gate_gen.sv
index dac761fd..01cf1813 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_gate_gen.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_gate_gen.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_gf_mult.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_gf_mult.sv
index aa47c22e..f8f34eea 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_gf_mult.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_gf_mult.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_intr_hw.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_intr_hw.sv
index 1813194e..e2a6e438 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_intr_hw.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_intr_hw.sv
@@ -1,27 +1,42 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
-// Primitive interrupt handler. This assumes the existence of three
-// controller registers: INTR_ENABLE, INTR_STATE, INTR_TEST.
-// This module can be instantiated once per interrupt field, or
-// "bussified" with all fields of the interrupt vector.
+// Primitive block for generating CIP interrupts in peripherals.
+//
+// This block generates both the level-triggered wired interrupt signal intr_o and also updates
+// the value of the INTR_STATE register. Together, the signal and register make up the two
+// externally-visible indications of of the interrupt state.
+//
+// This assumes the existence of three external controller registers, which
+// interface with this module via the standard reggen reg2hw/hw2reg signals. The 3 registers are:
+// - INTR_ENABLE : enables/masks the output of INTR_STATE as the intr_o signal
+// - INTR_STATE  : the current state of the interrupt (may be RO or W1C depending on "IntrT")
+// - INTR_TEST   : sw-access-only register which asserts the interrupt for testing purposes
 
 module prim_intr_hw # (
+  // This module can be instantiated once per interrupt field (Width == 1), or
+  // "bussified" with all fields of the interrupt vector (Width == $width(vec)).
   parameter int unsigned Width = 1,
-  parameter bit FlopOutput = 1,
-
-  // IntrT parameter is to hint the logic for the interrupt type. Module
-  // supports two interrupt types, *Status* and *Event*.
-  //
-  // The differences between those two types are:
-  // - Status is persistent. Until the root cause is alleviated, the interrupt
-  //   keeps asserting.
-  // - Event remains high for a relatively short period time without SW
-  //   intervention. One distinct example is an error (error could be status
-  //   though). If a certain error condition is captured, HW logic may create a
-  //   pulse. In this case the interrupt is assumed as an Event interrupt.
-  parameter IntrT = "Event" // Event or Status
+  parameter bit          FlopOutput = 1,
+
+  // As the wired interrupt signal intr_o is a level-triggered interrupt, the upstream consumer sw
+  // has two options to make forward progress when this signal is asserted:
+  // - Mask the interrupt, by setting INTR_ENABLE = 1'b0 or masking/enabling at an upstream
+  //   consumer.
+  // - Interact with the peripheral in some user-defined way that clears the signal.
+  // To make this user-defined interaction ergonomic from a SW-perspective, we have defined
+  // two common patterns for typical interrupt-triggering events, *Status* and *Event*.
+  // - *Event* is useful for capturing a momentary assertion of the input signal.
+  //   - INTR_STATE/intr_o is set to '1 upon the event occurring.
+  //   - INTR_STATE/intr_o remain set until software writes-1-to-clear to INTR_STATE.
+  // - *Status* captures a persistent conditional assertion that requires intervention to de-assert.
+  //   - Until the root cause is alleviated, the interrupt output (while enabled) is continuously
+  //     asserted.
+  //   - INTR_STATE for *status* interrupts is RO (it simply presents the raw HW input signal).
+  //   - If the root_cause is cleared, INTR_STATE/intr_o also clears automatically.
+  // More details about the interrupt type distinctions can be found in the comportability docs.
+  parameter              IntrT = "Event" // Event or Status
 ) (
   // event
   input  clk_i,
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_keccak.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_keccak.sv
index 16b31785..42984515 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_keccak.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_keccak.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -292,4 +292,3 @@ module prim_keccak #(
   //endfunction : keccak_rnd
 
 endmodule
-
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_and_hardened.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_and_hardened.sv
index ae10f6a4..5905b3c3 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_and_hardened.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_and_hardened.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_combine.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_combine.sv
index 2b3cce93..25aeb60d 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_combine.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_combine.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_dec.sv
index d10e0ce3..aeee8a75 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_or_hardened.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_or_hardened.sv
index a1c1df17..dce76646 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_or_hardened.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_or_hardened.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_sender.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_sender.sv
index ae95a2c7..849eba82 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_sender.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_sender.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_sync.sv
index d1536c6b..5f2f7d5f 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_sync.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_lc_sync.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv
index d6d12445..e2400a10 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_macros.svh b/vendor/lowrisc_ip/ip/prim/rtl/prim_macros.svh
index 5561f141..c4f739c6 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_macros.svh
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_macros.svh
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_max_tree.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_max_tree.sv
index e23a76f3..9422d6d0 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_max_tree.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_max_tree.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_msb_extend.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_msb_extend.sv
index 9b37c64a..9cb30380 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_msb_extend.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_msb_extend.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi12_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi12_dec.sv
index 1bc85033..6c983e0b 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi12_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi12_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi12_sender.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi12_sender.sv
index 230efdca..168b39e1 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi12_sender.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi12_sender.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi12_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi12_sync.sv
index 30ee2d6a..6376682d 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi12_sync.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi12_sync.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi16_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi16_dec.sv
index 17411474..a2d04a8d 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi16_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi16_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi16_sender.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi16_sender.sv
index e12b99d2..190d1343 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi16_sender.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi16_sender.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi16_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi16_sync.sv
index 02be5a0c..f73f5bb2 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi16_sync.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi16_sync.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi20_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi20_dec.sv
new file mode 100644
index 00000000..447a199d
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi20_dec.sv
@@ -0,0 +1,48 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+//    util/design/gen-mubi.py
+//
+// Decoder for multibit control signals with additional input buffers.
+
+`include "prim_assert.sv"
+
+module prim_mubi20_dec
+  import prim_mubi_pkg::*;
+#(
+  parameter bit TestTrue = 1,
+  parameter bit TestStrict = 1
+) (
+  input  mubi20_t mubi_i,
+  output logic           mubi_dec_o
+);
+
+logic [MuBi20Width-1:0] mubi, mubi_out;
+assign mubi = MuBi20Width'(mubi_i);
+
+// The buffer cells have a don't touch constraint on them
+// such that synthesis tools won't collapse them
+for (genvar k = 0; k < MuBi20Width; k++) begin : gen_bits
+  prim_buf u_prim_buf (
+    .in_i  ( mubi[k]     ),
+    .out_o ( mubi_out[k] )
+  );
+end
+
+if (TestTrue && TestStrict) begin : gen_test_true_strict
+  assign mubi_dec_o = mubi20_test_true_strict(mubi20_t'(mubi_out));
+end else if (TestTrue && !TestStrict) begin : gen_test_true_loose
+  assign mubi_dec_o = mubi20_test_true_loose(mubi20_t'(mubi_out));
+end else if (!TestTrue && TestStrict) begin : gen_test_false_strict
+  assign mubi_dec_o = mubi20_test_false_strict(mubi20_t'(mubi_out));
+end else if (!TestTrue && !TestStrict) begin : gen_test_false_loose
+  assign mubi_dec_o = mubi20_test_false_loose(mubi20_t'(mubi_out));
+end else begin : gen_unknown_config
+  `ASSERT_INIT(UnknownConfig_A, 0)
+end
+
+endmodule : prim_mubi20_dec
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi20_sender.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi20_sender.sv
new file mode 100644
index 00000000..73fc7d02
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi20_sender.sv
@@ -0,0 +1,94 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+//    util/design/gen-mubi.py
+//
+// Multibit sender module. This module is instantiates a hand-picked flop cell for each bit in the
+// multibit signal such that tools do not optimize the multibit encoding.
+
+`include "prim_assert.sv"
+
+module prim_mubi20_sender
+  import prim_mubi_pkg::*;
+#(
+  // This flops the output if set to 1.
+  // In special cases where the sender is in the same clock domain as the receiver,
+  // this can be set to 0. However, it is recommended to leave this at 1.
+  parameter bit AsyncOn = 1,
+  // Enable anchor buffer
+  parameter bit EnSecBuf = 0,
+  // Reset value for the sender flops
+  parameter mubi20_t ResetValue = MuBi20False
+) (
+  input          clk_i,
+  input          rst_ni,
+  input  mubi20_t mubi_i,
+  output mubi20_t mubi_o
+);
+
+  logic [MuBi20Width-1:0] mubi, mubi_int, mubi_out;
+  assign mubi = MuBi20Width'(mubi_i);
+
+  // first generation block decides whether a flop should be present
+  if (AsyncOn) begin : gen_flops
+    prim_flop #(
+      .Width(MuBi20Width),
+      .ResetValue(MuBi20Width'(ResetValue))
+    ) u_prim_flop (
+      .clk_i,
+      .rst_ni,
+      .d_i   ( mubi     ),
+      .q_o   ( mubi_int )
+    );
+  end else begin : gen_no_flops
+    assign mubi_int = mubi;
+
+    // This unused companion logic helps remove lint errors
+    // for modules where clock and reset are used for assertions only
+    // This logic will be removed for sythesis since it is unloaded.
+    mubi20_t unused_logic;
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+         unused_logic <= MuBi20False;
+      end else begin
+         unused_logic <= mubi_i;
+      end
+    end
+  end
+
+  // second generation block determines output buffer type
+  // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
+  // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
+  // 3. If not EnSecBuf and AsyncOn -> feed through
+  if (EnSecBuf) begin : gen_sec_buf
+    prim_sec_anchor_buf #(
+      .Width(20)
+    ) u_prim_sec_buf (
+      .in_i(mubi_int),
+      .out_o(mubi_out)
+    );
+  end else if (!AsyncOn) begin : gen_prim_buf
+    prim_buf #(
+      .Width(20)
+    ) u_prim_buf (
+      .in_i(mubi_int),
+      .out_o(mubi_out)
+    );
+  end else begin : gen_feedthru
+    assign mubi_out = mubi_int;
+  end
+
+  assign mubi_o = mubi20_t'(mubi_out);
+
+  ////////////////
+  // Assertions //
+  ////////////////
+
+  // The outputs should be known at all times.
+  `ASSERT_KNOWN(OutputsKnown_A, mubi_o)
+
+endmodule : prim_mubi20_sender
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi20_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi20_sync.sv
new file mode 100644
index 00000000..e54c6214
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi20_sync.sv
@@ -0,0 +1,178 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+//    util/design/gen-mubi.py
+//
+// Double-synchronizer flop for multibit signals with additional output buffers.
+
+`include "prim_assert.sv"
+
+module prim_mubi20_sync
+  import prim_mubi_pkg::*;
+#(
+  // Number of separately buffered output signals.
+  // The buffer cells have a don't touch constraint
+  // on them such that synthesis tools won't collapse
+  // all copies into one signal.
+  parameter int NumCopies = 1,
+  // This instantiates the synchronizer flops if set to 1.
+  // In special cases where the receiver is in the same clock domain as the sender,
+  // this can be set to 0. However, it is recommended to leave this at 1.
+  parameter bit AsyncOn = 1,
+  // This controls whether the mubi module institutes stability checks when
+  // AsyncOn is set.  If stability checks are on, a 3rd stage of storage is
+  // added after the synchronizers and the outputs only updated if the 3rd
+  // stage and sychronizer agree.  If they do not agree, the ResetValue is
+  // output instead.
+  parameter bit StabilityCheck = 0,
+  // Reset value for the sync flops
+  parameter mubi20_t ResetValue = MuBi20False
+) (
+  input                          clk_i,
+  input                          rst_ni,
+  input  mubi20_t                 mubi_i,
+  output mubi20_t [NumCopies-1:0] mubi_o
+);
+
+  `ASSERT_INIT(NumCopiesMustBeGreaterZero_A, NumCopies > 0)
+
+  logic [MuBi20Width-1:0] mubi;
+  if (AsyncOn) begin : gen_flops
+    logic [MuBi20Width-1:0] mubi_sync;
+    prim_flop_2sync #(
+      .Width(MuBi20Width),
+      .ResetValue(MuBi20Width'(ResetValue))
+    ) u_prim_flop_2sync (
+      .clk_i,
+      .rst_ni,
+      .d_i(MuBi20Width'(mubi_i)),
+      .q_o(mubi_sync)
+    );
+
+    if (StabilityCheck) begin : gen_stable_chks
+      logic [MuBi20Width-1:0] mubi_q;
+      prim_flop #(
+        .Width(MuBi20Width),
+        .ResetValue(MuBi20Width'(ResetValue))
+      ) u_prim_flop_3rd_stage (
+        .clk_i,
+        .rst_ni,
+        .d_i(mubi_sync),
+        .q_o(mubi_q)
+      );
+
+      logic [MuBi20Width-1:0] sig_unstable;
+      prim_xor2 #(
+        .Width(MuBi20Width)
+      ) u_mubi_xor (
+        .in0_i(mubi_sync),
+        .in1_i(mubi_q),
+        .out_o(sig_unstable)
+      );
+
+      logic [MuBi20Width-1:0] reset_value;
+      assign reset_value = ResetValue;
+
+      for (genvar k = 0; k < MuBi20Width; k++) begin : gen_bufs_muxes
+        logic [MuBi20Width-1:0] sig_unstable_buf;
+
+        // each mux gets its own buffered output, this ensures the OR-ing
+        // cannot be defeated in one place.
+        prim_sec_anchor_buf #(
+          .Width(MuBi20Width)
+        ) u_sig_unstable_buf (
+          .in_i(sig_unstable),
+          .out_o(sig_unstable_buf)
+        );
+
+        // if any xor indicates signal is unstable, output the reset
+        // value. note that the input and output signals of this mux
+        // are driven/read by constrained primitive cells (regs, buffers),
+        // hence this mux can be implemented behaviorally.
+        assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
+      end
+
+// Note regarding SVAs below:
+//
+// 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
+// a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
+// SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
+// 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
+// on the active clock edge. This causes the assertion to evaluate although the reset was actually
+// 0 when entering this simulation cycle.
+//
+// 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
+// originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
+// at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
+// cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
+// use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
+// sampling mismatches.
+`ifdef INC_ASSERT
+      mubi20_t mubi_in_sva_q;
+      always_ff @(posedge clk_i) begin
+        mubi_in_sva_q <= mubi_i;
+      end
+      `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
+      `ASSERT(OutputDelay_A,
+              rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
+`endif
+    end else begin : gen_no_stable_chks
+      assign mubi = mubi_sync;
+`ifdef INC_ASSERT
+      mubi20_t mubi_in_sva_q;
+      always_ff @(posedge clk_i) begin
+        mubi_in_sva_q <= mubi_i;
+      end
+      `ASSERT(OutputDelay_A,
+              rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
+                              $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
+`endif
+    end
+  end else begin : gen_no_flops
+
+    //VCS coverage off
+    // pragma coverage off
+
+    // This unused companion logic helps remove lint errors
+    // for modules where clock and reset are used for assertions only
+    // This logic will be removed for synthesis since it is unloaded.
+    mubi20_t unused_logic;
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+         unused_logic <= MuBi20False;
+      end else begin
+         unused_logic <= mubi_i;
+      end
+    end
+
+    //VCS coverage on
+    // pragma coverage on
+
+    assign mubi = MuBi20Width'(mubi_i);
+
+    `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
+  end
+
+  for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
+    logic [MuBi20Width-1:0] mubi_out;
+    for (genvar k = 0; k < MuBi20Width; k++) begin : gen_bits
+      prim_buf u_prim_buf (
+        .in_i(mubi[k]),
+        .out_o(mubi_out[k])
+      );
+    end
+    assign mubi_o[j] = mubi20_t'(mubi_out);
+  end
+
+  ////////////////
+  // Assertions //
+  ////////////////
+
+  // The outputs should be known at all times.
+  `ASSERT_KNOWN(OutputsKnown_A, mubi_o)
+
+endmodule : prim_mubi20_sync
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi24_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi24_dec.sv
new file mode 100644
index 00000000..7bb07314
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi24_dec.sv
@@ -0,0 +1,48 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+//    util/design/gen-mubi.py
+//
+// Decoder for multibit control signals with additional input buffers.
+
+`include "prim_assert.sv"
+
+module prim_mubi24_dec
+  import prim_mubi_pkg::*;
+#(
+  parameter bit TestTrue = 1,
+  parameter bit TestStrict = 1
+) (
+  input  mubi24_t mubi_i,
+  output logic           mubi_dec_o
+);
+
+logic [MuBi24Width-1:0] mubi, mubi_out;
+assign mubi = MuBi24Width'(mubi_i);
+
+// The buffer cells have a don't touch constraint on them
+// such that synthesis tools won't collapse them
+for (genvar k = 0; k < MuBi24Width; k++) begin : gen_bits
+  prim_buf u_prim_buf (
+    .in_i  ( mubi[k]     ),
+    .out_o ( mubi_out[k] )
+  );
+end
+
+if (TestTrue && TestStrict) begin : gen_test_true_strict
+  assign mubi_dec_o = mubi24_test_true_strict(mubi24_t'(mubi_out));
+end else if (TestTrue && !TestStrict) begin : gen_test_true_loose
+  assign mubi_dec_o = mubi24_test_true_loose(mubi24_t'(mubi_out));
+end else if (!TestTrue && TestStrict) begin : gen_test_false_strict
+  assign mubi_dec_o = mubi24_test_false_strict(mubi24_t'(mubi_out));
+end else if (!TestTrue && !TestStrict) begin : gen_test_false_loose
+  assign mubi_dec_o = mubi24_test_false_loose(mubi24_t'(mubi_out));
+end else begin : gen_unknown_config
+  `ASSERT_INIT(UnknownConfig_A, 0)
+end
+
+endmodule : prim_mubi24_dec
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi24_sender.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi24_sender.sv
new file mode 100644
index 00000000..d01239b6
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi24_sender.sv
@@ -0,0 +1,94 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+//    util/design/gen-mubi.py
+//
+// Multibit sender module. This module is instantiates a hand-picked flop cell for each bit in the
+// multibit signal such that tools do not optimize the multibit encoding.
+
+`include "prim_assert.sv"
+
+module prim_mubi24_sender
+  import prim_mubi_pkg::*;
+#(
+  // This flops the output if set to 1.
+  // In special cases where the sender is in the same clock domain as the receiver,
+  // this can be set to 0. However, it is recommended to leave this at 1.
+  parameter bit AsyncOn = 1,
+  // Enable anchor buffer
+  parameter bit EnSecBuf = 0,
+  // Reset value for the sender flops
+  parameter mubi24_t ResetValue = MuBi24False
+) (
+  input          clk_i,
+  input          rst_ni,
+  input  mubi24_t mubi_i,
+  output mubi24_t mubi_o
+);
+
+  logic [MuBi24Width-1:0] mubi, mubi_int, mubi_out;
+  assign mubi = MuBi24Width'(mubi_i);
+
+  // first generation block decides whether a flop should be present
+  if (AsyncOn) begin : gen_flops
+    prim_flop #(
+      .Width(MuBi24Width),
+      .ResetValue(MuBi24Width'(ResetValue))
+    ) u_prim_flop (
+      .clk_i,
+      .rst_ni,
+      .d_i   ( mubi     ),
+      .q_o   ( mubi_int )
+    );
+  end else begin : gen_no_flops
+    assign mubi_int = mubi;
+
+    // This unused companion logic helps remove lint errors
+    // for modules where clock and reset are used for assertions only
+    // This logic will be removed for sythesis since it is unloaded.
+    mubi24_t unused_logic;
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+         unused_logic <= MuBi24False;
+      end else begin
+         unused_logic <= mubi_i;
+      end
+    end
+  end
+
+  // second generation block determines output buffer type
+  // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
+  // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
+  // 3. If not EnSecBuf and AsyncOn -> feed through
+  if (EnSecBuf) begin : gen_sec_buf
+    prim_sec_anchor_buf #(
+      .Width(24)
+    ) u_prim_sec_buf (
+      .in_i(mubi_int),
+      .out_o(mubi_out)
+    );
+  end else if (!AsyncOn) begin : gen_prim_buf
+    prim_buf #(
+      .Width(24)
+    ) u_prim_buf (
+      .in_i(mubi_int),
+      .out_o(mubi_out)
+    );
+  end else begin : gen_feedthru
+    assign mubi_out = mubi_int;
+  end
+
+  assign mubi_o = mubi24_t'(mubi_out);
+
+  ////////////////
+  // Assertions //
+  ////////////////
+
+  // The outputs should be known at all times.
+  `ASSERT_KNOWN(OutputsKnown_A, mubi_o)
+
+endmodule : prim_mubi24_sender
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi24_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi24_sync.sv
new file mode 100644
index 00000000..f7a53281
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi24_sync.sv
@@ -0,0 +1,178 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+//    util/design/gen-mubi.py
+//
+// Double-synchronizer flop for multibit signals with additional output buffers.
+
+`include "prim_assert.sv"
+
+module prim_mubi24_sync
+  import prim_mubi_pkg::*;
+#(
+  // Number of separately buffered output signals.
+  // The buffer cells have a don't touch constraint
+  // on them such that synthesis tools won't collapse
+  // all copies into one signal.
+  parameter int NumCopies = 1,
+  // This instantiates the synchronizer flops if set to 1.
+  // In special cases where the receiver is in the same clock domain as the sender,
+  // this can be set to 0. However, it is recommended to leave this at 1.
+  parameter bit AsyncOn = 1,
+  // This controls whether the mubi module institutes stability checks when
+  // AsyncOn is set.  If stability checks are on, a 3rd stage of storage is
+  // added after the synchronizers and the outputs only updated if the 3rd
+  // stage and sychronizer agree.  If they do not agree, the ResetValue is
+  // output instead.
+  parameter bit StabilityCheck = 0,
+  // Reset value for the sync flops
+  parameter mubi24_t ResetValue = MuBi24False
+) (
+  input                          clk_i,
+  input                          rst_ni,
+  input  mubi24_t                 mubi_i,
+  output mubi24_t [NumCopies-1:0] mubi_o
+);
+
+  `ASSERT_INIT(NumCopiesMustBeGreaterZero_A, NumCopies > 0)
+
+  logic [MuBi24Width-1:0] mubi;
+  if (AsyncOn) begin : gen_flops
+    logic [MuBi24Width-1:0] mubi_sync;
+    prim_flop_2sync #(
+      .Width(MuBi24Width),
+      .ResetValue(MuBi24Width'(ResetValue))
+    ) u_prim_flop_2sync (
+      .clk_i,
+      .rst_ni,
+      .d_i(MuBi24Width'(mubi_i)),
+      .q_o(mubi_sync)
+    );
+
+    if (StabilityCheck) begin : gen_stable_chks
+      logic [MuBi24Width-1:0] mubi_q;
+      prim_flop #(
+        .Width(MuBi24Width),
+        .ResetValue(MuBi24Width'(ResetValue))
+      ) u_prim_flop_3rd_stage (
+        .clk_i,
+        .rst_ni,
+        .d_i(mubi_sync),
+        .q_o(mubi_q)
+      );
+
+      logic [MuBi24Width-1:0] sig_unstable;
+      prim_xor2 #(
+        .Width(MuBi24Width)
+      ) u_mubi_xor (
+        .in0_i(mubi_sync),
+        .in1_i(mubi_q),
+        .out_o(sig_unstable)
+      );
+
+      logic [MuBi24Width-1:0] reset_value;
+      assign reset_value = ResetValue;
+
+      for (genvar k = 0; k < MuBi24Width; k++) begin : gen_bufs_muxes
+        logic [MuBi24Width-1:0] sig_unstable_buf;
+
+        // each mux gets its own buffered output, this ensures the OR-ing
+        // cannot be defeated in one place.
+        prim_sec_anchor_buf #(
+          .Width(MuBi24Width)
+        ) u_sig_unstable_buf (
+          .in_i(sig_unstable),
+          .out_o(sig_unstable_buf)
+        );
+
+        // if any xor indicates signal is unstable, output the reset
+        // value. note that the input and output signals of this mux
+        // are driven/read by constrained primitive cells (regs, buffers),
+        // hence this mux can be implemented behaviorally.
+        assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
+      end
+
+// Note regarding SVAs below:
+//
+// 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
+// a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
+// SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
+// 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
+// on the active clock edge. This causes the assertion to evaluate although the reset was actually
+// 0 when entering this simulation cycle.
+//
+// 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
+// originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
+// at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
+// cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
+// use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
+// sampling mismatches.
+`ifdef INC_ASSERT
+      mubi24_t mubi_in_sva_q;
+      always_ff @(posedge clk_i) begin
+        mubi_in_sva_q <= mubi_i;
+      end
+      `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
+      `ASSERT(OutputDelay_A,
+              rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
+`endif
+    end else begin : gen_no_stable_chks
+      assign mubi = mubi_sync;
+`ifdef INC_ASSERT
+      mubi24_t mubi_in_sva_q;
+      always_ff @(posedge clk_i) begin
+        mubi_in_sva_q <= mubi_i;
+      end
+      `ASSERT(OutputDelay_A,
+              rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
+                              $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
+`endif
+    end
+  end else begin : gen_no_flops
+
+    //VCS coverage off
+    // pragma coverage off
+
+    // This unused companion logic helps remove lint errors
+    // for modules where clock and reset are used for assertions only
+    // This logic will be removed for synthesis since it is unloaded.
+    mubi24_t unused_logic;
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+         unused_logic <= MuBi24False;
+      end else begin
+         unused_logic <= mubi_i;
+      end
+    end
+
+    //VCS coverage on
+    // pragma coverage on
+
+    assign mubi = MuBi24Width'(mubi_i);
+
+    `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
+  end
+
+  for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
+    logic [MuBi24Width-1:0] mubi_out;
+    for (genvar k = 0; k < MuBi24Width; k++) begin : gen_bits
+      prim_buf u_prim_buf (
+        .in_i(mubi[k]),
+        .out_o(mubi_out[k])
+      );
+    end
+    assign mubi_o[j] = mubi24_t'(mubi_out);
+  end
+
+  ////////////////
+  // Assertions //
+  ////////////////
+
+  // The outputs should be known at all times.
+  `ASSERT_KNOWN(OutputsKnown_A, mubi_o)
+
+endmodule : prim_mubi24_sync
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi28_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi28_dec.sv
new file mode 100644
index 00000000..1a027e1c
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi28_dec.sv
@@ -0,0 +1,48 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+//    util/design/gen-mubi.py
+//
+// Decoder for multibit control signals with additional input buffers.
+
+`include "prim_assert.sv"
+
+module prim_mubi28_dec
+  import prim_mubi_pkg::*;
+#(
+  parameter bit TestTrue = 1,
+  parameter bit TestStrict = 1
+) (
+  input  mubi28_t mubi_i,
+  output logic           mubi_dec_o
+);
+
+logic [MuBi28Width-1:0] mubi, mubi_out;
+assign mubi = MuBi28Width'(mubi_i);
+
+// The buffer cells have a don't touch constraint on them
+// such that synthesis tools won't collapse them
+for (genvar k = 0; k < MuBi28Width; k++) begin : gen_bits
+  prim_buf u_prim_buf (
+    .in_i  ( mubi[k]     ),
+    .out_o ( mubi_out[k] )
+  );
+end
+
+if (TestTrue && TestStrict) begin : gen_test_true_strict
+  assign mubi_dec_o = mubi28_test_true_strict(mubi28_t'(mubi_out));
+end else if (TestTrue && !TestStrict) begin : gen_test_true_loose
+  assign mubi_dec_o = mubi28_test_true_loose(mubi28_t'(mubi_out));
+end else if (!TestTrue && TestStrict) begin : gen_test_false_strict
+  assign mubi_dec_o = mubi28_test_false_strict(mubi28_t'(mubi_out));
+end else if (!TestTrue && !TestStrict) begin : gen_test_false_loose
+  assign mubi_dec_o = mubi28_test_false_loose(mubi28_t'(mubi_out));
+end else begin : gen_unknown_config
+  `ASSERT_INIT(UnknownConfig_A, 0)
+end
+
+endmodule : prim_mubi28_dec
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi28_sender.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi28_sender.sv
new file mode 100644
index 00000000..633a693a
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi28_sender.sv
@@ -0,0 +1,94 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+//    util/design/gen-mubi.py
+//
+// Multibit sender module. This module is instantiates a hand-picked flop cell for each bit in the
+// multibit signal such that tools do not optimize the multibit encoding.
+
+`include "prim_assert.sv"
+
+module prim_mubi28_sender
+  import prim_mubi_pkg::*;
+#(
+  // This flops the output if set to 1.
+  // In special cases where the sender is in the same clock domain as the receiver,
+  // this can be set to 0. However, it is recommended to leave this at 1.
+  parameter bit AsyncOn = 1,
+  // Enable anchor buffer
+  parameter bit EnSecBuf = 0,
+  // Reset value for the sender flops
+  parameter mubi28_t ResetValue = MuBi28False
+) (
+  input          clk_i,
+  input          rst_ni,
+  input  mubi28_t mubi_i,
+  output mubi28_t mubi_o
+);
+
+  logic [MuBi28Width-1:0] mubi, mubi_int, mubi_out;
+  assign mubi = MuBi28Width'(mubi_i);
+
+  // first generation block decides whether a flop should be present
+  if (AsyncOn) begin : gen_flops
+    prim_flop #(
+      .Width(MuBi28Width),
+      .ResetValue(MuBi28Width'(ResetValue))
+    ) u_prim_flop (
+      .clk_i,
+      .rst_ni,
+      .d_i   ( mubi     ),
+      .q_o   ( mubi_int )
+    );
+  end else begin : gen_no_flops
+    assign mubi_int = mubi;
+
+    // This unused companion logic helps remove lint errors
+    // for modules where clock and reset are used for assertions only
+    // This logic will be removed for sythesis since it is unloaded.
+    mubi28_t unused_logic;
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+         unused_logic <= MuBi28False;
+      end else begin
+         unused_logic <= mubi_i;
+      end
+    end
+  end
+
+  // second generation block determines output buffer type
+  // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
+  // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
+  // 3. If not EnSecBuf and AsyncOn -> feed through
+  if (EnSecBuf) begin : gen_sec_buf
+    prim_sec_anchor_buf #(
+      .Width(28)
+    ) u_prim_sec_buf (
+      .in_i(mubi_int),
+      .out_o(mubi_out)
+    );
+  end else if (!AsyncOn) begin : gen_prim_buf
+    prim_buf #(
+      .Width(28)
+    ) u_prim_buf (
+      .in_i(mubi_int),
+      .out_o(mubi_out)
+    );
+  end else begin : gen_feedthru
+    assign mubi_out = mubi_int;
+  end
+
+  assign mubi_o = mubi28_t'(mubi_out);
+
+  ////////////////
+  // Assertions //
+  ////////////////
+
+  // The outputs should be known at all times.
+  `ASSERT_KNOWN(OutputsKnown_A, mubi_o)
+
+endmodule : prim_mubi28_sender
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi28_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi28_sync.sv
new file mode 100644
index 00000000..1c63536b
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi28_sync.sv
@@ -0,0 +1,178 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+//    util/design/gen-mubi.py
+//
+// Double-synchronizer flop for multibit signals with additional output buffers.
+
+`include "prim_assert.sv"
+
+module prim_mubi28_sync
+  import prim_mubi_pkg::*;
+#(
+  // Number of separately buffered output signals.
+  // The buffer cells have a don't touch constraint
+  // on them such that synthesis tools won't collapse
+  // all copies into one signal.
+  parameter int NumCopies = 1,
+  // This instantiates the synchronizer flops if set to 1.
+  // In special cases where the receiver is in the same clock domain as the sender,
+  // this can be set to 0. However, it is recommended to leave this at 1.
+  parameter bit AsyncOn = 1,
+  // This controls whether the mubi module institutes stability checks when
+  // AsyncOn is set.  If stability checks are on, a 3rd stage of storage is
+  // added after the synchronizers and the outputs only updated if the 3rd
+  // stage and sychronizer agree.  If they do not agree, the ResetValue is
+  // output instead.
+  parameter bit StabilityCheck = 0,
+  // Reset value for the sync flops
+  parameter mubi28_t ResetValue = MuBi28False
+) (
+  input                          clk_i,
+  input                          rst_ni,
+  input  mubi28_t                 mubi_i,
+  output mubi28_t [NumCopies-1:0] mubi_o
+);
+
+  `ASSERT_INIT(NumCopiesMustBeGreaterZero_A, NumCopies > 0)
+
+  logic [MuBi28Width-1:0] mubi;
+  if (AsyncOn) begin : gen_flops
+    logic [MuBi28Width-1:0] mubi_sync;
+    prim_flop_2sync #(
+      .Width(MuBi28Width),
+      .ResetValue(MuBi28Width'(ResetValue))
+    ) u_prim_flop_2sync (
+      .clk_i,
+      .rst_ni,
+      .d_i(MuBi28Width'(mubi_i)),
+      .q_o(mubi_sync)
+    );
+
+    if (StabilityCheck) begin : gen_stable_chks
+      logic [MuBi28Width-1:0] mubi_q;
+      prim_flop #(
+        .Width(MuBi28Width),
+        .ResetValue(MuBi28Width'(ResetValue))
+      ) u_prim_flop_3rd_stage (
+        .clk_i,
+        .rst_ni,
+        .d_i(mubi_sync),
+        .q_o(mubi_q)
+      );
+
+      logic [MuBi28Width-1:0] sig_unstable;
+      prim_xor2 #(
+        .Width(MuBi28Width)
+      ) u_mubi_xor (
+        .in0_i(mubi_sync),
+        .in1_i(mubi_q),
+        .out_o(sig_unstable)
+      );
+
+      logic [MuBi28Width-1:0] reset_value;
+      assign reset_value = ResetValue;
+
+      for (genvar k = 0; k < MuBi28Width; k++) begin : gen_bufs_muxes
+        logic [MuBi28Width-1:0] sig_unstable_buf;
+
+        // each mux gets its own buffered output, this ensures the OR-ing
+        // cannot be defeated in one place.
+        prim_sec_anchor_buf #(
+          .Width(MuBi28Width)
+        ) u_sig_unstable_buf (
+          .in_i(sig_unstable),
+          .out_o(sig_unstable_buf)
+        );
+
+        // if any xor indicates signal is unstable, output the reset
+        // value. note that the input and output signals of this mux
+        // are driven/read by constrained primitive cells (regs, buffers),
+        // hence this mux can be implemented behaviorally.
+        assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
+      end
+
+// Note regarding SVAs below:
+//
+// 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
+// a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
+// SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
+// 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
+// on the active clock edge. This causes the assertion to evaluate although the reset was actually
+// 0 when entering this simulation cycle.
+//
+// 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
+// originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
+// at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
+// cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
+// use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
+// sampling mismatches.
+`ifdef INC_ASSERT
+      mubi28_t mubi_in_sva_q;
+      always_ff @(posedge clk_i) begin
+        mubi_in_sva_q <= mubi_i;
+      end
+      `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
+      `ASSERT(OutputDelay_A,
+              rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
+`endif
+    end else begin : gen_no_stable_chks
+      assign mubi = mubi_sync;
+`ifdef INC_ASSERT
+      mubi28_t mubi_in_sva_q;
+      always_ff @(posedge clk_i) begin
+        mubi_in_sva_q <= mubi_i;
+      end
+      `ASSERT(OutputDelay_A,
+              rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
+                              $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
+`endif
+    end
+  end else begin : gen_no_flops
+
+    //VCS coverage off
+    // pragma coverage off
+
+    // This unused companion logic helps remove lint errors
+    // for modules where clock and reset are used for assertions only
+    // This logic will be removed for synthesis since it is unloaded.
+    mubi28_t unused_logic;
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+         unused_logic <= MuBi28False;
+      end else begin
+         unused_logic <= mubi_i;
+      end
+    end
+
+    //VCS coverage on
+    // pragma coverage on
+
+    assign mubi = MuBi28Width'(mubi_i);
+
+    `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
+  end
+
+  for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
+    logic [MuBi28Width-1:0] mubi_out;
+    for (genvar k = 0; k < MuBi28Width; k++) begin : gen_bits
+      prim_buf u_prim_buf (
+        .in_i(mubi[k]),
+        .out_o(mubi_out[k])
+      );
+    end
+    assign mubi_o[j] = mubi28_t'(mubi_out);
+  end
+
+  ////////////////
+  // Assertions //
+  ////////////////
+
+  // The outputs should be known at all times.
+  `ASSERT_KNOWN(OutputsKnown_A, mubi_o)
+
+endmodule : prim_mubi28_sync
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi32_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi32_dec.sv
new file mode 100644
index 00000000..c225fd5c
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi32_dec.sv
@@ -0,0 +1,48 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+//    util/design/gen-mubi.py
+//
+// Decoder for multibit control signals with additional input buffers.
+
+`include "prim_assert.sv"
+
+module prim_mubi32_dec
+  import prim_mubi_pkg::*;
+#(
+  parameter bit TestTrue = 1,
+  parameter bit TestStrict = 1
+) (
+  input  mubi32_t mubi_i,
+  output logic           mubi_dec_o
+);
+
+logic [MuBi32Width-1:0] mubi, mubi_out;
+assign mubi = MuBi32Width'(mubi_i);
+
+// The buffer cells have a don't touch constraint on them
+// such that synthesis tools won't collapse them
+for (genvar k = 0; k < MuBi32Width; k++) begin : gen_bits
+  prim_buf u_prim_buf (
+    .in_i  ( mubi[k]     ),
+    .out_o ( mubi_out[k] )
+  );
+end
+
+if (TestTrue && TestStrict) begin : gen_test_true_strict
+  assign mubi_dec_o = mubi32_test_true_strict(mubi32_t'(mubi_out));
+end else if (TestTrue && !TestStrict) begin : gen_test_true_loose
+  assign mubi_dec_o = mubi32_test_true_loose(mubi32_t'(mubi_out));
+end else if (!TestTrue && TestStrict) begin : gen_test_false_strict
+  assign mubi_dec_o = mubi32_test_false_strict(mubi32_t'(mubi_out));
+end else if (!TestTrue && !TestStrict) begin : gen_test_false_loose
+  assign mubi_dec_o = mubi32_test_false_loose(mubi32_t'(mubi_out));
+end else begin : gen_unknown_config
+  `ASSERT_INIT(UnknownConfig_A, 0)
+end
+
+endmodule : prim_mubi32_dec
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi32_sender.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi32_sender.sv
new file mode 100644
index 00000000..ba6343c8
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi32_sender.sv
@@ -0,0 +1,94 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+//    util/design/gen-mubi.py
+//
+// Multibit sender module. This module is instantiates a hand-picked flop cell for each bit in the
+// multibit signal such that tools do not optimize the multibit encoding.
+
+`include "prim_assert.sv"
+
+module prim_mubi32_sender
+  import prim_mubi_pkg::*;
+#(
+  // This flops the output if set to 1.
+  // In special cases where the sender is in the same clock domain as the receiver,
+  // this can be set to 0. However, it is recommended to leave this at 1.
+  parameter bit AsyncOn = 1,
+  // Enable anchor buffer
+  parameter bit EnSecBuf = 0,
+  // Reset value for the sender flops
+  parameter mubi32_t ResetValue = MuBi32False
+) (
+  input          clk_i,
+  input          rst_ni,
+  input  mubi32_t mubi_i,
+  output mubi32_t mubi_o
+);
+
+  logic [MuBi32Width-1:0] mubi, mubi_int, mubi_out;
+  assign mubi = MuBi32Width'(mubi_i);
+
+  // first generation block decides whether a flop should be present
+  if (AsyncOn) begin : gen_flops
+    prim_flop #(
+      .Width(MuBi32Width),
+      .ResetValue(MuBi32Width'(ResetValue))
+    ) u_prim_flop (
+      .clk_i,
+      .rst_ni,
+      .d_i   ( mubi     ),
+      .q_o   ( mubi_int )
+    );
+  end else begin : gen_no_flops
+    assign mubi_int = mubi;
+
+    // This unused companion logic helps remove lint errors
+    // for modules where clock and reset are used for assertions only
+    // This logic will be removed for sythesis since it is unloaded.
+    mubi32_t unused_logic;
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+         unused_logic <= MuBi32False;
+      end else begin
+         unused_logic <= mubi_i;
+      end
+    end
+  end
+
+  // second generation block determines output buffer type
+  // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
+  // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
+  // 3. If not EnSecBuf and AsyncOn -> feed through
+  if (EnSecBuf) begin : gen_sec_buf
+    prim_sec_anchor_buf #(
+      .Width(32)
+    ) u_prim_sec_buf (
+      .in_i(mubi_int),
+      .out_o(mubi_out)
+    );
+  end else if (!AsyncOn) begin : gen_prim_buf
+    prim_buf #(
+      .Width(32)
+    ) u_prim_buf (
+      .in_i(mubi_int),
+      .out_o(mubi_out)
+    );
+  end else begin : gen_feedthru
+    assign mubi_out = mubi_int;
+  end
+
+  assign mubi_o = mubi32_t'(mubi_out);
+
+  ////////////////
+  // Assertions //
+  ////////////////
+
+  // The outputs should be known at all times.
+  `ASSERT_KNOWN(OutputsKnown_A, mubi_o)
+
+endmodule : prim_mubi32_sender
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi32_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi32_sync.sv
new file mode 100644
index 00000000..afae3b31
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi32_sync.sv
@@ -0,0 +1,178 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+//    util/design/gen-mubi.py
+//
+// Double-synchronizer flop for multibit signals with additional output buffers.
+
+`include "prim_assert.sv"
+
+module prim_mubi32_sync
+  import prim_mubi_pkg::*;
+#(
+  // Number of separately buffered output signals.
+  // The buffer cells have a don't touch constraint
+  // on them such that synthesis tools won't collapse
+  // all copies into one signal.
+  parameter int NumCopies = 1,
+  // This instantiates the synchronizer flops if set to 1.
+  // In special cases where the receiver is in the same clock domain as the sender,
+  // this can be set to 0. However, it is recommended to leave this at 1.
+  parameter bit AsyncOn = 1,
+  // This controls whether the mubi module institutes stability checks when
+  // AsyncOn is set.  If stability checks are on, a 3rd stage of storage is
+  // added after the synchronizers and the outputs only updated if the 3rd
+  // stage and sychronizer agree.  If they do not agree, the ResetValue is
+  // output instead.
+  parameter bit StabilityCheck = 0,
+  // Reset value for the sync flops
+  parameter mubi32_t ResetValue = MuBi32False
+) (
+  input                          clk_i,
+  input                          rst_ni,
+  input  mubi32_t                 mubi_i,
+  output mubi32_t [NumCopies-1:0] mubi_o
+);
+
+  `ASSERT_INIT(NumCopiesMustBeGreaterZero_A, NumCopies > 0)
+
+  logic [MuBi32Width-1:0] mubi;
+  if (AsyncOn) begin : gen_flops
+    logic [MuBi32Width-1:0] mubi_sync;
+    prim_flop_2sync #(
+      .Width(MuBi32Width),
+      .ResetValue(MuBi32Width'(ResetValue))
+    ) u_prim_flop_2sync (
+      .clk_i,
+      .rst_ni,
+      .d_i(MuBi32Width'(mubi_i)),
+      .q_o(mubi_sync)
+    );
+
+    if (StabilityCheck) begin : gen_stable_chks
+      logic [MuBi32Width-1:0] mubi_q;
+      prim_flop #(
+        .Width(MuBi32Width),
+        .ResetValue(MuBi32Width'(ResetValue))
+      ) u_prim_flop_3rd_stage (
+        .clk_i,
+        .rst_ni,
+        .d_i(mubi_sync),
+        .q_o(mubi_q)
+      );
+
+      logic [MuBi32Width-1:0] sig_unstable;
+      prim_xor2 #(
+        .Width(MuBi32Width)
+      ) u_mubi_xor (
+        .in0_i(mubi_sync),
+        .in1_i(mubi_q),
+        .out_o(sig_unstable)
+      );
+
+      logic [MuBi32Width-1:0] reset_value;
+      assign reset_value = ResetValue;
+
+      for (genvar k = 0; k < MuBi32Width; k++) begin : gen_bufs_muxes
+        logic [MuBi32Width-1:0] sig_unstable_buf;
+
+        // each mux gets its own buffered output, this ensures the OR-ing
+        // cannot be defeated in one place.
+        prim_sec_anchor_buf #(
+          .Width(MuBi32Width)
+        ) u_sig_unstable_buf (
+          .in_i(sig_unstable),
+          .out_o(sig_unstable_buf)
+        );
+
+        // if any xor indicates signal is unstable, output the reset
+        // value. note that the input and output signals of this mux
+        // are driven/read by constrained primitive cells (regs, buffers),
+        // hence this mux can be implemented behaviorally.
+        assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
+      end
+
+// Note regarding SVAs below:
+//
+// 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
+// a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
+// SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
+// 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
+// on the active clock edge. This causes the assertion to evaluate although the reset was actually
+// 0 when entering this simulation cycle.
+//
+// 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
+// originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
+// at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
+// cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
+// use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
+// sampling mismatches.
+`ifdef INC_ASSERT
+      mubi32_t mubi_in_sva_q;
+      always_ff @(posedge clk_i) begin
+        mubi_in_sva_q <= mubi_i;
+      end
+      `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
+      `ASSERT(OutputDelay_A,
+              rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
+`endif
+    end else begin : gen_no_stable_chks
+      assign mubi = mubi_sync;
+`ifdef INC_ASSERT
+      mubi32_t mubi_in_sva_q;
+      always_ff @(posedge clk_i) begin
+        mubi_in_sva_q <= mubi_i;
+      end
+      `ASSERT(OutputDelay_A,
+              rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
+                              $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
+`endif
+    end
+  end else begin : gen_no_flops
+
+    //VCS coverage off
+    // pragma coverage off
+
+    // This unused companion logic helps remove lint errors
+    // for modules where clock and reset are used for assertions only
+    // This logic will be removed for synthesis since it is unloaded.
+    mubi32_t unused_logic;
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+         unused_logic <= MuBi32False;
+      end else begin
+         unused_logic <= mubi_i;
+      end
+    end
+
+    //VCS coverage on
+    // pragma coverage on
+
+    assign mubi = MuBi32Width'(mubi_i);
+
+    `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
+  end
+
+  for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
+    logic [MuBi32Width-1:0] mubi_out;
+    for (genvar k = 0; k < MuBi32Width; k++) begin : gen_bits
+      prim_buf u_prim_buf (
+        .in_i(mubi[k]),
+        .out_o(mubi_out[k])
+      );
+    end
+    assign mubi_o[j] = mubi32_t'(mubi_out);
+  end
+
+  ////////////////
+  // Assertions //
+  ////////////////
+
+  // The outputs should be known at all times.
+  `ASSERT_KNOWN(OutputsKnown_A, mubi_o)
+
+endmodule : prim_mubi32_sync
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi4_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi4_dec.sv
index b822fa89..4561f54f 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi4_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi4_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi4_sender.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi4_sender.sv
index 85b7af87..b69eefd2 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi4_sender.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi4_sender.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi4_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi4_sync.sv
index 02395409..b5aa0aa1 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi4_sync.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi4_sync.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi8_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi8_dec.sv
index 0f7171f2..e79ed824 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi8_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi8_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi8_sender.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi8_sender.sv
index 7fb81f50..e3379ad6 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi8_sender.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi8_sender.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi8_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi8_sync.sv
index 14e9254c..9e1151dd 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi8_sync.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi8_sync.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi_pkg.sv
index 13e167db..0277329a 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_mubi_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -542,4 +542,532 @@ package prim_mubi_pkg;
     return mubi16_and(a, b, MuBi16False);
   endfunction : mubi16_and_lo
 
+  //////////////////////////////////////////////
+  // 20 Bit Multibit Type and Functions //
+  //////////////////////////////////////////////
+
+  parameter int MuBi20Width = 20;
+  typedef enum logic [MuBi20Width-1:0] {
+    MuBi20True = 20'h69696, // enabled
+    MuBi20False = 20'h96969  // disabled
+  } mubi20_t;
+
+  // This is a prerequisite for the multibit functions below to work.
+  `ASSERT_STATIC_IN_PACKAGE(CheckMuBi20ValsComplementary_A, MuBi20True == ~MuBi20False)
+
+  // Test whether the multibit value is one of the valid enumerations
+  function automatic logic mubi20_test_invalid(mubi20_t val);
+    return ~(val inside {MuBi20True, MuBi20False});
+  endfunction : mubi20_test_invalid
+
+  // Convert a 1 input value to a mubi output
+  function automatic mubi20_t mubi20_bool_to_mubi(logic val);
+    return (val ? MuBi20True : MuBi20False);
+  endfunction : mubi20_bool_to_mubi
+
+  // Test whether the multibit value signals an "enabled" condition.
+  // The strict version of this function requires
+  // the multibit value to equal True.
+  function automatic logic mubi20_test_true_strict(mubi20_t val);
+    return MuBi20True == val;
+  endfunction : mubi20_test_true_strict
+
+  // Test whether the multibit value signals a "disabled" condition.
+  // The strict version of this function requires
+  // the multibit value to equal False.
+  function automatic logic mubi20_test_false_strict(mubi20_t val);
+    return MuBi20False == val;
+  endfunction : mubi20_test_false_strict
+
+  // Test whether the multibit value signals an "enabled" condition.
+  // The loose version of this function interprets all
+  // values other than False as "enabled".
+  function automatic logic mubi20_test_true_loose(mubi20_t val);
+    return MuBi20False != val;
+  endfunction : mubi20_test_true_loose
+
+  // Test whether the multibit value signals a "disabled" condition.
+  // The loose version of this function interprets all
+  // values other than True as "disabled".
+  function automatic logic mubi20_test_false_loose(mubi20_t val);
+    return MuBi20True != val;
+  endfunction : mubi20_test_false_loose
+
+
+  // Performs a logical OR operation between two multibit values.
+  // This treats "act" as logical 1, and all other values are
+  // treated as 0. Truth table:
+  //
+  // A    | B    | OUT
+  //------+------+-----
+  // !act | !act | !act
+  // act  | !act | act
+  // !act | act  | act
+  // act  | act  | act
+  //
+  function automatic mubi20_t mubi20_or(mubi20_t a, mubi20_t b, mubi20_t act);
+    logic [MuBi20Width-1:0] a_in, b_in, act_in, out;
+    a_in = a;
+    b_in = b;
+    act_in = act;
+    for (int k = 0; k < MuBi20Width; k++) begin
+      if (act_in[k]) begin
+        out[k] = a_in[k] || b_in[k];
+      end else begin
+        out[k] = a_in[k] && b_in[k];
+      end
+    end
+    return mubi20_t'(out);
+  endfunction : mubi20_or
+
+  // Performs a logical AND operation between two multibit values.
+  // This treats "act" as logical 1, and all other values are
+  // treated as 0. Truth table:
+  //
+  // A    | B    | OUT
+  //------+------+-----
+  // !act | !act | !act
+  // act  | !act | !act
+  // !act | act  | !act
+  // act  | act  | act
+  //
+  function automatic mubi20_t mubi20_and(mubi20_t a, mubi20_t b, mubi20_t act);
+    logic [MuBi20Width-1:0] a_in, b_in, act_in, out;
+    a_in = a;
+    b_in = b;
+    act_in = act;
+    for (int k = 0; k < MuBi20Width; k++) begin
+      if (act_in[k]) begin
+        out[k] = a_in[k] && b_in[k];
+      end else begin
+        out[k] = a_in[k] || b_in[k];
+      end
+    end
+    return mubi20_t'(out);
+  endfunction : mubi20_and
+
+  // Performs a logical OR operation between two multibit values.
+  // This treats "True" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi20_t mubi20_or_hi(mubi20_t a, mubi20_t b);
+    return mubi20_or(a, b, MuBi20True);
+  endfunction : mubi20_or_hi
+
+  // Performs a logical AND operation between two multibit values.
+  // This treats "True" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi20_t mubi20_and_hi(mubi20_t a, mubi20_t b);
+    return mubi20_and(a, b, MuBi20True);
+  endfunction : mubi20_and_hi
+
+  // Performs a logical OR operation between two multibit values.
+  // This treats "False" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi20_t mubi20_or_lo(mubi20_t a, mubi20_t b);
+    return mubi20_or(a, b, MuBi20False);
+  endfunction : mubi20_or_lo
+
+  // Performs a logical AND operation between two multibit values.
+  // This treats "False" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi20_t mubi20_and_lo(mubi20_t a, mubi20_t b);
+    return mubi20_and(a, b, MuBi20False);
+  endfunction : mubi20_and_lo
+
+  //////////////////////////////////////////////
+  // 24 Bit Multibit Type and Functions //
+  //////////////////////////////////////////////
+
+  parameter int MuBi24Width = 24;
+  typedef enum logic [MuBi24Width-1:0] {
+    MuBi24True = 24'h969696, // enabled
+    MuBi24False = 24'h696969  // disabled
+  } mubi24_t;
+
+  // This is a prerequisite for the multibit functions below to work.
+  `ASSERT_STATIC_IN_PACKAGE(CheckMuBi24ValsComplementary_A, MuBi24True == ~MuBi24False)
+
+  // Test whether the multibit value is one of the valid enumerations
+  function automatic logic mubi24_test_invalid(mubi24_t val);
+    return ~(val inside {MuBi24True, MuBi24False});
+  endfunction : mubi24_test_invalid
+
+  // Convert a 1 input value to a mubi output
+  function automatic mubi24_t mubi24_bool_to_mubi(logic val);
+    return (val ? MuBi24True : MuBi24False);
+  endfunction : mubi24_bool_to_mubi
+
+  // Test whether the multibit value signals an "enabled" condition.
+  // The strict version of this function requires
+  // the multibit value to equal True.
+  function automatic logic mubi24_test_true_strict(mubi24_t val);
+    return MuBi24True == val;
+  endfunction : mubi24_test_true_strict
+
+  // Test whether the multibit value signals a "disabled" condition.
+  // The strict version of this function requires
+  // the multibit value to equal False.
+  function automatic logic mubi24_test_false_strict(mubi24_t val);
+    return MuBi24False == val;
+  endfunction : mubi24_test_false_strict
+
+  // Test whether the multibit value signals an "enabled" condition.
+  // The loose version of this function interprets all
+  // values other than False as "enabled".
+  function automatic logic mubi24_test_true_loose(mubi24_t val);
+    return MuBi24False != val;
+  endfunction : mubi24_test_true_loose
+
+  // Test whether the multibit value signals a "disabled" condition.
+  // The loose version of this function interprets all
+  // values other than True as "disabled".
+  function automatic logic mubi24_test_false_loose(mubi24_t val);
+    return MuBi24True != val;
+  endfunction : mubi24_test_false_loose
+
+
+  // Performs a logical OR operation between two multibit values.
+  // This treats "act" as logical 1, and all other values are
+  // treated as 0. Truth table:
+  //
+  // A    | B    | OUT
+  //------+------+-----
+  // !act | !act | !act
+  // act  | !act | act
+  // !act | act  | act
+  // act  | act  | act
+  //
+  function automatic mubi24_t mubi24_or(mubi24_t a, mubi24_t b, mubi24_t act);
+    logic [MuBi24Width-1:0] a_in, b_in, act_in, out;
+    a_in = a;
+    b_in = b;
+    act_in = act;
+    for (int k = 0; k < MuBi24Width; k++) begin
+      if (act_in[k]) begin
+        out[k] = a_in[k] || b_in[k];
+      end else begin
+        out[k] = a_in[k] && b_in[k];
+      end
+    end
+    return mubi24_t'(out);
+  endfunction : mubi24_or
+
+  // Performs a logical AND operation between two multibit values.
+  // This treats "act" as logical 1, and all other values are
+  // treated as 0. Truth table:
+  //
+  // A    | B    | OUT
+  //------+------+-----
+  // !act | !act | !act
+  // act  | !act | !act
+  // !act | act  | !act
+  // act  | act  | act
+  //
+  function automatic mubi24_t mubi24_and(mubi24_t a, mubi24_t b, mubi24_t act);
+    logic [MuBi24Width-1:0] a_in, b_in, act_in, out;
+    a_in = a;
+    b_in = b;
+    act_in = act;
+    for (int k = 0; k < MuBi24Width; k++) begin
+      if (act_in[k]) begin
+        out[k] = a_in[k] && b_in[k];
+      end else begin
+        out[k] = a_in[k] || b_in[k];
+      end
+    end
+    return mubi24_t'(out);
+  endfunction : mubi24_and
+
+  // Performs a logical OR operation between two multibit values.
+  // This treats "True" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi24_t mubi24_or_hi(mubi24_t a, mubi24_t b);
+    return mubi24_or(a, b, MuBi24True);
+  endfunction : mubi24_or_hi
+
+  // Performs a logical AND operation between two multibit values.
+  // This treats "True" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi24_t mubi24_and_hi(mubi24_t a, mubi24_t b);
+    return mubi24_and(a, b, MuBi24True);
+  endfunction : mubi24_and_hi
+
+  // Performs a logical OR operation between two multibit values.
+  // This treats "False" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi24_t mubi24_or_lo(mubi24_t a, mubi24_t b);
+    return mubi24_or(a, b, MuBi24False);
+  endfunction : mubi24_or_lo
+
+  // Performs a logical AND operation between two multibit values.
+  // This treats "False" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi24_t mubi24_and_lo(mubi24_t a, mubi24_t b);
+    return mubi24_and(a, b, MuBi24False);
+  endfunction : mubi24_and_lo
+
+  //////////////////////////////////////////////
+  // 28 Bit Multibit Type and Functions //
+  //////////////////////////////////////////////
+
+  parameter int MuBi28Width = 28;
+  typedef enum logic [MuBi28Width-1:0] {
+    MuBi28True = 28'h6969696, // enabled
+    MuBi28False = 28'h9696969  // disabled
+  } mubi28_t;
+
+  // This is a prerequisite for the multibit functions below to work.
+  `ASSERT_STATIC_IN_PACKAGE(CheckMuBi28ValsComplementary_A, MuBi28True == ~MuBi28False)
+
+  // Test whether the multibit value is one of the valid enumerations
+  function automatic logic mubi28_test_invalid(mubi28_t val);
+    return ~(val inside {MuBi28True, MuBi28False});
+  endfunction : mubi28_test_invalid
+
+  // Convert a 1 input value to a mubi output
+  function automatic mubi28_t mubi28_bool_to_mubi(logic val);
+    return (val ? MuBi28True : MuBi28False);
+  endfunction : mubi28_bool_to_mubi
+
+  // Test whether the multibit value signals an "enabled" condition.
+  // The strict version of this function requires
+  // the multibit value to equal True.
+  function automatic logic mubi28_test_true_strict(mubi28_t val);
+    return MuBi28True == val;
+  endfunction : mubi28_test_true_strict
+
+  // Test whether the multibit value signals a "disabled" condition.
+  // The strict version of this function requires
+  // the multibit value to equal False.
+  function automatic logic mubi28_test_false_strict(mubi28_t val);
+    return MuBi28False == val;
+  endfunction : mubi28_test_false_strict
+
+  // Test whether the multibit value signals an "enabled" condition.
+  // The loose version of this function interprets all
+  // values other than False as "enabled".
+  function automatic logic mubi28_test_true_loose(mubi28_t val);
+    return MuBi28False != val;
+  endfunction : mubi28_test_true_loose
+
+  // Test whether the multibit value signals a "disabled" condition.
+  // The loose version of this function interprets all
+  // values other than True as "disabled".
+  function automatic logic mubi28_test_false_loose(mubi28_t val);
+    return MuBi28True != val;
+  endfunction : mubi28_test_false_loose
+
+
+  // Performs a logical OR operation between two multibit values.
+  // This treats "act" as logical 1, and all other values are
+  // treated as 0. Truth table:
+  //
+  // A    | B    | OUT
+  //------+------+-----
+  // !act | !act | !act
+  // act  | !act | act
+  // !act | act  | act
+  // act  | act  | act
+  //
+  function automatic mubi28_t mubi28_or(mubi28_t a, mubi28_t b, mubi28_t act);
+    logic [MuBi28Width-1:0] a_in, b_in, act_in, out;
+    a_in = a;
+    b_in = b;
+    act_in = act;
+    for (int k = 0; k < MuBi28Width; k++) begin
+      if (act_in[k]) begin
+        out[k] = a_in[k] || b_in[k];
+      end else begin
+        out[k] = a_in[k] && b_in[k];
+      end
+    end
+    return mubi28_t'(out);
+  endfunction : mubi28_or
+
+  // Performs a logical AND operation between two multibit values.
+  // This treats "act" as logical 1, and all other values are
+  // treated as 0. Truth table:
+  //
+  // A    | B    | OUT
+  //------+------+-----
+  // !act | !act | !act
+  // act  | !act | !act
+  // !act | act  | !act
+  // act  | act  | act
+  //
+  function automatic mubi28_t mubi28_and(mubi28_t a, mubi28_t b, mubi28_t act);
+    logic [MuBi28Width-1:0] a_in, b_in, act_in, out;
+    a_in = a;
+    b_in = b;
+    act_in = act;
+    for (int k = 0; k < MuBi28Width; k++) begin
+      if (act_in[k]) begin
+        out[k] = a_in[k] && b_in[k];
+      end else begin
+        out[k] = a_in[k] || b_in[k];
+      end
+    end
+    return mubi28_t'(out);
+  endfunction : mubi28_and
+
+  // Performs a logical OR operation between two multibit values.
+  // This treats "True" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi28_t mubi28_or_hi(mubi28_t a, mubi28_t b);
+    return mubi28_or(a, b, MuBi28True);
+  endfunction : mubi28_or_hi
+
+  // Performs a logical AND operation between two multibit values.
+  // This treats "True" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi28_t mubi28_and_hi(mubi28_t a, mubi28_t b);
+    return mubi28_and(a, b, MuBi28True);
+  endfunction : mubi28_and_hi
+
+  // Performs a logical OR operation between two multibit values.
+  // This treats "False" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi28_t mubi28_or_lo(mubi28_t a, mubi28_t b);
+    return mubi28_or(a, b, MuBi28False);
+  endfunction : mubi28_or_lo
+
+  // Performs a logical AND operation between two multibit values.
+  // This treats "False" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi28_t mubi28_and_lo(mubi28_t a, mubi28_t b);
+    return mubi28_and(a, b, MuBi28False);
+  endfunction : mubi28_and_lo
+
+  //////////////////////////////////////////////
+  // 32 Bit Multibit Type and Functions //
+  //////////////////////////////////////////////
+
+  parameter int MuBi32Width = 32;
+  typedef enum logic [MuBi32Width-1:0] {
+    MuBi32True = 32'h96969696, // enabled
+    MuBi32False = 32'h69696969  // disabled
+  } mubi32_t;
+
+  // This is a prerequisite for the multibit functions below to work.
+  `ASSERT_STATIC_IN_PACKAGE(CheckMuBi32ValsComplementary_A, MuBi32True == ~MuBi32False)
+
+  // Test whether the multibit value is one of the valid enumerations
+  function automatic logic mubi32_test_invalid(mubi32_t val);
+    return ~(val inside {MuBi32True, MuBi32False});
+  endfunction : mubi32_test_invalid
+
+  // Convert a 1 input value to a mubi output
+  function automatic mubi32_t mubi32_bool_to_mubi(logic val);
+    return (val ? MuBi32True : MuBi32False);
+  endfunction : mubi32_bool_to_mubi
+
+  // Test whether the multibit value signals an "enabled" condition.
+  // The strict version of this function requires
+  // the multibit value to equal True.
+  function automatic logic mubi32_test_true_strict(mubi32_t val);
+    return MuBi32True == val;
+  endfunction : mubi32_test_true_strict
+
+  // Test whether the multibit value signals a "disabled" condition.
+  // The strict version of this function requires
+  // the multibit value to equal False.
+  function automatic logic mubi32_test_false_strict(mubi32_t val);
+    return MuBi32False == val;
+  endfunction : mubi32_test_false_strict
+
+  // Test whether the multibit value signals an "enabled" condition.
+  // The loose version of this function interprets all
+  // values other than False as "enabled".
+  function automatic logic mubi32_test_true_loose(mubi32_t val);
+    return MuBi32False != val;
+  endfunction : mubi32_test_true_loose
+
+  // Test whether the multibit value signals a "disabled" condition.
+  // The loose version of this function interprets all
+  // values other than True as "disabled".
+  function automatic logic mubi32_test_false_loose(mubi32_t val);
+    return MuBi32True != val;
+  endfunction : mubi32_test_false_loose
+
+
+  // Performs a logical OR operation between two multibit values.
+  // This treats "act" as logical 1, and all other values are
+  // treated as 0. Truth table:
+  //
+  // A    | B    | OUT
+  //------+------+-----
+  // !act | !act | !act
+  // act  | !act | act
+  // !act | act  | act
+  // act  | act  | act
+  //
+  function automatic mubi32_t mubi32_or(mubi32_t a, mubi32_t b, mubi32_t act);
+    logic [MuBi32Width-1:0] a_in, b_in, act_in, out;
+    a_in = a;
+    b_in = b;
+    act_in = act;
+    for (int k = 0; k < MuBi32Width; k++) begin
+      if (act_in[k]) begin
+        out[k] = a_in[k] || b_in[k];
+      end else begin
+        out[k] = a_in[k] && b_in[k];
+      end
+    end
+    return mubi32_t'(out);
+  endfunction : mubi32_or
+
+  // Performs a logical AND operation between two multibit values.
+  // This treats "act" as logical 1, and all other values are
+  // treated as 0. Truth table:
+  //
+  // A    | B    | OUT
+  //------+------+-----
+  // !act | !act | !act
+  // act  | !act | !act
+  // !act | act  | !act
+  // act  | act  | act
+  //
+  function automatic mubi32_t mubi32_and(mubi32_t a, mubi32_t b, mubi32_t act);
+    logic [MuBi32Width-1:0] a_in, b_in, act_in, out;
+    a_in = a;
+    b_in = b;
+    act_in = act;
+    for (int k = 0; k < MuBi32Width; k++) begin
+      if (act_in[k]) begin
+        out[k] = a_in[k] && b_in[k];
+      end else begin
+        out[k] = a_in[k] || b_in[k];
+      end
+    end
+    return mubi32_t'(out);
+  endfunction : mubi32_and
+
+  // Performs a logical OR operation between two multibit values.
+  // This treats "True" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi32_t mubi32_or_hi(mubi32_t a, mubi32_t b);
+    return mubi32_or(a, b, MuBi32True);
+  endfunction : mubi32_or_hi
+
+  // Performs a logical AND operation between two multibit values.
+  // This treats "True" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi32_t mubi32_and_hi(mubi32_t a, mubi32_t b);
+    return mubi32_and(a, b, MuBi32True);
+  endfunction : mubi32_and_hi
+
+  // Performs a logical OR operation between two multibit values.
+  // This treats "False" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi32_t mubi32_or_lo(mubi32_t a, mubi32_t b);
+    return mubi32_or(a, b, MuBi32False);
+  endfunction : mubi32_or_lo
+
+  // Performs a logical AND operation between two multibit values.
+  // This treats "False" as logical 1, and all other values are
+  // treated as 0.
+  function automatic mubi32_t mubi32_and_lo(mubi32_t a, mubi32_t b);
+    return mubi32_and(a, b, MuBi32False);
+  endfunction : mubi32_and_lo
+
 endpackage : prim_mubi_pkg
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_multibit_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_multibit_sync.sv
index 79a3ab6d..0a1a7956 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_multibit_sync.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_multibit_sync.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_check.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_check.sv
index d2b56f87..9e76d79c 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_check.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_check.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -137,19 +137,20 @@ module prim_onehot_check #(
     assign addr_err = 1'b0;
   end
 
-  // This logic that will be assign to one, when user adds macro
-  // ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT to check the error with alert, in case that
-  // prim_onehot_check is used in design without adding this assertion check.
-  `ifdef INC_ASSERT
-  `ifndef PRIM_DEFAULT_IMPL
-    `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
-  `endif
-  parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
-
+  // We want to know that a block that instantiates prim_onehot_check will raise an alert if we set
+  // our err_o output.
+  //
+  // For confidence that this is true, we use the scheme described in "Security Countermeasure
+  // Verification Framework". We expect a user of prim_onehot_check to use the
+  // ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT macro to check that they will indeed raise an alert if we
+  // set err_o.
+  //
+  // That macro is also designed to drive our local unused_assert_connected variable to true. We add
+  // an assertion locally that checks (just after the start of time) that it is indeed true. This
+  // gives us confidence that the user has bound up the alert correctly.
+`ifdef INC_ASSERT
   logic unused_assert_connected;
-  // TODO(#13337): only check generic for now. The path of this prim in other Impl may differ
-  if (Impl == prim_pkg::ImplGeneric) begin : gen_generic
-    `ASSERT_INIT_NET(AssertConnected_A, unused_assert_connected === 1'b1 || !EnableAlertTriggerSVA)
-  end
-  `endif
+  `ASSERT_INIT_NET(AssertConnected_A, unused_assert_connected === 1'b1 || !EnableAlertTriggerSVA)
+`endif
+
 endmodule : prim_onehot_check
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_enc.sv
index 35ecee1d..dd58753b 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_mux.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_mux.sv
index 70bd2c38..16d377d6 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_mux.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_onehot_mux.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_otp_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_otp_pkg.sv
index 0b7ffc91..cefe43a5 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_otp_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_otp_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -6,13 +6,37 @@
 
 package prim_otp_pkg;
 
-  parameter int CmdWidth = 2;
+  // The command is sparsely encoded to make it more difficult to tamper with.
+  parameter int CmdWidth = 7;
   parameter int ErrWidth = 3;
 
+  // Encoding generated with:
+  // $ ./util/design/sparse-fsm-encode.py -d 4 -m 5 -n 7 \
+  //     -s 696743973 --language=sv
+  //
+  // Hamming distance histogram:
+  //
+  //  0: --
+  //  1: --
+  //  2: --
+  //  3: --
+  //  4: |||||||||||||||||||| (100.00%)
+  //  5: --
+  //  6: --
+  //  7: --
+  //
+  // Minimum Hamming distance: 4
+  // Maximum Hamming distance: 4
+  // Minimum Hamming weight: 3
+  // Maximum Hamming weight: 5
+  //
   typedef enum logic [CmdWidth-1:0] {
-    Read  = 2'b00,
-    Write = 2'b01,
-    Init  = 2'b11
+    Read     = 7'b1000101,
+    Write    = 7'b0110111,
+    // Raw commands ignore integrity
+    ReadRaw  = 7'b1111001,
+    WriteRaw = 7'b1100010,
+    Init     = 7'b0101100
   } cmd_e;
 
   typedef enum logic [ErrWidth-1:0] {
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_packer.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_packer.sv
index 106d1dd3..76339b42 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_packer.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_packer.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -133,17 +133,18 @@ module prim_packer #(
       .clk_i,
       .rst_ni,
 
-      .clr_i      (flush_done),
+      .clr_i              (flush_done),
 
-      .set_i      (cnt_set_en),
-      .set_cnt_i  (cnt_set   ),
+      .set_i              (cnt_set_en),
+      .set_cnt_i          (cnt_set   ),
 
-      .incr_en_i  (cnt_incr_en),
-      .decr_en_i  (cnt_decr_en),
-      .step_i     (cnt_step   ),
+      .incr_en_i          (cnt_incr_en),
+      .decr_en_i          (cnt_decr_en),
+      .step_i             (cnt_step   ),
+      .commit_i           (1'b1       ),
 
-      .cnt_o      (pos_q     ), // Current counter state
-      .cnt_next_o (          ), // Next counter state
+      .cnt_o              (pos_q     ), // Current counter state
+      .cnt_after_commit_o (          ), // Next counter state
 
       .err_o
     );
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_packer_fifo.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_packer_fifo.sv
index 95c143da..1f78e777 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_packer_fifo.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_packer_fifo.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -66,6 +66,7 @@ module prim_packer_fifo #(
 
   localparam int unsigned   WidthRatio = MaxW / MinW;
   localparam bit [DepthW:0] FullDepth = WidthRatio[DepthW:0];
+  localparam bit [DepthW:0] DepthOne = 1;
 
   // signals
   logic  load_data;
@@ -103,7 +104,7 @@ module prim_packer_fifo #(
     assign load_data = wvalid_i && wready_o;
 
     assign depth_d =  clear_status ? '0 :
-           load_data ? depth_q+1 :
+           load_data ? (depth_q + DepthOne):
            depth_q;
 
     assign data_d = clear_data ? '0 :
@@ -140,11 +141,11 @@ module prim_packer_fifo #(
 
     assign depth_d =  clear_status ? '0 :
            load_data ? max_value :
-           pull_data ? depth_q-1 :
+           pull_data ? (depth_q - DepthOne) :
            depth_q;
 
     assign ptr_d =  clear_status ? '0 :
-           pull_data ? ptr_q+1 :
+           pull_data ? (ptr_q + DepthOne) :
            ptr_q;
 
     assign data_d = clear_data ? '0 :
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_pad_wrapper_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_pad_wrapper_pkg.sv
index 05acab6a..66870669 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_pad_wrapper_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_pad_wrapper_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -27,6 +27,7 @@ package prim_pad_wrapper_pkg;
   typedef struct packed {
     logic [DriveStrDw-1:0] drive_strength; // Drive strength (0000: weakest, 1111: strongest).
     logic [SlewRateDw-1:0] slew_rate;      // Slew rate (0: slowest, 11: fastest).
+    logic input_disable;                   // Input disable.
     logic od_en;                           // Open-drain enable
     logic schmitt_en;                      // Schmitt trigger enable.
     logic keep_en;                         // Keeper enable.
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_present.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_present.sv
index 76c03bc3..d3621558 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_present.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_present.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_prince.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_prince.sv
index 779999c1..5878823d 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_prince.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_prince.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_pulse_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_pulse_sync.sv
index 4ce7a7e9..44d9b5f8 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_pulse_sync.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_pulse_sync.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -7,6 +7,9 @@
 // cycle of its respective clock domain. Consecutive pulses need to be spaced
 // appropriately apart from each other depending on the clock frequency ratio
 // of the two clock domains.
+//
+// Also note that a reset of either the source domain or the destination domain
+// in isolation may create a pulse at the destination.
 
 module prim_pulse_sync (
   // source clock domain
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_adv.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_adv.sv
index 71bd99b0..73a973e3 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_adv.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_adv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -47,9 +47,20 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #(
   output logic [1:0]         rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
 
   // config
-  input ram_1p_cfg_t         cfg_i
+  input ram_1p_cfg_t         cfg_i,
+
+  // When detecting multi-bit encoding errors, raise alert.
+  output logic               alert_o
 );
 
+  import prim_mubi_pkg::mubi4_t;
+  import prim_mubi_pkg::mubi4_and_hi;
+  import prim_mubi_pkg::mubi4_bool_to_mubi;
+  import prim_mubi_pkg::mubi4_test_invalid;
+  import prim_mubi_pkg::mubi4_test_true_loose;
+  import prim_mubi_pkg::MuBi4True;
+  import prim_mubi_pkg::MuBi4False;
+  import prim_mubi_pkg::MuBi4Width;
 
   `ASSERT_INIT(CannotHaveEccAndParity_A, !(EnableParity && EnableECC))
 
@@ -74,15 +85,22 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #(
   // RAM Primitive Instance //
   ////////////////////////////
 
-  logic                    req_q,    req_d ;
-  logic                    write_q,  write_d ;
-  logic [Aw-1:0]           addr_q,   addr_d ;
-  logic [TotalWidth-1:0]   wdata_q,  wdata_d ;
-  logic [TotalWidth-1:0]   wmask_q,  wmask_d ;
-  logic                    rvalid_q, rvalid_d, rvalid_sram_q ;
-  logic [Width-1:0]        rdata_q,  rdata_d ;
+  mubi4_t                  req_q,     req_d,    req_buf_d ;
+  logic [MuBi4Width-1:0]   req_buf_b_d;
+  logic                    req_q_b ;
+  mubi4_t                  write_q,   write_d,  write_buf_d ;
+  logic [MuBi4Width-1:0]   write_buf_b_d;
+  logic                    write_q_b ;
+  logic [Aw-1:0]           addr_q,    addr_d ;
+  logic [TotalWidth-1:0]   wdata_q,   wdata_d ;
+  logic [TotalWidth-1:0]   wmask_q,   wmask_d ;
+  mubi4_t                  rvalid_q,  rvalid_d, rvalid_sram_q, rvalid_sram_d ;
+  logic [Width-1:0]        rdata_q,   rdata_d ;
   logic [TotalWidth-1:0]   rdata_sram ;
-  logic [1:0]              rerror_q, rerror_d ;
+  logic [1:0]              rerror_q,  rerror_d ;
+
+  assign req_q_b = mubi4_test_true_loose(req_q);
+  assign write_q_b = mubi4_test_true_loose(write_q);
 
   prim_ram_1p #(
     .MemInitFile     (MemInitFile),
@@ -93,8 +111,8 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #(
   ) u_mem (
     .clk_i,
 
-    .req_i    (req_q),
-    .write_i  (write_q),
+    .req_i    (req_q_b),
+    .write_i  (write_q_b),
     .addr_i   (addr_q),
     .wdata_i  (wdata_q),
     .wmask_i  (wmask_q),
@@ -102,21 +120,41 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #(
     .cfg_i
   );
 
+  assign rvalid_sram_d = mubi4_and_hi(req_q, mubi4_t'(~write_q));
+
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
-      rvalid_sram_q <= 1'b0;
+      rvalid_sram_q <= MuBi4False;
     end else begin
-      rvalid_sram_q <= req_q & ~write_q;
+      rvalid_sram_q <= rvalid_sram_d;
     end
   end
 
-  assign req_d              = req_i;
-  assign write_d            = write_i;
+  assign req_d              = mubi4_bool_to_mubi(req_i);
+  assign write_d            = mubi4_bool_to_mubi(write_i);
   assign addr_d             = addr_i;
-  assign rvalid_o           = rvalid_q;
+  assign rvalid_o           = mubi4_test_true_loose(rvalid_q);
   assign rdata_o            = rdata_q;
   assign rerror_o           = rerror_q;
 
+  prim_buf #(
+    .Width(MuBi4Width)
+  ) u_req_d_buf (
+    .in_i (req_d),
+    .out_o(req_buf_b_d)
+  );
+
+  assign req_buf_d = mubi4_t'(req_buf_b_d);
+
+  prim_buf #(
+    .Width(MuBi4Width)
+  ) u_write_d_buf (
+    .in_i (write_d),
+    .out_o(write_buf_b_d)
+  );
+
+  assign write_buf_d = mubi4_t'(write_buf_b_d);
+
   /////////////////////////////
   // ECC / Parity Generation //
   /////////////////////////////
@@ -222,24 +260,55 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #(
 
   if (EnableInputPipeline) begin : gen_regslice_input
     // Put the register slices between ECC encoding to SRAM port
+
+    // If no ECC or parity is used, do not use prim_flop to allow synthesis
+    // tool to optimize the registers.
+    if (EnableECC || EnableParity) begin : gen_prim_flop
+      prim_flop #(
+        .Width(MuBi4Width),
+        .ResetValue(MuBi4Width'(MuBi4False))
+      ) u_write_flop (
+        .clk_i,
+        .rst_ni,
+        .d_i(MuBi4Width'(write_buf_d)),
+        .q_o({write_q})
+      );
+
+      prim_flop #(
+        .Width(MuBi4Width),
+        .ResetValue(MuBi4Width'(MuBi4False))
+      ) u_req_flop (
+        .clk_i,
+        .rst_ni,
+        .d_i(MuBi4Width'(req_buf_d)),
+        .q_o({req_q})
+      );
+    end else begin: gen_no_prim_flop
+      always_ff @(posedge clk_i or negedge rst_ni) begin
+        if (!rst_ni) begin
+          write_q <= MuBi4False;
+          req_q   <= MuBi4False;
+        end else begin
+          write_q <= write_buf_d;
+          req_q   <= req_buf_d;
+        end
+      end
+    end
+
     always_ff @(posedge clk_i or negedge rst_ni) begin
       if (!rst_ni) begin
-        req_q   <= '0;
-        write_q <= '0;
         addr_q  <= '0;
         wdata_q <= '0;
         wmask_q <= '0;
       end else begin
-        req_q   <= req_d;
-        write_q <= write_d;
         addr_q  <= addr_d;
         wdata_q <= wdata_d;
         wmask_q <= wmask_d;
       end
     end
   end else begin : gen_dirconnect_input
-    assign req_q   = req_d;
-    assign write_q = write_d;
+    assign req_q   = req_buf_d;
+    assign write_q = write_buf_d;
     assign addr_q  = addr_d;
     assign wdata_q = wdata_d;
     assign wmask_q = wmask_d;
@@ -247,23 +316,47 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #(
 
   if (EnableOutputPipeline) begin : gen_regslice_output
     // Put the register slices between ECC decoding to output
+
+    // If no ECC or parity is used, do not use prim_flop to allow synthesis
+    // tool to optimize the registers.
+    if (EnableECC || EnableParity) begin : gen_prim_rvalid_flop
+      prim_flop #(
+        .Width(MuBi4Width),
+        .ResetValue(MuBi4Width'(MuBi4False))
+      ) u_rvalid_flop (
+        .clk_i,
+        .rst_ni,
+        .d_i(MuBi4Width'(rvalid_d)),
+        .q_o({rvalid_q})
+      );
+    end else begin: gen_no_prim_rvalid_flop
+      always_ff @(posedge clk_i or negedge rst_ni) begin
+        if (!rst_ni) begin
+          rvalid_q <= MuBi4False;
+        end else begin
+          rvalid_q <= rvalid_d;
+        end
+      end
+    end
+
     always_ff @(posedge clk_i or negedge rst_ni) begin
       if (!rst_ni) begin
-        rvalid_q <= '0;
         rdata_q  <= '0;
         rerror_q <= '0;
       end else begin
-        rvalid_q <= rvalid_d;
         rdata_q  <= rdata_d;
         // tie to zero if the read data is not valid
-        rerror_q <= rerror_d & {2{rvalid_d}};
+        rerror_q <= rerror_d & {2{mubi4_test_true_loose(rvalid_d)}};
       end
     end
   end else begin : gen_dirconnect_output
     assign rvalid_q = rvalid_d;
     assign rdata_q  = rdata_d;
     // tie to zero if the read data is not valid
-    assign rerror_q = rerror_d & {2{rvalid_d}};
+    assign rerror_q = rerror_d & {2{mubi4_test_true_loose(rvalid_d)}};
   end
 
+  assign alert_o = mubi4_test_invalid(req_q) | mubi4_test_invalid(write_q) |
+                   mubi4_test_invalid(rvalid_q) | mubi4_test_invalid(rvalid_sram_q);
+
 endmodule : prim_ram_1p_adv
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
index d4796292..4aefd25f 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_scr.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_scr.sv
index 30655819..d31a7d5c 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_scr.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_scr.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -31,11 +31,14 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
 
   // Scrambling parameters. Note that this needs to be low-latency, hence we have to keep the
   // amount of cipher rounds low. PRINCE has 5 half rounds in its original form, which corresponds
-  // to 2*5 + 1 effective rounds. Setting this to 2 halves this to approximately 5 effective rounds.
+  // to 2*5 + 1 effective rounds. Setting this to 3 lowers this to approximately 7 effective rounds.
   // Number of PRINCE half rounds, can be [1..5]
-  parameter  int NumPrinceRoundsHalf = 2,
-  // Number of extra diffusion rounds. Setting this to 0 to disable diffusion.
-  parameter  int NumDiffRounds       = 2,
+  parameter  int NumPrinceRoundsHalf = 3,
+  // Number of extra diffusion rounds. Setting this to 0 to disables diffusion.
+  // NOTE: this is zero by default, since the non-linear transformation of data bits can interact
+  // adversely with end-to-end ECC integrity. Only enable this if you know what you are doing
+  // (e.g. using this primitive in a different context with byte parity). See #20788 for context.
+  parameter  int NumDiffRounds       = 0,
   // This parameter governs the block-width of additional diffusion layers.
   // For intra-byte diffusion, set this parameter to 8.
   parameter  int DiffWidth           = DataBitsPerMask,
@@ -80,9 +83,26 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
   output logic [31:0]               raddr_o,  // Read address for error reporting.
 
   // config
-  input ram_1p_cfg_t                cfg_i
+  input ram_1p_cfg_t                cfg_i,
+
+  // Write currently pending inside this module.
+  output logic                      wr_collision_o,
+  output logic                      write_pending_o,
+
+  // When detecting multi-bit encoding errors, raise alert.
+  output logic                      alert_o
 );
 
+  import prim_mubi_pkg::mubi4_t;
+  import prim_mubi_pkg::mubi4_and_hi;
+  import prim_mubi_pkg::mubi4_bool_to_mubi;
+  import prim_mubi_pkg::mubi4_or_hi;
+  import prim_mubi_pkg::mubi4_test_invalid;
+  import prim_mubi_pkg::mubi4_test_true_loose;
+  import prim_mubi_pkg::MuBi4True;
+  import prim_mubi_pkg::MuBi4False;
+  import prim_mubi_pkg::MuBi4Width;
+
   //////////////////////
   // Parameter Checks //
   //////////////////////
@@ -105,17 +125,51 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
   // the data from the write holding register.
 
   // Read / write strobes
-  logic read_en, write_en_d, write_en_q;
+  mubi4_t read_en, read_en_buf;
+  logic   read_en_b;
+  mubi4_t write_en_d, write_en_buf_d, write_en_q;
+  logic   write_en_b;
+  logic [MuBi4Width-1:0] read_en_b_buf, write_en_buf_b_d;
   assign gnt_o = req_i & key_valid_i;
 
-  assign read_en = gnt_o & ~write_i;
-  assign write_en_d = gnt_o & write_i;
+  assign read_en = mubi4_bool_to_mubi(gnt_o & ~write_i);
+  assign write_en_d = mubi4_bool_to_mubi(gnt_o & write_i);
+
+  prim_buf #(
+    .Width(MuBi4Width)
+  ) u_read_en_buf (
+    .in_i (read_en),
+    .out_o(read_en_b_buf)
+  );
+
+  assign read_en_buf = mubi4_t'(read_en_b_buf);
+
+  prim_buf #(
+    .Width(MuBi4Width)
+  ) u_write_en_d_buf (
+    .in_i (write_en_d),
+    .out_o(write_en_buf_b_d)
+  );
+
+  assign write_en_buf_d = mubi4_t'(write_en_buf_b_d);
 
-  logic write_pending_q;
-  logic addr_collision_d, addr_collision_q;
+  mubi4_t write_pending_q;
+  mubi4_t addr_collision_d, addr_collision_q;
   logic [AddrWidth-1:0] addr_scr;
   logic [AddrWidth-1:0] waddr_scr_q;
-  assign addr_collision_d = read_en & (write_en_q | write_pending_q) & (addr_scr == waddr_scr_q);
+  mubi4_t addr_match;
+  logic [MuBi4Width-1:0] addr_match_buf;
+
+  assign addr_match = (addr_scr == waddr_scr_q) ? MuBi4True : MuBi4False;
+  prim_buf #(
+    .Width(MuBi4Width)
+  ) u_addr_match_buf (
+    .in_i (addr_match),
+    .out_o(addr_match_buf)
+  );
+
+  assign addr_collision_d = mubi4_and_hi(mubi4_and_hi(mubi4_or_hi(write_en_q,
+      write_pending_q), read_en_buf), mubi4_t'(addr_match_buf));
 
   // Macro requests and write strobe
   // The macro operation is silenced if an integrity error is seen
@@ -125,13 +179,23 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
     .out_o(intg_error_buf)
   );
   logic macro_req;
-  assign macro_req   = ~intg_error_w_q & ~intg_error_buf & (read_en | write_en_q | write_pending_q);
+  assign macro_req   = ~intg_error_w_q & ~intg_error_buf &
+      mubi4_test_true_loose(mubi4_or_hi(mubi4_or_hi(read_en_buf, write_en_q), write_pending_q));
   // We are allowed to write a pending write transaction to the memory if there is no incoming read.
   logic macro_write;
-  assign macro_write = (write_en_q | write_pending_q) & ~read_en & ~intg_error_w_q;
+  assign macro_write = mubi4_test_true_loose(mubi4_or_hi(write_en_q, write_pending_q)) &
+    ~mubi4_test_true_loose(read_en_buf) & ~intg_error_w_q;
   // New read write collision
   logic rw_collision;
-  assign rw_collision = write_en_q & read_en;
+  assign rw_collision = mubi4_test_true_loose(mubi4_and_hi(write_en_q, read_en_buf));
+
+  // Write currently processed inside this module. Although we are sending an immediate d_valid
+  // back to the host, the write could take longer due to the scrambling.
+  assign write_pending_o = macro_write | mubi4_test_true_loose(write_en_buf_d);
+
+  // When a read is followed after a write with the same address, we return the data from the
+  // holding register.
+  assign wr_collision_o = mubi4_test_true_loose(addr_collision_q);
 
   ////////////////////////
   // Address Scrambling //
@@ -139,7 +203,7 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
 
   // We only select the pending write address in case there is no incoming read transaction.
   logic [AddrWidth-1:0] addr_mux;
-  assign addr_mux = (read_en) ? addr_scr : waddr_scr_q;
+  assign addr_mux = (mubi4_test_true_loose(read_en_buf)) ? addr_scr : waddr_scr_q;
 
   // This creates a bijective address mapping using a substitution / permutation network.
   if (NumAddrScrRounds > 0) begin : gen_addr_scr
@@ -293,9 +357,9 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
 
   // Clear this if we can write the memory in this cycle. Set only if the current write cannot
   // proceed due to an incoming read operation.
-  logic write_scr_pending_d;
-  assign write_scr_pending_d = (macro_write)  ? 1'b0 :
-                               (rw_collision) ? 1'b1 :
+  mubi4_t write_scr_pending_d;
+  assign write_scr_pending_d = (macro_write)  ? MuBi4False :
+                               (rw_collision) ? MuBi4True :
                                                 write_pending_q;
 
   // Select the correct scrambled word to be written, based on whether the word in the scrambled
@@ -303,20 +367,20 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
   // combined with the wdata_q register. We don't do that here for timing reasons, since that would
   // require another read data mux to inject the scrambled data into the read descrambling path.
   logic [Width-1:0] wdata_scr;
-  assign wdata_scr = (write_pending_q) ? wdata_scr_q : wdata_scr_d;
+  assign wdata_scr = (mubi4_test_true_loose(write_pending_q)) ? wdata_scr_q : wdata_scr_d;
 
-  logic rvalid_q;
+  mubi4_t rvalid_q;
   logic intg_error_r_q;
   logic [Width-1:0] wmask_q;
   always_comb begin : p_forward_mux
     rdata_o = '0;
     rvalid_o = 1'b0;
     // Kill the read response in case an integrity error was seen.
-    if (!intg_error_r_q && rvalid_q) begin
+    if (!intg_error_r_q && mubi4_test_true_loose(rvalid_q)) begin
       rvalid_o = 1'b1;
       // In case of a collision, we forward the valid bytes of the write data from the unscrambled
       // holding register.
-      if (addr_collision_q) begin
+      if (mubi4_test_true_loose(addr_collision_q)) begin
         for (int k = 0; k < Width; k++) begin
           if (wmask_q[k]) begin
             rdata_o[k] = wdata_q[k];
@@ -335,13 +399,57 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
   ///////////////
   // Registers //
   ///////////////
+  logic ram_alert;
+
+  assign alert_o = mubi4_test_invalid(write_en_q) | mubi4_test_invalid(addr_collision_q) |
+                   mubi4_test_invalid(write_pending_q) | mubi4_test_invalid(rvalid_q) |
+                   ram_alert;
+
+  prim_flop #(
+    .Width(MuBi4Width),
+    .ResetValue(MuBi4Width'(MuBi4False))
+  ) u_write_en_flop (
+    .clk_i,
+    .rst_ni,
+    .d_i(MuBi4Width'(write_en_buf_d)),
+    .q_o({write_en_q})
+  );
+
+  prim_flop #(
+    .Width(MuBi4Width),
+    .ResetValue(MuBi4Width'(MuBi4False))
+  ) u_addr_collision_flop (
+    .clk_i,
+    .rst_ni,
+    .d_i(MuBi4Width'(addr_collision_d)),
+    .q_o({addr_collision_q})
+  );
+
+  prim_flop #(
+    .Width(MuBi4Width),
+    .ResetValue(MuBi4Width'(MuBi4False))
+  ) u_write_pending_flop (
+    .clk_i,
+    .rst_ni,
+    .d_i(MuBi4Width'(write_scr_pending_d)),
+    .q_o({write_pending_q})
+  );
+
+  prim_flop #(
+    .Width(MuBi4Width),
+    .ResetValue(MuBi4Width'(MuBi4False))
+  ) u_rvalid_flop (
+    .clk_i,
+    .rst_ni,
+    .d_i(MuBi4Width'(read_en_buf)),
+    .q_o({rvalid_q})
+  );
+
+  assign read_en_b = mubi4_test_true_loose(read_en_buf);
+  assign write_en_b = mubi4_test_true_loose(write_en_buf_d);
 
   always_ff @(posedge clk_i or negedge rst_ni) begin : p_wdata_buf
     if (!rst_ni) begin
-      write_pending_q     <= 1'b0;
-      addr_collision_q    <= 1'b0;
-      rvalid_q            <= 1'b0;
-      write_en_q          <= 1'b0;
       intg_error_r_q      <= 1'b0;
       intg_error_w_q      <= 1'b0;
       raddr_q             <= '0;
@@ -350,16 +458,12 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
       wdata_q             <= '0;
       wdata_scr_q         <= '0;
     end else begin
-      write_pending_q     <= write_scr_pending_d;
-      addr_collision_q    <= addr_collision_d;
-      rvalid_q            <= read_en;
-      write_en_q          <= write_en_d;
       intg_error_r_q      <= intg_error_buf;
 
-      if (read_en) begin
+      if (read_en_b) begin
         raddr_q <= addr_i;
       end
-      if (write_en_d) begin
+      if (write_en_b) begin
         waddr_scr_q    <= addr_scr;
         wmask_q        <= wmask_i;
         wdata_q        <= wdata_i;
@@ -394,7 +498,8 @@ module prim_ram_1p_scr import prim_ram_1p_pkg::*; #(
     .rdata_o  ( rdata_scr   ),
     .rvalid_o ( ),
     .rerror_o,
-    .cfg_i
+    .cfg_i,
+    .alert_o  ( ram_alert   )
   );
 
   `include "prim_util_get_scramble_params.svh"
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1r1w_adv.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1r1w_adv.sv
new file mode 100644
index 00000000..a2924433
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1r1w_adv.sv
@@ -0,0 +1,83 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Two-Port SRAM Wrapper
+//
+// Supported configurations:
+// - ECC for 32b and 64b wide memories with no write mask
+//   (Width == 32 or Width == 64, DataBitsPerMask is ignored).
+// - Byte parity if Width is a multiple of 8 bit and write masks have Byte
+//   granularity (DataBitsPerMask == 8).
+//
+// Note that the write mask needs to be per Byte if parity is enabled. If ECC is enabled, the write
+// mask cannot be used and has to be tied to {Width{1'b1}}.
+
+`include "prim_assert.sv"
+
+module prim_ram_1r1w_adv import prim_ram_2p_pkg::*; #(
+  parameter  int Depth                = 512,
+  parameter  int Width                = 32,
+  parameter  int DataBitsPerMask      = 1,  // Number of data bits per bit of write mask
+  parameter      MemInitFile          = "", // VMEM file to initialize the memory with
+
+  // Configurations
+  parameter  bit EnableECC            = 0, // Enables per-word ECC
+  parameter  bit EnableParity         = 0, // Enables per-Byte Parity
+  parameter  bit EnableInputPipeline  = 0, // Adds an input register (read latency +1)
+  parameter  bit EnableOutputPipeline = 0, // Adds an output register (read latency +1)
+
+  // This switch allows to switch to standard Hamming ECC instead of the HSIAO ECC.
+  // It is recommended to leave this parameter at its default setting (HSIAO),
+  // since this results in a more compact and faster implementation.
+  parameter bit HammingECC            = 0,
+
+  localparam int Aw                   = prim_util_pkg::vbits(Depth)
+) (
+  input                    clk_i,
+  input                    rst_ni,
+
+  // Port A can only write
+  input                    a_req_i,
+  input        [Aw-1:0]    a_addr_i,
+  input        [Width-1:0] a_wdata_i,
+  input        [Width-1:0] a_wmask_i,  // cannot be used with ECC, tie to 1 in that case
+
+  // Port B can only read
+  input                    b_req_i,
+  input        [Aw-1:0]    b_addr_i,
+  output logic [Width-1:0] b_rdata_o,
+  output logic             b_rvalid_o, // read response (b_rdata_o) is valid
+  output logic [1:0]       b_rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
+
+  input ram_2p_cfg_t       cfg_i
+);
+
+  prim_ram_1r1w_async_adv #(
+    .Depth               (Depth),
+    .Width               (Width),
+    .DataBitsPerMask     (DataBitsPerMask),
+    .MemInitFile         (MemInitFile),
+    .EnableECC           (EnableECC),
+    .EnableParity        (EnableParity),
+    .EnableInputPipeline (EnableInputPipeline),
+    .EnableOutputPipeline(EnableOutputPipeline),
+    .HammingECC          (HammingECC)
+  ) i_prim_ram_1r1w_async_adv (
+    .clk_a_i(clk_i),
+    .rst_a_ni(rst_ni),
+    .clk_b_i(clk_i),
+    .rst_b_ni(rst_ni),
+    .a_req_i,
+    .a_addr_i,
+    .a_wdata_i,
+    .a_wmask_i,
+    .b_req_i,
+    .b_addr_i,
+    .b_rdata_o,
+    .b_rvalid_o,
+    .b_rerror_o,
+    .cfg_i
+  );
+
+endmodule : prim_ram_1r1w_adv
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1r1w_async_adv.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1r1w_async_adv.sv
new file mode 100644
index 00000000..6e9d31b5
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1r1w_async_adv.sv
@@ -0,0 +1,264 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Asynchronous Two-Port SRAM Wrapper
+//
+// Supported configurations:
+// - ECC for 32b and 64b wide memories with no write mask
+//   (Width == 32 or Width == 64, DataBitsPerMask is ignored).
+// - Byte parity if Width is a multiple of 8 bit and write masks have Byte
+//   granularity (DataBitsPerMask == 8).
+//
+// Note that the write mask needs to be per Byte if parity is enabled. If ECC is enabled, the write
+// mask cannot be used and has to be tied to {Width{1'b1}}.
+
+`include "prim_assert.sv"
+
+module prim_ram_1r1w_async_adv import prim_ram_2p_pkg::*; #(
+  parameter  int Depth                = 512,
+  parameter  int Width                = 32,
+  parameter  int DataBitsPerMask      = 1,  // Number of data bits per bit of write mask
+  parameter      MemInitFile          = "", // VMEM file to initialize the memory with
+
+  // Configurations
+  parameter  bit EnableECC            = 0, // Enables per-word ECC
+  parameter  bit EnableParity         = 0, // Enables per-Byte Parity
+  parameter  bit EnableInputPipeline  = 0, // Adds an input register (read latency +1)
+  parameter  bit EnableOutputPipeline = 0, // Adds an output register (read latency +1)
+
+  // This switch allows to switch to standard Hamming ECC instead of the HSIAO ECC.
+  // It is recommended to leave this parameter at its default setting (HSIAO),
+  // since this results in a more compact and faster implementation.
+  parameter bit HammingECC            = 0,
+
+  localparam int Aw                   = prim_util_pkg::vbits(Depth)
+) (
+  input clk_a_i,
+  input clk_b_i,
+  input rst_a_ni,
+  input rst_b_ni,
+
+  // Port A can only write
+  input                    a_req_i,
+  input        [Aw-1:0]    a_addr_i,
+  input        [Width-1:0] a_wdata_i,
+  input        [Width-1:0] a_wmask_i,  // cannot be used with ECC, tie to 1 in that case
+
+  // Port B can only read
+  input                    b_req_i,
+  input        [Aw-1:0]    b_addr_i,
+  output logic [Width-1:0] b_rdata_o,
+  output logic             b_rvalid_o, // read response (b_rdata_o) is valid
+  output logic [1:0]       b_rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
+
+  // config
+  input ram_2p_cfg_t       cfg_i
+);
+
+
+  `ASSERT_INIT(CannotHaveEccAndParity_A, !(EnableParity && EnableECC))
+
+  // Calculate ECC width
+  localparam int ParWidth  = (EnableParity) ? Width/8 :
+                             (!EnableECC)   ? 0 :
+                             (Width <=   4) ? 4 :
+                             (Width <=  11) ? 5 :
+                             (Width <=  26) ? 6 :
+                             (Width <=  57) ? 7 :
+                             (Width <= 120) ? 8 : 8 ;
+  localparam int TotalWidth = Width + ParWidth;
+
+  // If byte parity is enabled, the write enable bits are used to write memory colums
+  // with 8 + 1 = 9 bit width (data plus corresponding parity bit).
+  // If ECC is enabled, the DataBitsPerMask is ignored.
+  localparam int LocalDataBitsPerMask = (EnableParity) ? 9          :
+                                        (EnableECC)    ? TotalWidth :
+                                                         DataBitsPerMask;
+
+  ////////////////////////////
+  // RAM Primitive Instance //
+  ////////////////////////////
+
+  logic                    a_req_q,    a_req_d ;
+  logic [Aw-1:0]           a_addr_q,   a_addr_d ;
+  logic [TotalWidth-1:0]   a_wdata_q,  a_wdata_d ;
+  logic [TotalWidth-1:0]   a_wmask_q,  a_wmask_d ;
+
+  logic                    b_req_q,    b_req_d ;
+  logic [Aw-1:0]           b_addr_q,   b_addr_d ;
+  logic                    b_rvalid_q, b_rvalid_d, b_rvalid_sram_q ;
+  logic [Width-1:0]        b_rdata_q,  b_rdata_d ;
+  logic [TotalWidth-1:0]   b_rdata_sram ;
+  logic [1:0]              b_rerror_q, b_rerror_d ;
+
+  prim_ram_1r1w #(
+    .MemInitFile     (MemInitFile),
+
+    .Width           (TotalWidth),
+    .Depth           (Depth),
+    .DataBitsPerMask (LocalDataBitsPerMask)
+  ) u_mem (
+    .clk_a_i    (clk_a_i),
+    .clk_b_i    (clk_b_i),
+
+    .a_req_i    (a_req_q),
+    .a_addr_i   (a_addr_q),
+    .a_wdata_i  (a_wdata_q),
+    .a_wmask_i  (a_wmask_q),
+
+    .b_req_i    (b_req_q),
+    .b_addr_i   (b_addr_q),
+    .b_rdata_o  (b_rdata_sram),
+
+    .cfg_i
+  );
+
+  always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
+    if (!rst_b_ni) begin
+      b_rvalid_sram_q <= 1'b0;
+    end else begin
+      b_rvalid_sram_q <= b_req_q;
+    end
+  end
+
+  assign a_req_d              = a_req_i;
+  assign a_addr_d             = a_addr_i;
+
+  assign b_req_d              = b_req_i;
+  assign b_addr_d             = b_addr_i;
+  assign b_rvalid_o           = b_rvalid_q;
+  assign b_rdata_o            = b_rdata_q;
+  assign b_rerror_o           = b_rerror_q;
+
+  /////////////////////////////
+  // ECC / Parity Generation //
+  /////////////////////////////
+
+  if (EnableParity == 0 && EnableECC) begin : gen_secded
+
+    // check supported widths
+    `ASSERT_INIT(SecDecWidth_A, Width inside {32})
+
+    // the wmask is constantly set to 1 in this case
+    `ASSERT(OnlyWordWritePossibleWithEccPortA_A, a_req_i |->
+        a_wmask_i == {Width{1'b1}}, clk_a_i, rst_a_ni)
+
+    assign a_wmask_d = {TotalWidth{1'b1}};
+
+    if (Width == 32) begin : gen_secded_39_32
+      if (HammingECC) begin : gen_hamming
+        prim_secded_inv_hamming_39_32_enc u_enc_a (
+          .data_i(a_wdata_i),
+          .data_o(a_wdata_d)
+        );
+        prim_secded_inv_hamming_39_32_dec u_dec_b (
+          .data_i     (b_rdata_sram),
+          .data_o     (b_rdata_d[0+:Width]),
+          .syndrome_o ( ),
+          .err_o      (b_rerror_d)
+        );
+      end else begin : gen_hsiao
+        prim_secded_inv_39_32_enc u_enc_a (
+          .data_i(a_wdata_i),
+          .data_o(a_wdata_d)
+        );
+        prim_secded_inv_39_32_dec u_dec_b (
+          .data_i     (b_rdata_sram),
+          .data_o     (b_rdata_d[0+:Width]),
+          .syndrome_o ( ),
+          .err_o      (b_rerror_d)
+        );
+      end
+    end
+  end else if (EnableParity) begin : gen_byte_parity
+
+    `ASSERT_INIT(ParityNeedsByteWriteMask_A, DataBitsPerMask == 8)
+    `ASSERT_INIT(WidthNeedsToBeByteAligned_A, Width % 8 == 0)
+
+    always_comb begin : p_parity
+      b_rerror_d = '0;
+      for (int i = 0; i < Width/8; i ++) begin
+        // Data mapping. We have to make 8+1 = 9 bit groups
+        // that have the same write enable such that FPGA tools
+        // can map this correctly to BRAM resources.
+        a_wmask_d[i*9 +: 8] = a_wmask_i[i*8 +: 8];
+        a_wdata_d[i*9 +: 8] = a_wdata_i[i*8 +: 8];
+        b_rdata_d[i*8 +: 8] = b_rdata_sram[i*9 +: 8];
+
+        // parity generation (odd parity)
+        a_wdata_d[i*9 + 8] = ~(^a_wdata_i[i*8 +: 8]);
+        a_wmask_d[i*9 + 8] = &a_wmask_i[i*8 +: 8];
+        // parity decoding (errors are always uncorrectable)
+        b_rerror_d[1] |= ~(^{b_rdata_sram[i*9 +: 8], b_rdata_sram[i*9 + 8]});
+      end
+    end
+  end else begin : gen_nosecded_noparity
+    assign a_wmask_d  = a_wmask_i;
+    assign a_wdata_d  = a_wdata_i;
+    assign b_rdata_d  = b_rdata_sram[0+:Width];
+    assign b_rerror_d = '0;
+  end
+
+  assign b_rvalid_d = b_rvalid_sram_q;
+
+  /////////////////////////////////////
+  // Input/Output Pipeline Registers //
+  /////////////////////////////////////
+
+  if (EnableInputPipeline) begin : gen_regslice_input
+    // Put the register slices between ECC encoding to SRAM port
+    always_ff @(posedge clk_a_i or negedge rst_a_ni) begin
+      if (!rst_a_ni) begin
+        a_req_q   <= '0;
+        a_addr_q  <= '0;
+        a_wdata_q <= '0;
+        a_wmask_q <= '0;
+      end else begin
+        a_req_q   <= a_req_d;
+        a_addr_q  <= a_addr_d;
+        a_wdata_q <= a_wdata_d;
+        a_wmask_q <= a_wmask_d;
+      end
+    end
+    always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
+      if (!rst_b_ni) begin
+        b_req_q   <= '0;
+        b_addr_q  <= '0;
+      end else begin
+        b_req_q   <= b_req_d;
+        b_addr_q  <= b_addr_d;
+      end
+    end
+  end else begin : gen_dirconnect_input
+    assign a_req_q   = a_req_d;
+    assign a_addr_q  = a_addr_d;
+    assign a_wdata_q = a_wdata_d;
+    assign a_wmask_q = a_wmask_d;
+
+    assign b_req_q   = b_req_d;
+    assign b_addr_q  = b_addr_d;
+  end
+
+  if (EnableOutputPipeline) begin : gen_regslice_output
+    // Put the register slices between ECC decoding to output
+    always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
+      if (!rst_b_ni) begin
+        b_rvalid_q <= '0;
+        b_rdata_q  <= '0;
+        b_rerror_q <= '0;
+      end else begin
+        b_rvalid_q <= b_rvalid_d;
+        b_rdata_q  <= b_rdata_d;
+        // tie to zero if the read data is not valid
+        b_rerror_q <= b_rerror_d & {2{b_rvalid_d}};
+      end
+    end
+  end else begin : gen_dirconnect_output
+    assign b_rvalid_q = b_rvalid_d;
+    assign b_rdata_q  = b_rdata_d;
+    // tie to zero if the read data is not valid
+    assign b_rerror_q = b_rerror_d & {2{b_rvalid_d}};
+  end
+
+endmodule : prim_ram_1r1w_async_adv
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_2p_adv.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_2p_adv.sv
index 866217a6..951ae981 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_2p_adv.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_2p_adv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_2p_async_adv.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_2p_async_adv.sv
index d3de6f67..5c93fe28 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_2p_async_adv.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_2p_async_adv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_2p_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_2p_pkg.sv
index 4ae04271..0b002b4e 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_2p_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_2p_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_reg_cdc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_reg_cdc.sv
index f323100b..94a1f50c 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_reg_cdc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_reg_cdc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -11,6 +11,17 @@
 //
 // If in the future this assumption changes, we can modify this module easily to
 // support the new behavior.
+//
+// Note on domain resets
+//
+// When a single domain is reset, assertions of the internal signals 'dst_req'
+// and/or 'src_ack' may occur as the two ends of a pulse synchronizer
+// (prim_pulse_sync or prim_sync_reqack, NRZ option) are briefly inconsistent,
+// generating a spurious pulse at the destination.
+//
+// These pulses are prevented from propagating outside of this module, provided
+// that the reset does not occur whilst a transaction is in progress; firmware
+// is responsible for preventing that.
 
 `include "prim_assert.sv"
 
@@ -77,7 +88,7 @@ module prim_reg_cdc #(
   // register.
   // When software performs a write, the write data is captured in src_q for
   // CDC purposes.  When not performing a write, the src_q reflects the most recent
-  // hardware value. For registes with no hardware access, this is simply the
+  // hardware value. For registers with no hardware access, this is simply the
   // the value programmed by software (or in the case R1C, W1C etc) the value after
   // the operation. For registers with hardware access, this reflects a potentially
   // delayed version of the real value, as the software facing updates lag real
@@ -115,7 +126,7 @@ module prim_reg_cdc #(
       // sample data whenever a busy transaction finishes OR
       // when an update pulse is seen.
       // TODO: We should add a cover group to test different sync timings
-      // between src_ack and src_update. Ie, there can be 3 scearios:
+      // between src_ack and src_update. ie. there can be 3 scenarios:
       // 1. update one cycle before ack
       // 2. ack one cycle before update
       // 3. update / ack on the same cycle
@@ -183,7 +194,9 @@ module prim_reg_cdc #(
   );
 
 
-  // Each is valid only when destination request pulse is high
+  // Each is valid only when destination request pulse is high; this is important in not propagating
+  // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
+  // reset.
   assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
 
   `ASSERT_KNOWN(SrcBusyKnown_A, src_busy_o, clk_src_i, !rst_src_ni)
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_reg_cdc_arb.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_reg_cdc_arb.sv
index 815fef89..77fe83a4 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_reg_cdc_arb.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_reg_cdc_arb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -93,7 +93,7 @@ module prim_reg_cdc_arb #(
   } state_e;
 
 
-  // Only honor the incoming destinate update request if the incoming
+  // Only honor the incoming destination update request if the incoming
   // value is actually different from what is already completed in the
   // handshake
   logic dst_update;
@@ -107,7 +107,6 @@ module prim_reg_cdc_arb #(
     req_sel_e id_q;
 
     state_e state_q, state_d;
-    // Make sure to indent the following later
     always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
       if (!rst_dst_ni) begin
         state_q <= StIdle;
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_reg_we_check.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_reg_we_check.sv
index 51373ca3..0734ec87 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_reg_we_check.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_reg_we_check.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_rom_adv.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_rom_adv.sv
index dbeec644..bfa0c5b3 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_rom_adv.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_rom_adv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_rom_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_rom_pkg.sv
index 1ac84ee0..c6c4be04 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_rom_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_rom_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_rst_sync.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_rst_sync.sv
index b499a1a8..f90a7ab4 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_rst_sync.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_rst_sync.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_sec_anchor_buf.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_sec_anchor_buf.sv
index 1ea71841..3639f144 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_sec_anchor_buf.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_sec_anchor_buf.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_sec_anchor_flop.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_sec_anchor_flop.sv
index ce18b47d..68dec7ea 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_sec_anchor_flop.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_sec_anchor_flop.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_22_16_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_22_16_dec.sv
index 4fa1196c..1bd7590f 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_22_16_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_22_16_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_22_16_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_22_16_enc.sv
index 41ad31b9..ae80637a 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_22_16_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_22_16_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_dec.sv
index 7df02e24..80e8117d 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_enc.sv
index f4e451af..4814d576 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_dec.sv
index 10ee733e..94959c88 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_enc.sv
index 5668ff3a..347b1dd6 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_64_57_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_64_57_dec.sv
index dc1fd426..bfe6b363 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_64_57_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_64_57_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_64_57_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_64_57_enc.sv
index 6e837262..071dbbde 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_64_57_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_64_57_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_dec.sv
index 112a64fd..664f093f 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_enc.sv
index 5e9f674d..a0d97db8 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_22_16_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_22_16_dec.sv
index 135dc2fd..4b838293 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_22_16_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_22_16_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_22_16_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_22_16_enc.sv
index 9eb7295e..81c1d9a8 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_22_16_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_22_16_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_39_32_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_39_32_dec.sv
index 1f41364f..da37f70c 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_39_32_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_39_32_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_39_32_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_39_32_enc.sv
index 47b60f56..4942a689 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_39_32_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_39_32_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_72_64_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_72_64_dec.sv
index 7eaaa40d..a4e43962 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_72_64_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_72_64_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_72_64_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_72_64_enc.sv
index a24f3c8f..bbddeee2 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_72_64_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_72_64_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_76_68_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_76_68_dec.sv
index 418a2331..86daf1cf 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_76_68_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_76_68_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_76_68_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_76_68_enc.sv
index 3e940838..6cd4cf2d 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_76_68_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_76_68_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_22_16_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_22_16_dec.sv
index 5d53680e..184731d4 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_22_16_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_22_16_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_22_16_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_22_16_enc.sv
index a057b0d4..c125cc39 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_22_16_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_22_16_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_28_22_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_28_22_dec.sv
index b54b6474..214f848e 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_28_22_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_28_22_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_28_22_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_28_22_enc.sv
index b1998e3c..2e6d1182 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_28_22_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_28_22_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_dec.sv
index a40a86cd..760242a7 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_enc.sv
index dedd585c..c4d03371 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_64_57_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_64_57_dec.sv
index 6e34b502..e70eec0f 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_64_57_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_64_57_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_64_57_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_64_57_enc.sv
index 99565b79..a1fcefb2 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_64_57_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_64_57_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_72_64_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_72_64_dec.sv
index aa4c5b59..ca58f0c9 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_72_64_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_72_64_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_72_64_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_72_64_enc.sv
index 87b36c4c..83fc880d 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_72_64_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_72_64_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_22_16_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_22_16_dec.sv
index 0f077ee7..11a7b48c 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_22_16_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_22_16_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_22_16_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_22_16_enc.sv
index 0b63ff60..95715e7a 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_22_16_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_22_16_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_39_32_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_39_32_dec.sv
index f65e86d5..7981dbbd 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_39_32_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_39_32_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_39_32_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_39_32_enc.sv
index ee988db4..1f17fc5b 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_39_32_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_39_32_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_72_64_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_72_64_dec.sv
index 99c2e5de..9a3c9052 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_72_64_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_72_64_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_72_64_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_72_64_enc.sv
index 3a47ca5c..d109fc3f 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_72_64_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_72_64_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_76_68_dec.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_76_68_dec.sv
index c2aa75e4..6128e1e1 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_76_68_dec.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_76_68_dec.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_76_68_enc.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_76_68_enc.sv
index 324f9c6b..6e798bdf 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_76_68_enc.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_hamming_76_68_enc.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
index 4c17534a..b5782845 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_sha2.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_sha2.sv
new file mode 100644
index 00000000..e2a571cd
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_sha2.sv
@@ -0,0 +1,487 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SHA-256/384/512 configurable mode engine (64-bit word datapath)
+
+module prim_sha2 import prim_sha2_pkg::*;
+#(
+  parameter bit MultimodeEn = 0, // assert to enable multi-mode digest feature
+
+  localparam int unsigned RndWidth256 = $clog2(NumRound256),
+  localparam int unsigned RndWidth512 = $clog2(NumRound512),
+  localparam sha_word64_t ZeroWord      = '0
+ ) (
+  input clk_i,
+  input rst_ni,
+
+  input               wipe_secret_i,
+  input sha_word32_t  wipe_v_i,
+  // control signals and message words input to the message FIFO
+  input               fifo_rvalid_i, // indicates that the message FIFO (prim_sync_fifo) has words
+                                     // ready to write into the SHA-2 padding buffer
+  input  sha_fifo64_t fifo_rdata_i,
+  output logic        fifo_rready_o, // indicates the internal padding buffer is ready to receive
+                                     // words from the message FIFO
+  // control signals
+  input               sha_en_i,   // if disabled, it clears internal content
+  input               hash_start_i, // start hashing: initialize data counter to zero and clear
+                                    // digest
+  input               hash_stop_i, // stop hashing: after all data up to message length has been
+                                   // hashed, stop without padding
+  input               hash_continue_i, // continue hashing: set data counter to `message_length_i`
+                                       // and use current digest
+  input digest_mode_e digest_mode_i,
+  input               hash_process_i,
+  output logic        hash_done_o,
+
+  input  [63:0]             message_length_i, // bits but byte based
+  input  sha_word64_t [7:0] digest_i,
+  input  logic [7:0]        digest_we_i,
+  output sha_word64_t [7:0] digest_o, // tie off unused port slice when MultimodeEn = 0
+  output logic digest_on_blk_o, // digest being computed for a complete block
+  output logic hash_running_o, // `1` iff hash computation is active (as opposed to `idle_o`, which
+                               // is also `0` and thus 'busy' when waiting for a FIFO input)
+  output logic idle_o
+);
+
+  logic        msg_feed_complete;
+  logic        shaf_rready;
+  logic        shaf_rvalid;
+
+  // control signals - shared for both modes
+  logic update_w_from_fifo, calculate_next_w;
+  logic init_hash, run_hash, one_chunk_done;
+  logic update_digest, clear_digest;
+  logic hash_done_next; // to meet the phase with digest value
+  logic hash_go;
+
+  // datapath signals - shared for both modes
+  logic [RndWidth512-1:0] round_d, round_q;
+  logic [3:0]             w_index_d, w_index_q;
+  digest_mode_e           digest_mode_flag_d, digest_mode_flag_q;
+  sha_word64_t            shaf_rdata;
+
+  // tie off unused input ports and signals slices
+  if (!MultimodeEn) begin : gen_tie_unused
+    logic [7:0] unused_digest_upper;
+    for (genvar i = 0; i < 8; i++) begin : gen_unused_digest_upper
+      assign unused_digest_upper[i] = ^digest_i[i][63:32];
+    end
+    logic unused_signals;
+    assign unused_signals = ^{shaf_rdata[63:32], unused_digest_upper};
+  end
+
+  // Most operations and control signals are identical no matter if we are starting or continuing
+  // to hash.
+  assign hash_go = hash_start_i | hash_continue_i;
+
+  assign digest_mode_flag_d = hash_go     ? digest_mode_i   :    // latch in configured mode
+                              hash_done_o ? SHA2_None       :    // clear
+                                            digest_mode_flag_q;  // keep
+
+  if (MultimodeEn) begin : gen_multimode
+    // datapath signal definitions for multi-mode
+    sha_word64_t [7:0]  hash_d, hash_q; // a,b,c,d,e,f,g,h
+    sha_word64_t [15:0] w_d, w_q;
+    sha_word64_t [7:0]  digest_d, digest_q;
+
+    // compute w
+    always_comb begin : compute_w_multimode
+      w_d = w_q;
+      if (wipe_secret_i) begin
+        w_d = {32{wipe_v_i}};
+      end else if (!sha_en_i || hash_go) begin
+        w_d = '0;
+      end else if (!run_hash && update_w_from_fifo) begin
+        // this logic runs at the first stage of SHA: hash not running yet,
+        // still filling in first 16 words
+        w_d = {shaf_rdata, w_q[15:1]};
+      end else if (calculate_next_w) begin // message scheduling/derivation for last 48/64 rounds
+        if (digest_mode_flag_q == SHA2_256) begin
+          // this computes the next w[16] and shifts out w[0] into compression below
+          w_d = {{32'b0, calc_w_256(w_q[0][31:0], w_q[1][31:0], w_q[9][31:0],
+                w_q[14][31:0])}, w_q[15:1]};
+        end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
+          w_d = {calc_w_512(w_q[0], w_q[1], w_q[9], w_q[14]), w_q[15:1]};
+        end
+      end else if (run_hash) begin
+        // just shift-out the words as they get consumed. There's no incoming data.
+        w_d = {ZeroWord, w_q[15:1]};
+      end
+    end : compute_w_multimode
+
+    // update w
+    always_ff @(posedge clk_i or negedge rst_ni) begin : update_w_multimode
+      if (!rst_ni)            w_q <= '0;
+      else if (MultimodeEn)   w_q <= w_d;
+    end : update_w_multimode
+
+    // compute hash
+    always_comb begin : compression_multimode
+      hash_d = hash_q;
+      if (wipe_secret_i) begin
+        hash_d = {16{wipe_v_i}};
+      end else if (init_hash) begin
+        hash_d = digest_q;
+      end else if (run_hash) begin
+        if (digest_mode_flag_q == SHA2_256) begin
+          hash_d = compress_multi_256(w_q[0][31:0],
+                   CubicRootPrime256[round_q[RndWidth256-1:0]], hash_q);
+        end else if ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384)) begin
+          hash_d = compress_512(w_q[0], CubicRootPrime512[round_q], hash_q);
+        end
+      end
+    end : compression_multimode
+
+    // update hash
+    always_ff @(posedge clk_i or negedge rst_ni) begin : update_hash_multimode
+      if (!rst_ni)  hash_q <= '0;
+      else          hash_q <= hash_d;
+    end : update_hash_multimode
+
+    // compute digest
+    always_comb begin : compute_digest_multimode
+      digest_d = digest_q;
+      if (wipe_secret_i) begin
+        digest_d = {16{wipe_v_i}};
+      end else if (hash_start_i) begin
+        for (int i = 0 ; i < 8 ; i++) begin
+          if (digest_mode_i == SHA2_256) begin
+            digest_d[i] = {32'b0, InitHash_256[i]};
+          end else if (digest_mode_i == SHA2_384) begin
+            digest_d[i] = InitHash_384[i];
+          end else if (digest_mode_i == SHA2_512) begin
+            digest_d[i] = InitHash_512[i];
+          end
+        end
+      end else if (clear_digest) begin
+        digest_d = '0;
+      end else if (!sha_en_i) begin
+        for (int i = 0; i < 8; i++) begin
+          digest_d[i] = digest_we_i[i] ? digest_i[i] : digest_q[i];
+        end
+      end else if (update_digest) begin
+        for (int i = 0 ; i < 8 ; i++) begin
+          digest_d[i] = digest_q[i] + hash_q[i];
+        end
+      end
+    end : compute_digest_multimode
+
+    // update digest
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni)  digest_q <= '0;
+      else          digest_q <= digest_d;
+    end
+
+    // assign digest to output
+    assign digest_o = digest_q;
+
+  end else begin : gen_256 // MultimodeEn = 0
+    // datapath signal definitions for SHA-2 256 only
+    sha_word32_t        shaf_rdata256;
+    sha_word32_t [7:0]  hash256_d, hash256_q; // a,b,c,d,e,f,g,h
+    sha_word32_t [15:0] w256_d, w256_q;
+    sha_word32_t [7:0]  digest256_d, digest256_q;
+
+    assign shaf_rdata256 = shaf_rdata[31:0];
+
+    always_comb begin : compute_w_256
+      // ~MultimodeEn
+      w256_d = w256_q;
+      if (wipe_secret_i) begin
+        w256_d = {16{wipe_v_i}};
+      end else if (!sha_en_i || hash_go) begin
+        w256_d = '0;
+      end else if (!run_hash && update_w_from_fifo) begin
+        // this logic runs at the first stage of SHA: hash not running yet,
+        // still filling in first 16 words
+        w256_d = {shaf_rdata256, w256_q[15:1]};
+      end else if (calculate_next_w) begin // message scheduling/derivation for last 48/64 rounds
+        w256_d = {calc_w_256(w256_q[0][31:0], w256_q[1][31:0], w256_q[9][31:0],
+                 w256_q[14][31:0]), w256_q[15:1]};
+      end else if (run_hash) begin
+        // just shift-out the words as they get consumed. There's no incoming data.
+        w256_d = {ZeroWord[31:0], w256_q[15:1]};
+      end
+    end : compute_w_256
+
+    // update w_256
+    always_ff @(posedge clk_i or negedge rst_ni) begin : update_w_256
+      if (!rst_ni)            w256_q <= '0;
+      else if (!MultimodeEn)  w256_q <= w256_d;
+    end : update_w_256
+
+    // compute hash_256
+    always_comb begin : compression_256
+      hash256_d = hash256_q;
+      if (wipe_secret_i) begin
+        hash256_d = {8{wipe_v_i}};
+      end else if (init_hash) begin
+        hash256_d = digest256_q;
+      end else if (run_hash) begin
+        hash256_d = compress_256(w256_q[0], CubicRootPrime256[round_q[RndWidth256-1:0]], hash256_q);
+      end
+    end : compression_256
+
+    // update hash_256
+    always_ff @(posedge clk_i or negedge rst_ni) begin : update_hash256
+      if (!rst_ni) hash256_q <= '0;
+      else         hash256_q <= hash256_d;
+    end : update_hash256
+
+    // compute digest_256
+    always_comb begin : compute_digest_256
+      digest256_d = digest256_q;
+      if (wipe_secret_i) begin
+        digest256_d = {8{wipe_v_i}};
+      end else if (hash_start_i) begin
+        for (int i = 0 ; i < 8 ; i++) begin
+            digest256_d[i] = InitHash_256[i];
+        end
+      end else if (clear_digest) begin
+        digest256_d = '0;
+      end else if (!sha_en_i) begin
+        for (int i = 0; i < 8; i++) begin
+          digest256_d[i] = digest_we_i[i] ? digest_i[i][31:0] : digest256_q[i];
+        end
+      end else if (update_digest) begin
+        for (int i = 0 ; i < 8 ; i++) begin
+          digest256_d[i] = digest256_q[i] + hash256_q[i];
+        end
+      end
+    end : compute_digest_256
+
+    // update digest_256
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni)  digest256_q <= '0;
+      else          digest256_q <= digest256_d;
+    end
+
+    // assign digest to output
+    for (genvar i = 0; i < 8; i++) begin  : gen_assign_digest_256
+      assign digest_o[i][31:0]  = digest256_q[i];
+      assign digest_o[i][63:32] = 32'b0;
+    end
+  end
+
+  // compute round counter (shared)
+  always_comb begin : round_counter
+    round_d = round_q;
+    if (!sha_en_i || hash_go) begin
+      round_d = '0;
+    end else if (run_hash) begin
+      if (((round_q[RndWidth256-1:0] == RndWidth256'(unsigned'(NumRound256-1))) &&
+         (digest_mode_flag_q == SHA2_256 || !MultimodeEn)) ||
+         ((round_q == RndWidth512'(unsigned'(NumRound512-1))) &&
+         ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))) begin
+        round_d = '0;
+      end else begin
+        round_d = round_q + 1;
+      end
+    end
+  end
+
+  // update round counter (shared)
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) round_q <= '0;
+    else         round_q <= round_d;
+  end
+
+  // compute w_index (shared)
+  assign w_index_d = (~sha_en_i || hash_go) ? '0            :  // clear
+                     update_w_from_fifo     ? w_index_q + 1 :  // increment
+                                              w_index_q;       // keep
+  // update w_index (shared)
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) w_index_q <= '0;
+    else         w_index_q <= w_index_d;
+  end
+
+  // ready for a word from the padding buffer in sha2_pad
+  assign shaf_rready = update_w_from_fifo;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) hash_done_o <= 1'b0;
+    else         hash_done_o <= hash_done_next;
+  end
+
+  typedef enum logic [1:0] {
+    FifoIdle,
+    FifoLoadFromFifo,
+    FifoWait
+  } fifoctl_state_e;
+
+  fifoctl_state_e fifo_st_q, fifo_st_d;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) fifo_st_q <= FifoIdle;
+    else         fifo_st_q <= fifo_st_d;
+  end
+
+  always_comb begin
+    fifo_st_d          = FifoIdle;
+    update_w_from_fifo = 1'b0;
+    hash_done_next     = 1'b0;
+
+    unique case (fifo_st_q)
+      FifoIdle: begin
+        if (hash_go) fifo_st_d = FifoLoadFromFifo;
+        else         fifo_st_d = FifoIdle;
+      end
+
+      FifoLoadFromFifo: begin
+        if (!shaf_rvalid) begin
+          // Wait until it is filled
+          fifo_st_d          = FifoLoadFromFifo;
+          update_w_from_fifo = 1'b0;
+        end else if (w_index_q == 4'd 15) begin
+          fifo_st_d = FifoWait;
+          // To increment w_index and it rolls over to 0
+          update_w_from_fifo = 1'b1;
+        end else begin
+          fifo_st_d          = FifoLoadFromFifo;
+          update_w_from_fifo = 1'b1;
+        end
+      end
+
+      FifoWait: begin
+        if (msg_feed_complete && one_chunk_done) begin
+          fifo_st_d      = FifoIdle;
+          // hashing the full message is done
+          hash_done_next = 1'b1;
+        end else if (one_chunk_done) begin
+          fifo_st_d      = FifoLoadFromFifo;
+        end else begin
+          fifo_st_d      = FifoWait;
+        end
+      end
+
+      default: begin
+        fifo_st_d = FifoIdle;
+      end
+    endcase
+
+    if (!sha_en_i)  begin
+      fifo_st_d          = FifoIdle;
+      update_w_from_fifo = 1'b0;
+    end else if (hash_go) begin
+      fifo_st_d          = FifoLoadFromFifo;
+    end
+  end
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) digest_mode_flag_q <= SHA2_None;
+    else         digest_mode_flag_q <= digest_mode_flag_d;
+  end
+
+  // SHA control (shared)
+  typedef enum logic [1:0] {
+    ShaIdle,
+    ShaCompress,
+    ShaUpdateDigest
+  } sha_st_t;
+
+  sha_st_t sha_st_q, sha_st_d;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) sha_st_q <= ShaIdle;
+    else         sha_st_q <= sha_st_d;
+  end
+
+  logic sha_en_q;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) sha_en_q <= 1'b0;
+    else         sha_en_q <= sha_en_i;
+  end
+
+  assign clear_digest = hash_start_i | (~sha_en_i & sha_en_q);
+
+  always_comb begin
+    update_digest    = 1'b0;
+    calculate_next_w = 1'b0;
+    init_hash        = 1'b0;
+    run_hash         = 1'b0;
+    sha_st_d         = sha_st_q;
+
+    unique case (sha_st_q)
+      ShaIdle: begin
+        if (fifo_st_q == FifoWait) begin
+          init_hash = 1'b1;
+          sha_st_d  = ShaCompress;
+        end else begin
+          sha_st_d  = ShaIdle;
+        end
+      end
+
+      ShaCompress: begin
+        run_hash = 1'b1;
+        if (((digest_mode_flag_q == SHA2_256 || ~MultimodeEn) && round_q < 48) ||
+           (((digest_mode_flag_q == SHA2_384) ||
+           (digest_mode_flag_q == SHA2_512)) && round_q < 64)) begin
+          calculate_next_w = 1'b1;
+        end else if (one_chunk_done) begin
+          sha_st_d = ShaUpdateDigest;
+        end else begin
+          sha_st_d = ShaCompress;
+        end
+      end
+
+      ShaUpdateDigest: begin
+        update_digest = 1'b1;
+        if (fifo_st_q == FifoWait) begin
+          init_hash = 1'b1;
+          sha_st_d  = ShaCompress;
+        end else begin
+          sha_st_d  = ShaIdle;
+        end
+      end
+
+      default: begin
+        sha_st_d = ShaIdle;
+      end
+    endcase
+
+    if (!sha_en_i || hash_go) sha_st_d  = ShaIdle;
+  end
+
+  // Determine whether a digest is being computed for a complete block: when `update_digest` is set,
+  // this module is not waiting for more data from the FIFO, and `message_length_i` is zero modulo a
+  // complete block (512 bit for SHA2_256 and 1024 bit for SHA2_384 and SHA2_512).
+  assign digest_on_blk_o = update_digest && (fifo_st_q == FifoIdle) && (
+      (digest_mode_flag_q == SHA2_256                 && message_length_i[8:0] == '0) ||
+      (digest_mode_flag_q inside {SHA2_384, SHA2_512} && message_length_i[9:0] == '0));
+
+  assign one_chunk_done = ((digest_mode_flag_q == SHA2_256 || ~MultimodeEn)
+                          && (round_q == 7'd63)) ? 1'b1 :
+                          (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
+                          && (round_q == 7'd79)) ? 1'b1 : 1'b0;
+
+  prim_sha2_pad #(
+      .MultimodeEn(MultimodeEn)
+    ) u_pad (
+    .clk_i,
+    .rst_ni,
+    .fifo_rvalid_i,
+    .fifo_rdata_i,
+    .fifo_rready_o,
+    .shaf_rvalid_o (shaf_rvalid), // is set when the 512-bit chunk is ready in the padding buffer
+    .shaf_rdata_o  (shaf_rdata),
+    .shaf_rready_i (shaf_rready), // indicates that w is ready for more words from padding buffer
+    .sha_en_i,
+    .hash_start_i,
+    .hash_stop_i,
+    .hash_continue_i,
+    .digest_mode_i,
+    .hash_process_i,
+    .hash_done_i (hash_done_o),
+    .message_length_i ({64'b0, message_length_i}), // 128-bit message length per NIST-FIPS-180-4
+    .msg_feed_complete_o (msg_feed_complete)
+  );
+
+  assign hash_running_o = init_hash | run_hash | update_digest;
+
+  // Idle
+  assign idle_o = (fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && !hash_go;
+endmodule : prim_sha2
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_32.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_32.sv
new file mode 100644
index 00000000..adac15b6
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_32.sv
@@ -0,0 +1,267 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// 32-bit input wrapper for the SHA-2 engine
+
+module prim_sha2_32 import prim_sha2_pkg::*;
+#(
+  parameter bit MultimodeEn = 0 // assert to enable multi-mode feature
+ ) (
+  input clk_i,
+  input rst_ni,
+
+  input              wipe_secret_i,
+  input sha_word32_t wipe_v_i,
+  // Control signals and message words input to the message FIFO
+  input               fifo_rvalid_i,      // indicates that there are data words/word parts
+                                          // ready to write into the SHA-2 padding buffer
+  input  sha_fifo32_t fifo_rdata_i,
+  output logic        fifo_rready_o,      // indicates that the wrapper word accumulation buffer is
+                                          // ready to receive words to feed into the SHA-2 engine
+  // Control signals
+  input                     sha_en_i, // if disabled, it clears internal content
+  input                     hash_start_i,
+  input                     hash_stop_i,
+  input                     hash_continue_i,
+  input digest_mode_e       digest_mode_i,
+  input                     hash_process_i,
+  output logic              hash_done_o,
+  input [63:0]              message_length_i,
+  input  sha_word64_t [7:0] digest_i,
+  input  logic [7:0]        digest_we_i,
+  output sha_word64_t [7:0] digest_o,         // use extended digest length
+  output logic              digest_on_blk_o,
+  output logic              hash_running_o,
+  output logic              idle_o
+);
+  // signal definitions shared for both 256-bit and multi-mode
+  sha_fifo64_t  full_word;
+  logic sha_ready, hash_go;
+
+  // Most operations and control signals are identical no matter if we are starting or re-starting
+  // to hash.
+  assign hash_go = hash_start_i | hash_continue_i;
+
+  // tie off unused ports/port slices
+  if (!MultimodeEn) begin : gen_tie_unused
+    logic unused_signals;
+    assign unused_signals = ^{digest_mode_i, hash_go};
+  end
+
+  // logic and prim_sha2 instantiation for MultimodeEn = 1
+  if (MultimodeEn) begin : gen_multimode_logic
+    // signal definitions for multi-mode
+    sha_fifo64_t  word_buffer_d, word_buffer_q;
+    logic [1:0]   word_part_count_d, word_part_count_q;
+    logic         sha_process, process_flag_d, process_flag_q;
+    logic         word_valid;
+    logic         word_part_inc, word_part_reset;
+    digest_mode_e digest_mode_flag_d, digest_mode_flag_q;
+
+    always_comb begin : multimode_combinational
+      word_part_inc    = 1'b0;
+      word_part_reset  = 1'b0;
+      full_word.mask   = 8'hFF; // to keep the padding buffer ready to receive
+      full_word.data   = 64'h0;
+      sha_process      = 1'b0;
+      word_valid       = 1'b0;
+      fifo_rready_o    = 1'b0;
+
+      // assign word_buffer
+      if (!sha_en_i || hash_go) word_buffer_d = 0;
+      else                      word_buffer_d = word_buffer_q;
+
+      if (sha_en_i && fifo_rvalid_i) begin // valid incoming word part and SHA engine is enabled
+        if (word_part_count_q == 2'b00) begin
+          if (digest_mode_flag_q != SHA2_256) begin
+            // accumulate most significant 32 bits of word and mask bits
+            word_buffer_d.data[63:32] = fifo_rdata_i.data;
+            word_buffer_d.mask[7:4]   = fifo_rdata_i.mask;
+            word_part_inc             = 1'b1;
+            fifo_rready_o             = 1'b1;
+          end else begin   // SHA2_256 so pad and push out the word
+            word_valid = 1'b1;
+            // store the word with most significant padding
+            word_buffer_d.data = {32'b0, fifo_rdata_i.data};
+            word_buffer_d.mask = {4'hF, fifo_rdata_i.mask}; // pad with all-1 byte mask
+            // pad with all-zero data and all-one byte masking and push word out already for 256
+            full_word.data =  {32'b0, fifo_rdata_i.data};
+            full_word.mask =  {4'hF, fifo_rdata_i.mask};
+            if (hash_process_i || process_flag_q) begin
+                sha_process = 1'b1;
+            end
+            if (sha_ready == 1'b1) begin
+              // if word has been absorbed into hash engine
+              fifo_rready_o = 1'b1; // word pushed out to SHA engine so word buffer ready
+            end else begin
+              fifo_rready_o = 1'b0;
+            end
+          end
+        end else if (word_part_count_q == 2'b01) begin
+          fifo_rready_o = 1'b1; // buffer still has room for another word
+          // accumulate least significant 32 bits and mask
+          word_buffer_d.data [31:0] = fifo_rdata_i.data;
+          word_buffer_d.mask [3:0]  = fifo_rdata_i.mask;
+
+          // now ready to pass full word through
+          word_valid              = 1'b1;
+          full_word.data [63:32]  = word_buffer_q.data[63:32];
+          full_word.mask [7:4]    = word_buffer_q.mask[7:4];
+          full_word.data [31:0]   = fifo_rdata_i.data;
+          full_word.mask  [3:0]   = fifo_rdata_i.mask;
+
+          if (hash_process_i || process_flag_q) begin
+              sha_process = 1'b1;
+          end
+          if (sha_ready == 1'b1) begin
+            // word has been consumed
+            fifo_rready_o       = 1'b1; // word pushed out to SHA engine so word buffer ready
+            word_part_reset   = 1'b1;
+            word_part_inc     = 1'b0;
+          end else begin
+            fifo_rready_o       = 1'b1;
+            word_part_inc     = 1'b1;
+          end
+        end else if (word_part_count_q == 2'b10) begin // word buffer is full and not loaded out yet
+          // fifo_rready_o is now deasserted: accumulated word is waiting to be pushed out
+          fifo_rready_o     = 1'b0;
+          word_valid        = 1'b1; // word buffer is ready to shift word out to SHA engine
+          full_word         = word_buffer_q;
+          if (hash_process_i || process_flag_q) begin
+              sha_process   = 1'b1;
+          end
+          if (sha_ready == 1'b1) begin // waiting on sha_ready to turn 1
+            // do not assert fifo_rready_o yet
+            word_part_reset = 1'b1;
+          end
+        end
+      end else if (sha_en_i) begin // hash engine still enabled but no new valid input
+        // provide the last latched input so long as hash is enabled
+        full_word = word_buffer_q;
+        if (word_part_count_q == 2'b00 && (hash_process_i || process_flag_q)) begin
+          sha_process = 1'b1; // wait on hash_process_i
+        end else if (word_part_count_q == 2'b01 && (hash_process_i || process_flag_q)) begin
+          // 384/512: msg ended: apply 32-bit word packing and push last word
+          full_word.data [31:0] = 32'b0;
+          full_word.mask [3:0]  = 4'h0;
+          word_valid            = 1'b1;
+          sha_process           = 1'b1;
+          if (sha_ready == 1'b1) begin // word has been consumed
+            word_part_reset = 1'b1; // which will also reset word_valid in the next cycle
+          end
+        end else if (word_part_count_q == 2'b01) begin // word feeding stalled but msg not ended
+          word_valid = 1'b0;
+        end else if (word_part_count_q == 2'b10 && (hash_process_i || process_flag_q)) begin
+          // 384/512: msg ended but last word still waiting to be fed in
+          word_valid  = 1'b1;
+          sha_process = 1'b1;
+          if (sha_ready == 1'b1) begin // word has been consumed
+            word_part_reset = 1'b1; // which will also reset word_valid in the next cycle
+          end
+        end else if (word_part_count_q == 2'b10) begin // word feeding stalled
+          word_valid = 1'b0;
+        end
+      end
+
+      // assign word_part_count_d
+      if ((word_part_reset || hash_go || !sha_en_i)) begin
+        word_part_count_d = '0;
+      end else if (word_part_inc) begin
+        word_part_count_d = word_part_count_q + 1'b1;
+      end else begin
+        word_part_count_d = word_part_count_q;
+      end
+
+      // assign digest_mode_flag_d
+      if (hash_go)          digest_mode_flag_d = digest_mode_i;      // latch in configured mode
+      else if (hash_done_o) digest_mode_flag_d = SHA2_None;          // clear
+      else                  digest_mode_flag_d = digest_mode_flag_q; // keep
+
+      // assign process_flag
+      if (!sha_en_i || hash_go) process_flag_d = 1'b0;
+      else if (hash_process_i)  process_flag_d = 1'b1;
+      else                      process_flag_d = process_flag_q;
+    end : multimode_combinational
+
+    prim_sha2 #(
+      .MultimodeEn(1)
+    ) u_prim_sha2_multimode (
+      .clk_i (clk_i),
+      .rst_ni (rst_ni),
+      .wipe_secret_i      (wipe_secret_i),
+      .wipe_v_i           (wipe_v_i),
+      .fifo_rvalid_i      (word_valid),
+      .fifo_rdata_i       (full_word),
+      .fifo_rready_o      (sha_ready),
+      .sha_en_i           (sha_en_i),
+      .hash_start_i       (hash_start_i),
+      .hash_stop_i        (hash_stop_i),
+      .hash_continue_i    (hash_continue_i),
+      .digest_mode_i      (digest_mode_i),
+      .hash_process_i     (sha_process),
+      .hash_done_o        (hash_done_o),
+      .message_length_i   (message_length_i),
+      .digest_i           (digest_i),
+      .digest_we_i        (digest_we_i),
+      .digest_o           (digest_o),
+      .digest_on_blk_o    (digest_on_blk_o),
+      .hash_running_o     (hash_running_o),
+      .idle_o             (idle_o)
+    );
+
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni)  word_part_count_q <= '0;
+      else          word_part_count_q <= word_part_count_d;
+    end
+
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni)  word_buffer_q <= 0;
+      else          word_buffer_q <= word_buffer_d;
+    end
+
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+     if (!rst_ni)          process_flag_q <= '0;
+      else  process_flag_q <= process_flag_d;
+    end
+
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) digest_mode_flag_q <= SHA2_None;
+      else         digest_mode_flag_q <= digest_mode_flag_d;
+    end
+  // logic and prim_sha2 instantiation for MultimodeEn = 0
+  end else begin : gen_sha256_logic  // MultimodeEn = 0
+    always_comb begin : sha256_combinational
+      full_word.data   = {32'b0, fifo_rdata_i.data};
+      full_word.mask   = {4'hF,  fifo_rdata_i.mask};
+      fifo_rready_o    = sha_ready;
+    end : sha256_combinational
+
+    prim_sha2 #(
+      .MultimodeEn(0)
+    ) u_prim_sha2_256 (
+      .clk_i (clk_i),
+      .rst_ni (rst_ni),
+      .wipe_secret_i      (wipe_secret_i),
+      .wipe_v_i           (wipe_v_i),
+      .fifo_rvalid_i      (fifo_rvalid_i), // feed input directly
+      .fifo_rdata_i       (full_word),
+      .fifo_rready_o      (sha_ready),
+      .sha_en_i           (sha_en_i),
+      .hash_start_i       (hash_start_i),
+      .hash_stop_i        (hash_stop_i),
+      .hash_continue_i    (hash_continue_i),
+      .digest_mode_i      (SHA2_None),      // unused input port tied to ground
+      .hash_process_i     (hash_process_i), // feed input port directly to SHA-2 engine
+      .hash_done_o        (hash_done_o),
+      .message_length_i   (message_length_i),
+      .digest_i           (digest_i),
+      .digest_we_i        (digest_we_i),
+      .digest_o           (digest_o),
+      .digest_on_blk_o    (digest_on_blk_o),
+      .hash_running_o     (hash_running_o),
+      .idle_o             (idle_o)
+    );
+  end
+
+endmodule : prim_sha2_32
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_pad.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_pad.sv
new file mode 100644
index 00000000..1dc010df
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_pad.sv
@@ -0,0 +1,380 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// SHA-256/Multi-Mode SHA-2 Padding logic
+
+`include "prim_assert.sv"
+
+module prim_sha2_pad import prim_sha2_pkg::*;
+#(
+  parameter bit MultimodeEn = 1
+ ) (
+  input clk_i,
+  input rst_ni,
+
+  // to actual FIFO
+  input                 fifo_rvalid_i,
+  input  sha_fifo64_t   fifo_rdata_i,
+  output logic          fifo_rready_o,
+  // from SHA2 compression engine
+  output logic          shaf_rvalid_o,
+  output sha_word64_t   shaf_rdata_o,
+  input                 shaf_rready_i,
+  input                 sha_en_i,
+  input                 hash_start_i,
+  input                 hash_stop_i,
+  input                 hash_continue_i,
+  input digest_mode_e   digest_mode_i,
+  input                 hash_process_i,
+  input                 hash_done_i,
+  input        [127:0]  message_length_i,   // # of bytes in bits (8 bits granularity)
+  output logic          msg_feed_complete_o // indicates all message is feeded
+);
+
+  logic [127:0] tx_count_d, tx_count;    // fin received data count.
+  logic         inc_txcount;
+  logic         fifo_partial;
+  logic         txcnt_eq_1a0;
+  logic         txcnt_eq_msg_len;
+  logic         hash_go;
+
+  logic         hash_stop_flag_d, hash_stop_flag_q;
+  logic         hash_process_flag_d, hash_process_flag_q;
+  digest_mode_e digest_mode_flag_d,  digest_mode_flag_q;
+
+  // Most operations and control signals are identical no matter if we are starting or continuing
+  // to hash.
+  assign hash_go = hash_start_i | hash_continue_i;
+
+  // tie off unused inport ports and signals
+  if (!MultimodeEn) begin : gen_tie_unused
+    logic unused_signals;
+    assign unused_signals = ^{message_length_i[127:64]};
+  end
+
+  assign fifo_partial = MultimodeEn ? ~&fifo_rdata_i.mask :
+                                      ~&fifo_rdata_i.mask[3:0];
+
+  // tx_count[8:0] == 'h1c0 --> should send LenHi
+  assign txcnt_eq_1a0 = (digest_mode_flag_q == SHA2_256   || ~MultimodeEn)               ?
+                                                                        (tx_count[8:0] == 9'h1a0)  :
+                        ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
+                                                                        (tx_count[9:0] == 10'h340) :
+                                                                        '0;
+
+  if (MultimodeEn) begin : gen_txcnt_comp_multimode
+    assign txcnt_eq_msg_len = (tx_count == message_length_i);
+  end else begin : gen_txcnt_comp_no_multimode
+    assign txcnt_eq_msg_len = (tx_count[63:0] == message_length_i[63:0]);
+  end
+
+  assign hash_stop_flag_d = (~sha_en_i || hash_go || hash_done_i) ? 1'b0 :
+                            hash_stop_i                           ? 1'b1 :
+                                                                    hash_stop_flag_q;
+
+  assign hash_process_flag_d = (~sha_en_i || hash_go || hash_done_i) ? 1'b0 :
+                               hash_process_i                        ? 1'b1 :
+                                                                       hash_process_flag_q;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      hash_stop_flag_q    <= 1'b0;
+      hash_process_flag_q <= 1'b0;
+    end else begin
+      hash_stop_flag_q    <= hash_stop_flag_d;
+      hash_process_flag_q <= hash_process_flag_d;
+    end
+  end
+
+  // data path: fout_wdata
+  typedef enum logic [2:0] {
+    FifoIn,         // fin_wdata, fin_wstrb
+    Pad80,          // {8'h80, 8'h00} , strb (calc based on len[4:3])
+    Pad00,          // 32'h0, full strb
+    LenHi,          // len[63:32], full strb
+    LenLo           // len[31:0], full strb
+  } sel_data_e;
+  sel_data_e sel_data;
+
+  always_comb begin
+    unique case (sel_data)
+      FifoIn: begin
+        shaf_rdata_o = fifo_rdata_i.data;
+      end
+
+      Pad80: begin
+        // {a[7:0], b[7:0], c[7:0], d[7:0]}
+        // msglen[4:3] == 00 |-> {'h80, 'h00, 'h00, 'h00}
+        // msglen[4:3] == 01 |-> {msg,  'h80, 'h00, 'h00}
+        // msglen[4:3] == 10 |-> {msg[15:0],  'h80, 'h00}
+        // msglen[4:3] == 11 |-> {msg[23:0],        'h80}
+        if ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) begin
+          unique case (message_length_i[4:3])
+            2'b 00:  shaf_rdata_o = 64'h 0000_0000_8000_0000;
+            2'b 01:  shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31:24], 24'h 8000_00};
+            2'b 10:  shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31:16], 16'h 8000};
+            2'b 11:  shaf_rdata_o = {32'h 0000_0000, fifo_rdata_i.data[31: 8],  8'h 80};
+            default: shaf_rdata_o = 64'h0;
+          endcase
+        end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
+          unique case (message_length_i[5:3])
+            3'b 000: shaf_rdata_o = 64'h 8000_0000_0000_0000;
+            3'b 001: shaf_rdata_o = {fifo_rdata_i.data[63:56], 56'h 8000_0000_0000_00};
+            3'b 010: shaf_rdata_o = {fifo_rdata_i.data[63:48], 48'h 8000_0000_0000};
+            3'b 011: shaf_rdata_o = {fifo_rdata_i.data[63:40], 40'h 8000_0000_00};
+            3'b 100: shaf_rdata_o = {fifo_rdata_i.data[63:32], 32'h 8000_0000};
+            3'b 101: shaf_rdata_o = {fifo_rdata_i.data[63:24], 24'h 8000_00};
+            3'b 110: shaf_rdata_o = {fifo_rdata_i.data[63:16], 16'h 8000};
+            3'b 111: shaf_rdata_o = {fifo_rdata_i.data[63:8],  8'h 80};
+            default: shaf_rdata_o = 64'h0;
+          endcase
+        end else
+            shaf_rdata_o = '0;
+      end
+
+      Pad00: begin
+        shaf_rdata_o = '0;
+      end
+
+      LenHi: begin
+        shaf_rdata_o = ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) ?
+                                                     {32'b0, message_length_i[63:32]}:
+                       ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
+                                                     message_length_i[127:64] : '0;
+      end
+
+      LenLo: begin
+        shaf_rdata_o = ((digest_mode_flag_q == SHA2_256) || ~MultimodeEn) ?
+                                                     {32'b0, message_length_i[31:0]}:
+                       ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
+                                                     message_length_i[63:0]: '0;
+      end
+
+      default: begin
+        shaf_rdata_o = '0;
+      end
+    endcase
+
+    if (!MultimodeEn) shaf_rdata_o [63:32] = 32'b0; // assign most sig 32 bits to constant 0
+  end
+
+  // Padded length
+  // $ceil(message_length_i + 8 + 64, 512) -> message_length_i [8:0] + 440 and ignore carry
+  //assign length_added = (message_length_i[8:0] + 9'h1b8) ;
+
+  // fifo control
+  // add 8'h 80 , N 8'h00, 64'h message_length_i
+
+  // Steps
+  // 1. `hash_start_i` from CPU (or DMA?)
+  // 2. calculate `padded_length` from `message_length_i`
+  // 3. Check if tx_count == message_length_i, then go to 5
+  // 4. Receiving FIFO input (hand over to fifo output)
+  // 5. Padding bit 1 (8'h80) followed by 8'h00 if needed
+  // 6. Padding with length (high -> low)
+
+  // State Machine
+  typedef enum logic [2:0] {
+    StIdle,        // fin_full to prevent unwanted FIFO write
+    StFifoReceive, // Check tx_count == message_length_i
+    StPad80,       // 8'h 80 + 8'h 00 X N
+    StPad00,
+    StLenHi,
+    StLenLo
+  } pad_st_e;
+
+  pad_st_e st_q, st_d;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) st_q <= StIdle;
+    else         st_q <= st_d;
+  end
+
+  // Next state
+  always_comb begin
+    shaf_rvalid_o = 1'b0;
+    inc_txcount   = 1'b0;
+    sel_data      = FifoIn;
+    fifo_rready_o = 1'b0;
+    st_d          = StIdle;
+
+    unique case (st_q)
+      StIdle: begin
+        sel_data      = FifoIn;
+        shaf_rvalid_o = 1'b0;
+        if (sha_en_i && hash_go) begin
+          inc_txcount = 1'b0;
+          st_d        = StFifoReceive;
+        end else begin
+          st_d        = StIdle;
+        end
+      end
+
+      StFifoReceive: begin
+        sel_data = FifoIn;
+        if (fifo_partial && fifo_rvalid_i) begin
+          // End of the message (last bit is not word-aligned) , assume hash_process_flag is set
+          shaf_rvalid_o = 1'b0; // Update entry at StPad80
+          inc_txcount   = 1'b0;
+          fifo_rready_o = 1'b0;
+          st_d = StPad80;
+        end else if (!hash_process_flag_q) begin
+          fifo_rready_o = shaf_rready_i;
+          shaf_rvalid_o = fifo_rvalid_i;
+          inc_txcount   = shaf_rready_i;
+          st_d = StFifoReceive;
+        end else if (txcnt_eq_msg_len) begin
+          // already received all msg and was waiting process flag
+          shaf_rvalid_o = 1'b0;
+          inc_txcount   = 1'b0;
+          fifo_rready_o = 1'b0;
+          st_d = StPad80;
+        end else begin
+          shaf_rvalid_o = fifo_rvalid_i;
+          fifo_rready_o = shaf_rready_i; // 0 always
+          inc_txcount   = shaf_rready_i; // 0 always
+          st_d = StFifoReceive;
+        end
+
+        if (txcnt_eq_msg_len && hash_stop_flag_q) begin
+          shaf_rvalid_o = 1'b0;
+          inc_txcount   = 1'b0;
+          fifo_rready_o = 1'b0;
+          st_d = StIdle;
+        end
+      end
+
+      StPad80: begin
+        sel_data      = Pad80;
+        shaf_rvalid_o = 1'b1;
+        fifo_rready_o = (digest_mode_flag_q == SHA2_256 || ~MultimodeEn) ?
+                        shaf_rready_i && |message_length_i[4:3] :
+                        ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ?
+                        shaf_rready_i && |message_length_i[5:3] : '0; // Only when partial
+
+        // exactly 192 bits left, do not need to pad00's
+        if (shaf_rready_i && txcnt_eq_1a0) begin
+          st_d        = StLenHi;
+          inc_txcount = 1'b1;
+        // it does not matter if value is < or > than 416 bits.  If it's the former, 00 pad until
+        // length field.  If >, then the next chunk will contain the length field with appropriate
+        // 0 padding.
+        end else if (shaf_rready_i && !txcnt_eq_1a0) begin
+          st_d        = StPad00;
+          inc_txcount = 1'b1;
+        end else begin
+          st_d        = StPad80;
+          inc_txcount = 1'b0;
+        end
+
+        // # Below part is temporal code to speed up the SHA by 16 clocks per chunk
+        // # (80 clk --> 64 clk)
+        // # leaving this as a reference but needs to verify it.
+        //if (shaf_rready_i && !txcnt_eq_1a0) begin
+        //  st_d = StPad00;
+        //
+        //  inc_txcount = 1'b1;
+        //  shaf_rvalid_o = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
+        //  fifo_rready = (msg_word_aligned) ? 1'b0 : 1'b1;
+        //end else if (!shaf_rready_i && !txcnt_eq_1a0) begin
+        //  st_d = StPad80;
+        //
+        //  inc_txcount = 1'b0;
+        //  shaf_rvalid_o = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
+        //
+        //end else if (shaf_rready_i && txcnt_eq_1a0) begin
+        //  st_d = StLenHi;
+        //  inc_txcount = 1'b1;
+        //end else begin
+        //  // !shaf_rready_i && txcnt_eq_1a0 , just wait until fifo_rready asserted
+        //  st_d = StPad80;
+        //  inc_txcount = 1'b0;
+        //end
+      end
+
+      StPad00: begin
+        sel_data      = Pad00;
+        shaf_rvalid_o = 1'b1;
+
+        if (shaf_rready_i) begin
+          inc_txcount = 1'b1;
+          if (txcnt_eq_1a0) st_d = StLenHi;
+          else              st_d = StPad00;
+        end else begin
+          st_d = StPad00;
+        end
+      end
+
+      StLenHi: begin
+        sel_data      = LenHi;
+        shaf_rvalid_o = 1'b1;
+
+        if (shaf_rready_i) begin
+          st_d = StLenLo;
+          inc_txcount = 1'b1;
+        end else begin
+          st_d = StLenHi;
+          inc_txcount = 1'b0;
+        end
+      end
+
+      StLenLo: begin
+        sel_data        = LenLo;
+        shaf_rvalid_o   = 1'b1;
+
+        if (shaf_rready_i) begin
+          st_d        = StIdle;
+          inc_txcount = 1'b1;
+        end else begin
+          st_d        = StLenLo;
+          inc_txcount = 1'b0;
+        end
+      end
+
+      default: begin
+        st_d = StIdle;
+      end
+    endcase
+
+    if (!sha_en_i)    st_d = StIdle;
+    else if (hash_go) st_d = StFifoReceive;
+  end
+
+  // tx_count
+  always_comb begin
+    tx_count_d = tx_count;
+
+    if (hash_start_i) begin
+      // When starting a fresh hash, initialize the data counter to zero.
+      tx_count_d = '0;
+    end else if (hash_continue_i) begin
+      // When continuing to hash, set the data counter to the current message length.
+      tx_count_d = message_length_i;
+    end else if (inc_txcount) begin
+      if ((digest_mode_flag_q == SHA2_256) || !MultimodeEn) begin
+        tx_count_d[127:5] = tx_count[127:5] + 1'b1;
+      end else if ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) begin
+        tx_count_d[127:6] = tx_count[127:6] + 1'b1;
+      end
+    end
+  end
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) tx_count <= '0;
+    else         tx_count <= tx_count_d;
+  end
+
+  assign digest_mode_flag_d = (hash_start_i || hash_continue_i) ? digest_mode_i  :    // set config
+                              hash_done_i                       ? SHA2_None      :    // clear
+                                                                  digest_mode_flag_q; // keep
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni)  digest_mode_flag_q <= SHA2_None;
+    else          digest_mode_flag_q <= digest_mode_flag_d;
+  end
+
+  // State machine is in Idle only when it meets tx_count == message length
+  assign msg_feed_complete_o = (hash_process_flag_q || hash_stop_flag_q) && (st_q == StIdle);
+
+endmodule
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_pkg.sv
new file mode 100644
index 00000000..1a30d278
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_sha2_pkg.sv
@@ -0,0 +1,250 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package prim_sha2_pkg;
+
+  localparam int NumRound256 = 64;   // SHA-224, SHA-256
+  localparam int NumRound512 = 80;   // SHA-512, SHA-384
+
+  typedef logic [31:0] sha_word32_t;
+  typedef logic [63:0] sha_word64_t;
+
+  localparam int WordByte32 = $bits(sha_word32_t)/8;
+  localparam int WordByte64 = $bits(sha_word64_t)/8;
+
+  typedef struct packed {
+    sha_word32_t           data;
+    logic [WordByte32-1:0] mask; // 4 mask bits: to mask off bytes if this is not word-aligned
+                                 // set to all-1 for word-aligned input
+  } sha_fifo32_t;
+
+  typedef struct packed {
+    sha_word64_t           data;
+    logic [WordByte64-1:0] mask; // 8 mask bits: to mask off bytes if this is not word-aligned
+                                 // set to all-1 for word-aligned input
+  } sha_fifo64_t;
+
+  // one-hot encoded
+  typedef enum logic [3:0] {
+    SHA2_256  = 4'b0001,
+    SHA2_384  = 4'b0010,
+    SHA2_512  = 4'b0100,
+    SHA2_None = 4'b1000
+  } digest_mode_e;
+
+  // one-hot encoded
+  typedef enum logic [5:0] {
+    Key_128  = 6'b00_0001,
+    Key_256  = 6'b00_0010,
+    Key_384  = 6'b00_0100,
+    Key_512  = 6'b00_1000,
+    Key_1024 = 6'b01_0000,
+    Key_None = 6'b10_0000
+  } key_length_e;
+
+  localparam sha_word32_t InitHash_256 [8]= '{
+    32'h 6a09_e667, 32'h bb67_ae85, 32'h 3c6e_f372, 32'h a54f_f53a,
+    32'h 510e_527f, 32'h 9b05_688c, 32'h 1f83_d9ab, 32'h 5be0_cd19
+  };
+
+  localparam sha_word64_t InitHash_384 [8]= '{
+    64'h cbbb_9d5d_c105_9ed8, 64'h 629a_292a_367c_d507, 64'h 9159_015a_3070_dd17,
+    64'h 152f_ecd8_f70e_5939, 64'h 6733_2667_ffc0_0b31, 64'h 8eb4_4a87_6858_1511,
+    64'h db0c_2e0d_64f9_8fa7, 64'h 47b5_481d_befa_4fa4
+  };
+
+  localparam sha_word64_t InitHash_512 [8]= '{
+    64'h 6a09_e667_f3bc_c908, 64'h bb67_ae85_84ca_a73b, 64'h 3c6e_f372_fe94_f82b,
+    64'h a54f_f53a_5f1d_36f1, 64'h 510e_527f_ade6_82d1, 64'h 9b05_688c_2b3e_6c1f,
+    64'h 1f83_d9ab_fb41_bd6b, 64'h 5be0_cd19_137e_2179
+  };
+
+  // SHA-256 constants
+  localparam sha_word32_t CubicRootPrime256 [NumRound256] = '{
+    32'h 428a_2f98, 32'h 7137_4491, 32'h b5c0_fbcf, 32'h e9b5_dba5,
+    32'h 3956_c25b, 32'h 59f1_11f1, 32'h 923f_82a4, 32'h ab1c_5ed5,
+    32'h d807_aa98, 32'h 1283_5b01, 32'h 2431_85be, 32'h 550c_7dc3,
+    32'h 72be_5d74, 32'h 80de_b1fe, 32'h 9bdc_06a7, 32'h c19b_f174,
+    32'h e49b_69c1, 32'h efbe_4786, 32'h 0fc1_9dc6, 32'h 240c_a1cc,
+    32'h 2de9_2c6f, 32'h 4a74_84aa, 32'h 5cb0_a9dc, 32'h 76f9_88da,
+    32'h 983e_5152, 32'h a831_c66d, 32'h b003_27c8, 32'h bf59_7fc7,
+    32'h c6e0_0bf3, 32'h d5a7_9147, 32'h 06ca_6351, 32'h 1429_2967,
+    32'h 27b7_0a85, 32'h 2e1b_2138, 32'h 4d2c_6dfc, 32'h 5338_0d13,
+    32'h 650a_7354, 32'h 766a_0abb, 32'h 81c2_c92e, 32'h 9272_2c85,
+    32'h a2bf_e8a1, 32'h a81a_664b, 32'h c24b_8b70, 32'h c76c_51a3,
+    32'h d192_e819, 32'h d699_0624, 32'h f40e_3585, 32'h 106a_a070,
+    32'h 19a4_c116, 32'h 1e37_6c08, 32'h 2748_774c, 32'h 34b0_bcb5,
+    32'h 391c_0cb3, 32'h 4ed8_aa4a, 32'h 5b9c_ca4f, 32'h 682e_6ff3,
+    32'h 748f_82ee, 32'h 78a5_636f, 32'h 84c8_7814, 32'h 8cc7_0208,
+    32'h 90be_fffa, 32'h a450_6ceb, 32'h bef9_a3f7, 32'h c671_78f2
+  };
+
+  // SHA-512/SHA-384 constants
+  localparam sha_word64_t CubicRootPrime512 [NumRound512] = '{
+    64'h 428a_2f98_d728_ae22, 64'h 7137_4491_23ef_65cd, 64'h b5c0_fbcf_ec4d_3b2f,
+    64'h e9b5_dba5_8189_dbbc, 64'h 3956_c25b_f348_b538, 64'h 59f1_11f1_b605_d019,
+    64'h 923f_82a4_af19_4f9b, 64'h ab1c_5ed5_da6d_8118, 64'h d807_aa98_a303_0242,
+    64'h 1283_5b01_4570_6fbe, 64'h 2431_85be_4ee4_b28c, 64'h 550c_7dc3_d5ff_b4e2,
+    64'h 72be_5d74_f27b_896f, 64'h 80de_b1fe_3b16_96b1, 64'h 9bdc_06a7_25c7_1235,
+    64'h c19b_f174_cf69_2694, 64'h e49b_69c1_9ef1_4ad2, 64'h efbe_4786_384f_25e3,
+    64'h 0fc1_9dc6_8b8c_d5b5, 64'h 240c_a1cc_77ac_9c65, 64'h 2de9_2c6f_592b_0275,
+    64'h 4a74_84aa_6ea6_e483, 64'h 5cb0_a9dc_bd41_fbd4, 64'h 76f9_88da_8311_53b5,
+    64'h 983e_5152_ee66_dfab, 64'h a831_c66d_2db4_3210, 64'h b003_27c8_98fb_213f,
+    64'h bf59_7fc7_beef_0ee4, 64'h c6e0_0bf3_3da8_8fc2, 64'h d5a7_9147_930a_a725,
+    64'h 06ca_6351_e003_826f, 64'h 1429_2967_0a0e_6e70, 64'h 27b7_0a85_46d2_2ffc,
+    64'h 2e1b_2138_5c26_c926, 64'h 4d2c_6dfc_5ac4_2aed, 64'h 5338_0d13_9d95_b3df,
+    64'h 650a_7354_8baf_63de, 64'h 766a_0abb_3c77_b2a8, 64'h 81c2_c92e_47ed_aee6,
+    64'h 9272_2c85_1482_353b, 64'h a2bf_e8a1_4cf1_0364, 64'h a81a_664b_bc42_3001,
+    64'h c24b_8b70_d0f8_9791, 64'h c76c_51a3_0654_be30, 64'h d192_e819_d6ef_5218,
+    64'h d699_0624_5565_a910, 64'h f40e_3585_5771_202a, 64'h 106a_a070_32bb_d1b8,
+    64'h 19a4_c116_b8d2_d0c8, 64'h 1e37_6c08_5141_ab53, 64'h 2748_774c_df8e_eb99,
+    64'h 34b0_bcb5_e19b_48a8, 64'h 391c_0cb3_c5c9_5a63, 64'h 4ed8_aa4a_e341_8acb,
+    64'h 5b9c_ca4f_7763_e373, 64'h 682e_6ff3_d6b2_b8a3, 64'h 748f_82ee_5def_b2fc,
+    64'h 78a5_636f_4317_2f60, 64'h 84c8_7814_a1f0_ab72, 64'h 8cc7_0208_1a64_39ec,
+    64'h 90be_fffa_2363_1e28, 64'h a450_6ceb_de82_bde9, 64'h bef9_a3f7_b2c6_7915,
+    64'h c671_78f2_e372_532b, 64'h ca27_3ece_ea26_619c, 64'h d186_b8c7_21c0_c207,
+    64'h eada_7dd6_cde0_eb1e, 64'h f57d_4f7f_ee6e_d178, 64'h 06f0_67aa_7217_6fba,
+    64'h 0a63_7dc5_a2c8_98a6, 64'h 113f_9804_bef9_0dae, 64'h 1b71_0b35_131c_471b,
+    64'h 28db_77f5_2304_7d84, 64'h 32ca_ab7b_40c7_2493, 64'h 3c9e_be0a_15c9_bebc,
+    64'h 431d_67c4_9c10_0d4c, 64'h 4cc5_d4be_cb3e_42b6, 64'h 597f_299c_fc65_7e2a,
+    64'h 5fcb_6fab_3ad6_faec, 64'h 6c44_198c_4a47_5817
+  };
+
+  function automatic sha_word32_t conv_endian32(input sha_word32_t v, input logic swap);
+    sha_word32_t conv_data = {<<8{v}};
+    conv_endian32 = (swap) ? conv_data : v;
+  endfunction : conv_endian32
+
+  function automatic sha_word64_t conv_endian64(input sha_word64_t v, input logic swap);
+    sha_word64_t conv_data = {<<8{v}};
+    conv_endian64 = (swap) ? conv_data : v;
+  endfunction : conv_endian64
+
+  function automatic sha_word32_t rotr32(input sha_word32_t v, input integer amt);
+    rotr32 = (v >> amt) | (v << (32-amt));
+  endfunction : rotr32
+
+  function automatic sha_word64_t rotr64(input sha_word64_t v, input integer amt);
+    rotr64 = (v >> amt) | (v << (64-amt));
+  endfunction : rotr64
+
+  function automatic sha_word32_t shiftr32(input sha_word32_t v, input integer amt);
+    shiftr32 = (v >> amt);
+  endfunction : shiftr32
+
+  function automatic sha_word64_t shiftr64(input sha_word64_t v, input integer amt);
+    shiftr64 = (v >> amt);
+  endfunction : shiftr64
+
+  // compression function for SHA-256 in multi-mode configuration
+  function automatic sha_word64_t [7:0] compress_multi_256(input sha_word32_t w,
+                                                           input sha_word32_t k,
+                                                           input sha_word64_t [7:0] h_i);
+    // as input: takes 64-bit word hash vector, 32-bit slice of w[0] and 32-bit constant
+    automatic sha_word32_t sigma_0, sigma_1, ch, maj, temp1, temp2;
+
+    sigma_1 = rotr32(h_i[4][31:0], 6) ^ rotr32(h_i[4][31:0], 11) ^ rotr32(h_i[4][31:0], 25);
+    ch = (h_i[4][31:0] & h_i[5][31:0]) ^ (~h_i[4][31:0] & h_i[6][31:0]);
+    temp1 = (h_i[7][31:0] + sigma_1 + ch + k + w);
+    sigma_0 = rotr32(h_i[0][31:0], 2) ^ rotr32(h_i[0][31:0], 13) ^ rotr32(h_i[0][31:0], 22);
+    maj = (h_i[0][31:0] & h_i[1][31:0]) ^ (h_i[0][31:0] & h_i[2][31:0]) ^
+          (h_i[1][31:0] & h_i[2][31:0]);
+    temp2 = (sigma_0 + maj);
+
+    // 32-bit zero padding to complete 64-bit words of hash vector for output
+    compress_multi_256[7] = {32'b0, h_i[6][31:0]};          // h = g
+    compress_multi_256[6] = {32'b0, h_i[5][31:0]};          // g = f
+    compress_multi_256[5] = {32'b0, h_i[4][31:0]};          // f = e
+    compress_multi_256[4] = {32'b0, h_i[3][31:0] + temp1};  // e = (d + temp1)
+    compress_multi_256[3] = {32'b0, h_i[2][31:0]};          // d = c
+    compress_multi_256[2] = {32'b0, h_i[1][31:0]};          // c = b
+    compress_multi_256[1] = {32'b0, h_i[0][31:0]};          // b = a
+    compress_multi_256[0] = {32'b0, (temp1 + temp2)};       // a = (temp1 + temp2)
+  endfunction : compress_multi_256
+
+  // compression function for SHA-256 in 256-only configuration
+  function automatic sha_word32_t [7:0] compress_256(input sha_word32_t w,
+                                                     input sha_word32_t k,
+                                                     input sha_word32_t [7:0] h_i);
+    automatic sha_word32_t sigma_0, sigma_1, ch, maj, temp1, temp2;
+
+    sigma_1 = rotr32(h_i[4], 6) ^ rotr32(h_i[4], 11) ^ rotr32(h_i[4], 25);
+    ch = (h_i[4] & h_i[5]) ^ (~h_i[4] & h_i[6]);
+    temp1 = (h_i[7] + sigma_1 + ch + k + w);
+    sigma_0 = rotr32(h_i[0], 2) ^ rotr32(h_i[0], 13) ^ rotr32(h_i[0], 22);
+    maj = (h_i[0] & h_i[1]) ^ (h_i[0] & h_i[2]) ^
+          (h_i[1] & h_i[2]);
+    temp2 = (sigma_0 + maj);
+
+    compress_256[7] = h_i[6];          // h = g
+    compress_256[6] = h_i[5];          // g = f
+    compress_256[5] = h_i[4];          // f = e
+    compress_256[4] = h_i[3] + temp1;  // e = (d + temp1)
+    compress_256[3] = h_i[2];          // d = c
+    compress_256[2] = h_i[1];          // c = b
+    compress_256[1] = h_i[0];          // b = a
+    compress_256[0] = temp1 + temp2;       // a = (temp1 + temp2)
+  endfunction : compress_256
+
+  // compression function for SHA-512/384
+  function automatic sha_word64_t [7:0] compress_512(input sha_word64_t w,
+                                                     input sha_word64_t k,
+                                                     input sha_word64_t [7:0] h_i);
+    automatic sha_word64_t sigma_0, sigma_1, ch, maj, temp1, temp2;
+
+    sigma_1 = rotr64(h_i[4], 14) ^ rotr64(h_i[4], 18) ^ rotr64(h_i[4], 41);
+    ch = (h_i[4] & h_i[5]) ^ (~h_i[4] & h_i[6]);
+    temp1 = (h_i[7] + sigma_1 + ch + k + w);
+    sigma_0 = rotr64(h_i[0], 28) ^ rotr64(h_i[0], 34) ^ rotr64(h_i[0], 39);
+    maj = (h_i[0] & h_i[1]) ^ (h_i[0] & h_i[2]) ^ (h_i[1] & h_i[2]);
+    temp2 = (sigma_0 + maj);
+
+    compress_512[7] = h_i[6];          // h = g
+    compress_512[6] = h_i[5];          // g = f
+    compress_512[5] = h_i[4];          // f = e
+    compress_512[4] = h_i[3] + temp1;  // e = (d + temp1)
+    compress_512[3] = h_i[2];          // d = c
+    compress_512[2] = h_i[1];          // c = b
+    compress_512[1] = h_i[0];          // b = a
+    compress_512[0] = (temp1 + temp2); // a = (temp1 + temp2)
+  endfunction : compress_512
+
+  function automatic sha_word32_t calc_w_256(input sha_word32_t w_0,
+                                             input sha_word32_t w_1,
+                                             input sha_word32_t w_9,
+                                             input sha_word32_t w_14);
+    automatic sha_word32_t sum0, sum1;
+    sum0 = rotr32(w_1,   7) ^ rotr32(w_1,  18) ^ shiftr32(w_1,   3);
+    sum1 = rotr32(w_14, 17) ^ rotr32(w_14, 19) ^ shiftr32(w_14, 10);
+    calc_w_256 = w_0 + sum0 + w_9 + sum1;
+  endfunction : calc_w_256
+
+  function automatic sha_word64_t calc_w_512(input sha_word64_t w_0,
+                                             input sha_word64_t w_1,
+                                             input sha_word64_t w_9,
+                                             input sha_word64_t w_14);
+    automatic sha_word64_t sum0, sum1;
+    sum0 = rotr64(w_1,   1) ^ rotr64(w_1,  8) ^ shiftr64(w_1,   7);
+    sum1 = rotr64(w_14, 19) ^ rotr64(w_14, 61) ^ shiftr64(w_14, 6);
+    calc_w_512 = w_0 + sum0 + w_9 + sum1;
+  endfunction : calc_w_512
+
+  typedef enum logic [31:0] {
+    NoError                    = 32'h 0000_0000,
+    // SwPushMsgWhenShaDisabled is not used in this version. The error code is
+    // guarded by the HW. HW drops the message write request if `sha_en` is
+    // off. eunchan@ left the error code to not corrupt the code sequence.
+    // Need to rename to DeprecatedSwPush...
+    //
+    // Issue #3022
+    SwPushMsgWhenShaDisabled   = 32'h 0000_0001,
+    SwHashStartWhenShaDisabled = 32'h 0000_0002,
+    SwUpdateSecretKeyInProcess = 32'h 0000_0003,
+    SwHashStartWhenActive      = 32'h 0000_0004,
+    SwPushMsgWhenDisallowed    = 32'h 0000_0005,
+    SwInvalidConfig            = 32'h 0000_0006
+  } err_code_e;
+
+endpackage : prim_sha2_pkg
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_slicer.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_slicer.sv
index 3c61669e..7b87ddd7 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_slicer.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_slicer.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -29,4 +29,3 @@ module prim_slicer #(
   `ASSERT_INIT(ValidWidth_A, InW <= OutW*(2**IndexW))
 
 endmodule
-
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_sparse_fsm_flop.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_sparse_fsm_flop.sv
index ca2599e3..1e0126ec 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_sparse_fsm_flop.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_sparse_fsm_flop.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_sram_arbiter.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_sram_arbiter.sv
index e168dac8..d166179d 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_sram_arbiter.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_sram_arbiter.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg.sv
index 0210928b..44f01b9c 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_arb.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_arb.sv
index ba8a2821..32269cc8 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_arb.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_arb.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_ext.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_ext.sv
index 30a40c60..efb662cc 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_ext.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_ext.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_pkg.sv
index 6e1da043..633b919e 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_shadow.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_shadow.sv
index e51e3b22..53206d0c 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_shadow.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_subreg_shadow.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -190,5 +190,7 @@ module prim_subreg_shadow
 
   // prim_subreg_shadow does not support multi-bit software access yet
   `ASSERT_NEVER(MubiIsNotYetSupported_A, Mubi)
+  logic unused_mubi;
+  assign unused_mubi = Mubi;
 
 endmodule
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_subst_perm.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_subst_perm.sv
index e75e3d6f..7dd6bd07 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_subst_perm.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_subst_perm.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_sum_tree.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_sum_tree.sv
index 2c8179ab..65cfc88f 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_sum_tree.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_sum_tree.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack.sv
index 518546fa..4dc029d4 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -20,8 +20,8 @@
 //   - 1 source + 2 destination + 1 destination + 2 source clock cycles until the handshake is
 //     performed in the SRC domain.
 // - Optionally, the module can also use a return-to-zero (RZ), four-phase handshake protocol.
-//   That one has lower throughput, but it is safe to partially reset either side, since the
-//   two FSMs cannot get out of sync due to persisting EVEN/ODD states. The handshake latencies
+//   That one has lower throughput, but it is safe to reset either domain in isolation, since the
+//   two FSMs cannot get out of sync due to persistent EVEN/ODD states. The handshake latencies
 //   are the same as for the NRZ protocol, but the throughput is half that of the NRZ protocol
 //   since the signals neet to return to zero first, causing two round-trips through the
 //   synchronizers instead of just one.
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack_data.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack_data.sv
index c4ef5e32..cab6a01e 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack_data.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_reqack_data.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_slow_fast.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_slow_fast.sv
index 8bffa1d5..b1e06cdb 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_slow_fast.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_sync_slow_fast.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_trivium.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_trivium.sv
index a6a18705..c648a31e 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_trivium.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_trivium.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -58,10 +58,12 @@
 
 module prim_trivium import prim_trivium_pkg::*;
 #(
-  parameter bit          BiviumVariant = 0,     // 0: Trivium, 1: Bivium
-  parameter int unsigned OutputWidth = 64,      // Number of output bits generated per update.
-  parameter bit          LockupProtection = 1,  // Upon entering an all zero state, 1: restore to
-                                                // the default seed, or 0: keep the all zero state.
+  parameter bit          BiviumVariant = 0,          // 0: Trivium, 1: Bivium
+  parameter int unsigned OutputWidth = 64,           // Number of output bits generated per update.
+  parameter bit          StrictLockupProtection = 1, // Upon entering an all zero state, 1: always
+                                                     // restore to the default seed, or 0: allow
+                                                     // to keep the all zero state if requested by
+                                                     // allow_lockup_i.
   parameter seed_type_e  SeedType = SeedTypeStateFull, // Reseeding inteface selection, see
                                                        // prim_trivium_pkg.sv for possible values.
   parameter int unsigned PartialSeedWidth = PartialSeedWidthDefault,
@@ -78,6 +80,9 @@ module prim_trivium import prim_trivium_pkg::*;
   input logic rst_ni,
 
   input  logic                        en_i,                 // Update the primitive.
+  input  logic                        allow_lockup_i,       // Allow locking up in all zero state.
+                                                            // Only taken into account if
+                                                            // LockupParameter = 0
   input  logic                        seed_en_i,            // Start reseeding (pulse or level).
   output logic                        seed_done_o,          // Reseeding is done (pulse).
   output logic                        seed_req_o,           // Seed REQ handshake signal
@@ -90,8 +95,9 @@ module prim_trivium import prim_trivium_pkg::*;
   output logic [OutputWidth-1:0] key_o, // Key stream output
   output logic                   err_o  // The primitive entered an all zero state and may have
                                         // locked up or entered the default state defined by
-                                        // RndCnstTriviumLfsrSeed depending on the LockupProtection
-                                        // parameter.
+                                        // RndCnstTriviumLfsrSeed depending on the
+                                        // StrictLockupProtection parameter and the allow_lockup_i
+                                        // signal.
 );
 
   localparam int unsigned LastStatePartFractional = StateWidth % PartialSeedWidth != 0 ? 1 : 0;
@@ -108,7 +114,7 @@ module prim_trivium import prim_trivium_pkg::*;
   logic update, update_init, wr_en_seed;
   logic [StateIdxWidth-1:0] state_idx_d, state_idx_q;
   logic last_state_part;
-  logic lockup;
+  logic lockup, restore;
 
   assign update = en_i | update_init;
   assign wr_en_seed = seed_req_o & seed_ack_i;
@@ -175,12 +181,14 @@ module prim_trivium import prim_trivium_pkg::*;
   // State register and updating //
   /////////////////////////////////
 
-  // The lockup protection is optional, as it may be required to put the primitive into an all zero
-  // state, e.g., to switch off masking countermeasures for analysis if the primitive is used for
-  // generating masks. However, the err_o bit always signals this condition to the outside.
-  assign state_d = (LockupProtection && lockup) ? StateSeed    :
-                                    wr_en_seed  ? state_seed   :
-                                    update      ? state_update : state_q;
+  // The lockup protection can optionally be disabled at run time. This may be required to put the
+  // primitive into an all zero state, e.g., to switch off masking countermeasures for analysis if
+  // the primitive is used for generating masks. However, the err_o bit always signals this
+  // condition to the outside.
+  assign restore = lockup & (StrictLockupProtection | ~allow_lockup_i);
+  assign state_d = restore     ? StateSeed    :
+                   wr_en_seed  ? state_seed   :
+                   update      ? state_update : state_q;
 
   always_ff @(posedge clk_i or negedge rst_ni) begin : state_reg
     if (!rst_ni) begin
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_trivium_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_trivium_pkg.sv
index 7437143a..6f769f0c 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_trivium_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_trivium_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -17,7 +17,7 @@ package prim_trivium_pkg;
   parameter int unsigned MinNfsrWidth = 84;
 
   // These LFSR parameters have been generated with
-  // $ ./util/design/gen-lfsr-seed.py --width 287 --seed 31468618 --prefix "Trivium"
+  // $ ./util/design/gen-lfsr-seed.py --width 288 --seed 31468618 --prefix "Trivium"
   parameter int TriviumLfsrWidth = 288;
   typedef logic [TriviumLfsrWidth-1:0] trivium_lfsr_seed_t;
   parameter trivium_lfsr_seed_t RndCnstTriviumLfsrSeedDefault = {
@@ -87,7 +87,7 @@ package prim_trivium_pkg;
 
   function automatic logic [TriviumStateWidth-1:0] trivium_seed_key_iv(
       logic [KeyIvWidth-1:0] key,
-      logic [KeyIvWidth-1:0] iv,
+      logic [KeyIvWidth-1:0] iv
     );
     logic [TriviumStateWidth-1:0] state;
     //     [287:285] [284:173] [172:93] [92:80] [79:0]
@@ -148,7 +148,7 @@ package prim_trivium_pkg;
 
   function automatic logic [BiviumStateWidth-1:0] bivium_seed_key_iv(
       logic [KeyIvWidth-1:0] key,
-      logic [KeyIvWidth-1:0] iv,
+      logic [KeyIvWidth-1:0] iv
     );
     logic [BiviumStateWidth-1:0] state;
     //   [176:173] [172:93] [92:80] [79:0]
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_util_get_scramble_params.svh b/vendor/lowrisc_ip/ip/prim/rtl/prim_util_get_scramble_params.svh
index e5e1860f..11245a86 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_util_get_scramble_params.svh
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_util_get_scramble_params.svh
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_util_memload.svh b/vendor/lowrisc_ip/ip/prim/rtl/prim_util_memload.svh
index 7f8c6da9..81600a8d 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_util_memload.svh
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_util_memload.svh
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_util_pkg.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_util_pkg.sv
index f5e3c92a..cb30121c 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_util_pkg.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_util_pkg.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/rtl/prim_xoshiro256pp.sv b/vendor/lowrisc_ip/ip/prim/rtl/prim_xoshiro256pp.sv
index cb6d9538..ed7cc1b5 100644
--- a/vendor/lowrisc_ip/ip/prim/rtl/prim_xoshiro256pp.sv
+++ b/vendor/lowrisc_ip/ip/prim/rtl/prim_xoshiro256pp.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/util/prim_crc32_table_gen.py b/vendor/lowrisc_ip/ip/prim/util/prim_crc32_table_gen.py
index a978d44a..955f469b 100755
--- a/vendor/lowrisc_ip/ip/prim/util/prim_crc32_table_gen.py
+++ b/vendor/lowrisc_ip/ip/prim/util/prim_crc32_table_gen.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/util/primgen.py b/vendor/lowrisc_ip/ip/prim/util/primgen.py
index 8ea68270..3e3ba412 100755
--- a/vendor/lowrisc_ip/ip/prim/util/primgen.py
+++ b/vendor/lowrisc_ip/ip/prim/util/primgen.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/util/primgen/abstract_prim.sv.tpl b/vendor/lowrisc_ip/ip/prim/util/primgen/abstract_prim.sv.tpl
index 4bbefd30..9b3432a3 100644
--- a/vendor/lowrisc_ip/ip/prim/util/primgen/abstract_prim.sv.tpl
+++ b/vendor/lowrisc_ip/ip/prim/util/primgen/abstract_prim.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -24,7 +24,7 @@ ${module_header_params}
   ${module_header_ports}
 );
 % if num_techlibs > 1:
-  parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+  localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
 % endif
 
 ${instances}
diff --git a/vendor/lowrisc_ip/ip/prim/util/primgen/prim_pkg.core.tpl b/vendor/lowrisc_ip/ip/prim/util/primgen/prim_pkg.core.tpl
index 47483155..b51a34c5 100644
--- a/vendor/lowrisc_ip/ip/prim/util/primgen/prim_pkg.core.tpl
+++ b/vendor/lowrisc_ip/ip/prim/util/primgen/prim_pkg.core.tpl
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:prim_abstract:prim_pkg:0.1"
diff --git a/vendor/lowrisc_ip/ip/prim/util/primgen/prim_pkg.sv.tpl b/vendor/lowrisc_ip/ip/prim/util/primgen/prim_pkg.sv.tpl
index 7974e5ad..def5d496 100644
--- a/vendor/lowrisc_ip/ip/prim/util/primgen/prim_pkg.sv.tpl
+++ b/vendor/lowrisc_ip/ip/prim/util/primgen/prim_pkg.sv.tpl
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim/util/vendor/google_verible_verilog_syntax_py.lock.hjson b/vendor/lowrisc_ip/ip/prim/util/vendor/google_verible_verilog_syntax_py.lock.hjson
index dc471725..e215964e 100644
--- a/vendor/lowrisc_ip/ip/prim/util/vendor/google_verible_verilog_syntax_py.lock.hjson
+++ b/vendor/lowrisc_ip/ip/prim/util/vendor/google_verible_verilog_syntax_py.lock.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim/util/vendor/google_verible_verilog_syntax_py.vendor.hjson b/vendor/lowrisc_ip/ip/prim/util/vendor/google_verible_verilog_syntax_py.vendor.hjson
index 0aeafcab..db0b403b 100644
--- a/vendor/lowrisc_ip/ip/prim/util/vendor/google_verible_verilog_syntax_py.vendor.hjson
+++ b/vendor/lowrisc_ip/ip/prim/util/vendor/google_verible_verilog_syntax_py.vendor.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/ip/prim_generic/BUILD b/vendor/lowrisc_ip/ip/prim_generic/BUILD
index c87fb863..f42854cd 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/BUILD
+++ b/vendor/lowrisc_ip/ip/prim_generic/BUILD
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_buf.vlt b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_buf.vlt
index 4408716d..c61d4c6e 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_buf.vlt
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_buf.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_buf.waiver b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_buf.waiver
index aad9fb15..89ab9b8f 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_buf.waiver
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_buf.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_div.waiver b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_div.waiver
index ada8d2b0..d748ccb3 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_div.waiver
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_div.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_gating.vlt b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_gating.vlt
index c38cafc5..2c6c5af8 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_gating.vlt
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_gating.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_gating.waiver b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_gating.waiver
index 469cd42b..1eb85611 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_gating.waiver
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_gating.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_mux2.vlt b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_mux2.vlt
index b7a50c7d..d62099a9 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_mux2.vlt
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_mux2.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_mux2.waiver b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_mux2.waiver
index d69c7f74..42d76a8d 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_mux2.waiver
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_mux2.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_flash.vlt b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_flash.vlt
index 544a7b79..b8340b20 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_flash.vlt
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_flash.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_flash.waiver b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_flash.waiver
index c9602d59..d733a256 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_flash.waiver
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_flash.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_otp.vlt b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_otp.vlt
index 9e469b8a..3aa735e9 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_otp.vlt
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_otp.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_otp.waiver b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_otp.waiver
index c85cee67..c2313ab0 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_otp.waiver
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_otp.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_pad_wrapper.vlt b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_pad_wrapper.vlt
index 544a7b79..b8340b20 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_pad_wrapper.vlt
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_pad_wrapper.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver
index f0445863..e9e9acd1 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1p.vlt b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1p.vlt
index 544a7b79..b8340b20 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1p.vlt
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1p.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1p.waiver b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1p.waiver
index cf4af6c3..997c72c7 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1p.waiver
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1p.waiver
@@ -1,10 +1,10 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_ram_[1,2]p
+# waiver file for prim_generic_ram_1p
 
-waive -rules ALWAYS_SPEC       -location {prim_generic_ram_*p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
+waive -rules ALWAYS_SPEC       -location {prim_generic_ram_1p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
       -comment "Vivado requires here an always instead of always_ff"
 waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_1p.sv.* is not read from in module 'prim_generic_ram_1p'} \
       -comment "Ascentlint blackboxes very deep RAMs to speed up runtime. This blackboxing causes above lint errors."
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1r1w.vlt b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1r1w.vlt
new file mode 100644
index 00000000..b0b7717a
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1r1w.vlt
@@ -0,0 +1,6 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+`verilator_config
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver
new file mode 100644
index 00000000..0a717f45
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1r1w.waiver
@@ -0,0 +1,12 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for prim_generic_ram_1r1w
+
+waive -rules ALWAYS_SPEC       -location {prim_generic_ram_1r1w.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
+      -comment "Vivado requires here an always instead of always_ff"
+waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_1r1w.sv.* is not read from in module 'prim_generic_ram_1r1w'} \
+      -comment "Ascentlint blackboxes very deep RAMs to speed up runtime. This blackboxing causes above lint errors."
+waive -rules IFDEF_CODE -location {prim_generic_ram_1r1w.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
+      -comment "Declaration of signal and assignment to it are in same `ifndef"
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_2p.vlt b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_2p.vlt
index 2654984e..c2c00c8c 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_2p.vlt
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_2p.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_2p.waiver b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_2p.waiver
index d6f7d5e7..69590e89 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_2p.waiver
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_2p.waiver
@@ -1,14 +1,14 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
-# waiver file for prim_generic_ram_[1,2]p
+# waiver file for prim_generic_ram_2p
 
 waive -rules MULTI_PROC_ASSIGN -location {prim_generic_ram_2p.sv} -regexp {Assignment to 'mem' from more than one block} \
       -comment "That is the nature of a dual-port memory: both write ports can access the same storage simultaneously"
-waive -rules ALWAYS_SPEC       -location {prim_generic_ram_*p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
+waive -rules ALWAYS_SPEC       -location {prim_generic_ram_2p.sv} -regexp {Edge triggered block may be more accurately modeled as always_ff} \
       -comment "Vivado requires here an always instead of always_ff"
-waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_1p.sv.* is not read from in module 'prim_generic_ram_1p'} \
+waive -rules HIER_NET_NOT_READ -regexp {Connected net '(addr|wdata)_i' at prim_generic_ram_2p.sv.* is not read from in module 'prim_generic_ram_2p'} \
       -comment "Ascentlint blackboxes very deep RAMs to speed up runtime. This blackboxing causes above lint errors."
 waive -rules IFDEF_CODE -location {prim_generic_ram_2p.sv} -regexp {Assignment to 'unused_cfg' contained within `ifndef} \
       -comment "Declaration of signal and assignment to it are in same `ifndef"
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_rom.vlt b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_rom.vlt
index 544a7b79..b8340b20 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_rom.vlt
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_rom.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_rom.waiver b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_rom.waiver
index 9d0ded35..351694ba 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_rom.waiver
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_rom.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -6,4 +6,3 @@
 
 waive -rules NOT_DRIVEN  -location {prim_generic_rom.sv} -regexp {Signal 'mem' has no driver in module 'prim_generic_rom'} \
       -comment "since this is a ROM, the signal mem has no driver, but it is populated using an initialization file"
-
diff --git a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver
index dfc86269..3ae5442b 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver
+++ b/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_usb_diff_rx.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_and2.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_and2.core
index 2dbc79c4..35bf0a05 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_and2.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_and2.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,15 +15,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_buf.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_buf.core
index 142bc8db..1e938000 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_buf.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_buf.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,15 +15,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_buf.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_buf.core
index 04f6ed9f..a0527957 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_buf.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_buf.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_div.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_div.core
index c5092645..80665407 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_div.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_div.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_gating.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_gating.core
index d083e867..c1e87818 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_gating.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_gating.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_inv.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_inv.core
index 19920df8..4f48b07a 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_inv.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_inv.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -18,17 +18,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      # - lint/prim_generic_clock_inv.vlt
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      # - lint/prim_generic_clock_inv.waiver
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_mux2.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_mux2.core
index 6e8ed693..f4f343d4 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_mux2.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_mux2.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flash.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flash.core
index 29afdf8f..736caad5 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flash.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flash.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -12,7 +12,7 @@ filesets:
       - lowrisc:prim:ram_1p
       - "fileset_partner  ? (partner:systems:ast_pkg)"
       - "!fileset_partner ? (lowrisc:systems:ast_pkg)"
-      - lowrisc:ip:flash_ctrl_pkg
+      - lowrisc:ip_interfaces:flash_ctrl_pkg
       - lowrisc:ip:flash_ctrl_prim_reg_top
     files:
       - rtl/prim_generic_flash_bank.sv
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop.core
index 6209a7bc..c66701bc 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,15 +15,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop_en.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop_en.core
index 275e2a8d..8e39916e 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop_en.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop_en.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -17,15 +17,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_otp.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_otp.core
index 7c548275..db270f07 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_otp.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_otp.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -11,7 +11,8 @@ filesets:
       - lowrisc:prim:all
       - lowrisc:prim:util
       - lowrisc:prim:ram_1p_adv
-      - lowrisc:systems:ast_pkg
+      - "fileset_partner  ? (partner:systems:ast_pkg)"
+      - "!fileset_partner ? (lowrisc:systems:ast_pkg)"
       - lowrisc:prim:otp_pkg
       - lowrisc:ip:otp_ctrl_prim_reg_top
     files:
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_pad_attr.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_pad_attr.core
index 1cf1eaf2..0629996c 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_pad_attr.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_pad_attr.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -18,17 +18,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      #- lint/prim_generic_pad_attr.vlt
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      #- lint/prim_generic_pad_attr.waiver
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_pad_wrapper.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_pad_wrapper.core
index 3a374820..ab7f0a1c 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_pad_wrapper.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_pad_wrapper.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_1p.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_1p.core
index 1be782c9..ea3848b1 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_1p.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_1p.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_1r1w.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_1r1w.core
new file mode 100644
index 00000000..2cc65296
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_1r1w.core
@@ -0,0 +1,45 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim_generic:ram_1r1w"
+description: "prim"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:assert
+      - lowrisc:prim:ram_2p_pkg
+      - lowrisc:prim:util_memload
+    files:
+      - rtl/prim_generic_ram_1r1w.sv
+    file_type: systemVerilogSource
+
+  files_verilator_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+      - lint/prim_generic_ram_1r1w.vlt
+    file_type: vlt
+
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+      - lint/prim_generic_ram_1r1w.waiver
+    file_type: waiver
+
+  files_veriblelint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+targets:
+  default:
+    filesets:
+      - tool_verilator   ? (files_verilator_waiver)
+      - tool_ascentlint  ? (files_ascentlint_waiver)
+      - tool_veriblelint ? (files_veriblelint_waiver)
+      - files_rtl
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_2p.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_2p.core
index 065962b5..13c41145 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_2p.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_2p.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_rom.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_rom.core
index a8821e2e..5bf3b6ce 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_rom.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_rom.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_usb_diff_rx.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_usb_diff_rx.core
index a633b676..d1c34a6a 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_usb_diff_rx.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_usb_diff_rx.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,9 +15,6 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      #- lint/prim_generic_usb_diff_rx.vlt
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_xnor2.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_xnor2.core
index f7a9b259..24e3a125 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_xnor2.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_xnor2.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,15 +15,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_xor2.core b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_xor2.core
index 3fa56ce3..e3cf88c2 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/prim_generic_xor2.core
+++ b/vendor/lowrisc_ip/ip/prim_generic/prim_generic_xor2.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,15 +15,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_and2.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_and2.sv
index 0b62bef2..df1b65fa 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_and2.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_and2.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv
index 1b2fbffa..ede99f1d 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_buf.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_buf.sv
index a0e841ad..d660aab6 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_buf.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_buf.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_div.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_div.sv
index da326623..798aa35e 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_div.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_div.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -27,6 +27,7 @@ module prim_generic_clock_div #(
   assign step_down_req = test_en_i ? '0 : step_down_req_i;
 
   logic clk_int;
+  logic clk_muxed;
 
   if (Divisor == 2) begin : gen_div2
     logic q_p, q_n;
@@ -86,7 +87,7 @@ module prim_generic_clock_div #(
         clk_int <= ResetValue;
       end else if (cnt >= limit) begin
         cnt <= '0;
-        clk_int <= ~clk_o;
+        clk_int <= ~clk_muxed;
       end else begin
         cnt <= cnt + 1'b1;
       end
@@ -102,7 +103,6 @@ module prim_generic_clock_div #(
   end
 
   // anchor points for constraints
-  logic clk_muxed;
   prim_clock_mux2 #(
     .NoFpgaBufG(1'b1)
   ) u_clk_mux (
@@ -112,6 +112,7 @@ module prim_generic_clock_div #(
     .clk_o(clk_muxed)
   );
 
+  // Hookup point for OCC on divided clock.
   prim_clock_buf u_clk_div_buf (
     .clk_i(clk_muxed),
     .clk_o
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
index d4b64568..6f80f6e8 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_inv.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_inv.sv
index 31a439cf..2f56d328 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_inv.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_inv.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_mux2.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_mux2.sv
index 143597da..85418e0d 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_mux2.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_mux2.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flash.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flash.sv
index e67e25a8..2349dd8f 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flash.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flash.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -41,13 +41,9 @@ module prim_generic_flash #(
   output tlul_pkg::tl_d2h_t tl_o,
   // Observability
   input ast_pkg::ast_obs_ctrl_t obs_ctrl_i,
-  output logic [7:0] fla_obs_o,
-  input  devmode_i
+  output logic [7:0] fla_obs_o
 );
 
-  logic unused_devmode;
-  assign unused_devmode = devmode_i;
-
   // convert this into a tlul write later
   logic init;
   assign init = 1'b1;
@@ -126,8 +122,7 @@ module prim_generic_flash #(
     .tl_o      (tl_o),
     .reg2hw    (reg2hw),
     .hw2reg    (hw2reg),
-    .intg_err_o(intg_err),
-    .devmode_i (1'b1)
+    .intg_err_o(intg_err)
   );
 
   logic unused_reg_sig;
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flash_bank.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flash_bank.sv
index b6e0d8b0..566a2e8f 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flash_bank.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flash_bank.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv
index 67b6e890..426b44e0 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop_en.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop_en.sv
index 3c367b73..94ca795f 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop_en.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop_en.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_otp.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_otp.sv
index 298a6d38..5fe826d6 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_otp.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_otp.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
@@ -52,8 +52,10 @@ module prim_generic_otp
   // Ready valid handshake for read/write command
   output logic                   ready_o,
   input                          valid_i,
-  input [SizeWidth-1:0]          size_i, // #(Native words)-1, e.g. size == 0 for 1 native word.
-  input  cmd_e                   cmd_i,  // 00: read command, 01: write command, 11: init command
+  // #(Native words)-1, e.g. size == 0 for 1 native word.
+  input [SizeWidth-1:0]          size_i,
+  // See prim_otp_pkg for the command encoding.
+  input  cmd_e                   cmd_i,
   input [AddrWidth-1:0]          addr_i,
   input [IfWidth-1:0]            wdata_i,
   // Response channel
@@ -106,8 +108,7 @@ module prim_generic_otp
     .tl_o      (test_tl_o ),
     .reg2hw    (reg2hw    ),
     .hw2reg    (hw2reg    ),
-    .intg_err_o(intg_err  ),
-    .devmode_i (1'b1      )
+    .intg_err_o(intg_err  )
   );
 
   logic unused_reg_sig;
@@ -157,13 +158,14 @@ module prim_generic_otp
   state_e state_d, state_q;
   err_e err_d, err_q;
   logic valid_d, valid_q;
+  logic integrity_en_d, integrity_en_q;
   logic req, wren, rvalid;
   logic [1:0] rerror;
   logic [AddrWidth-1:0] addr_q;
   logic [SizeWidth-1:0] size_q;
   logic [SizeWidth-1:0] cnt_d, cnt_q;
   logic cnt_clr, cnt_en;
-  logic read_ecc_on;
+  logic read_ecc_on, write_ecc_on;
   logic wdata_inconsistent;
 
 
@@ -184,7 +186,9 @@ module prim_generic_otp
     cnt_clr = 1'b0;
     cnt_en  = 1'b0;
     read_ecc_on = 1'b1;
+    write_ecc_on = 1'b1;
     fsm_err = 1'b0;
+    integrity_en_d = integrity_en_q;
 
     unique case (state_q)
       // Wait here until we receive an initialization command.
@@ -211,8 +215,22 @@ module prim_generic_otp
           cnt_clr = 1'b1;
           err_d = NoError;
           unique case (cmd_i)
-            Read:  state_d = ReadSt;
-            Write: state_d = WriteCheckSt;
+            Read:  begin
+              state_d = ReadSt;
+              integrity_en_d = 1'b1;
+            end
+            Write: begin
+              state_d = WriteCheckSt;
+              integrity_en_d = 1'b1;
+            end
+            ReadRaw:  begin
+              state_d = ReadSt;
+              integrity_en_d = 1'b0;
+            end
+            WriteRaw: begin
+              state_d = WriteCheckSt;
+              integrity_en_d = 1'b0;
+            end
             default: ;
           endcase // cmd_i
         end
@@ -221,13 +239,17 @@ module prim_generic_otp
       ReadSt: begin
         state_d = ReadWaitSt;
         req     = 1'b1;
+        // Suppress ECC correction if needed.
+        read_ecc_on = integrity_en_q;
       end
       // Wait for response from macro.
       ReadWaitSt: begin
+        // Suppress ECC correction if needed.
+        read_ecc_on = integrity_en_q;
         if (rvalid) begin
           cnt_en = 1'b1;
           // Uncorrectable error, bail out.
-          if (rerror[1]) begin
+          if (rerror[1] && integrity_en_q) begin
             state_d = IdleSt;
             valid_d = 1'b1;
             err_d = MacroEccUncorrError;
@@ -239,7 +261,7 @@ module prim_generic_otp
               state_d = ReadSt;
             end
             // Correctable error, carry on but signal back.
-            if (rerror[0]) begin
+            if (rerror[0] && integrity_en_q) begin
               err_d = MacroEccCorrError;
             end
           end
@@ -250,12 +272,14 @@ module prim_generic_otp
       WriteCheckSt: begin
         state_d = WriteWaitSt;
         req     = 1'b1;
-        // Register raw memory contents without correction
+        // Register raw memory contents without correction so that we can
+        // perform the read-modify-write correctly.
         read_ecc_on = 1'b0;
       end
       // Wait for readout to complete first.
       WriteWaitSt: begin
-        // Register raw memory contents without correction
+        // Register raw memory contents without correction so that we can
+        // perform the read-modify-write correctly.
         read_ecc_on = 1'b0;
         if (rvalid) begin
           cnt_en = 1'b1;
@@ -274,6 +298,9 @@ module prim_generic_otp
         req = 1'b1;
         wren = 1'b1;
         cnt_en = 1'b1;
+        // Suppress ECC calculation if needed.
+        write_ecc_on = integrity_en_q;
+
         if (wdata_inconsistent) begin
           err_d = MacroWriteBlankError;
         end
@@ -323,7 +350,9 @@ module prim_generic_otp
                                  : rdata_ecc;
 
   // Read-modify-write (OTP can only set bits to 1, but not clear to 0).
-  assign wdata_rmw = wdata_ecc | rdata_q[cnt_q];
+  assign wdata_rmw = (write_ecc_on) ? wdata_ecc | rdata_q[cnt_q]
+                                    : {{EccWidth{1'b0}}, wdata_q[cnt_q]} | rdata_q[cnt_q];
+
   // This indicates if the write data is inconsistent (i.e., if the operation attempts to
   // clear an already programmed bit to zero).
   assign wdata_inconsistent = (rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q];
@@ -353,7 +382,8 @@ module prim_generic_otp
     .rdata_o  ( rdata_ecc              ),
     .rvalid_o ( rvalid                 ),
     .rerror_o (                        ),
-    .cfg_i    ( '0                     )
+    .cfg_i    ( '0                     ),
+    .alert_o  (                        )
   );
 
   // Currently it is assumed that no wrap arounds can occur.
@@ -374,10 +404,12 @@ module prim_generic_otp
       rdata_q <= '0;
       cnt_q   <= '0;
       size_q  <= '0;
+      integrity_en_q <= 1'b0;
     end else begin
       valid_q <= valid_d;
       err_q   <= err_d;
       cnt_q   <= cnt_d;
+      integrity_en_q <= integrity_en_d;
       if (ready_o && valid_i) begin
         addr_q  <= addr_i;
         wdata_q <= wdata_i;
@@ -395,7 +427,8 @@ module prim_generic_otp
 
   // Check that the otp_ctrl FSMs only issue legal commands to the wrapper.
   `ASSERT(CheckCommands0_A, state_q == ResetSt && valid_i && ready_o |-> cmd_i == Init)
-  `ASSERT(CheckCommands1_A, state_q != ResetSt && valid_i && ready_o |-> cmd_i inside {Read, Write})
+  `ASSERT(CheckCommands1_A, state_q != ResetSt && valid_i && ready_o
+      |-> cmd_i inside {Read, ReadRaw, Write, WriteRaw})
 
 
 endmodule : prim_generic_otp
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_attr.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_attr.sv
index 1dcfae51..80e93f82 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_attr.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_attr.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -19,6 +19,7 @@ module prim_generic_pad_attr
   //
   // - inversion
   // - pullup / pulldown
+  // - input disable
   //
   // Bidirectional:
   //
@@ -26,6 +27,7 @@ module prim_generic_pad_attr
   // - virtual open drain
   // - pullup / pulldown
   // - 1 driving strength bit
+  // - input disable
   //
   // Note that the last three attributes are not supported on Verilator.
   if (PadType == InputStd) begin : gen_input_only_warl
@@ -34,6 +36,7 @@ module prim_generic_pad_attr
       attr_warl_o.invert = 1'b1;
       attr_warl_o.pull_en = 1'b1;
       attr_warl_o.pull_select = 1'b1;
+      attr_warl_o.input_disable = 1'b1;
     end
   end else if (PadType == BidirStd ||
                PadType == BidirTol ||
@@ -50,12 +53,14 @@ module prim_generic_pad_attr
       // Only one driving strength bit is supported.
       attr_warl_o.drive_strength[0] = 1'b1;
   `endif
+      attr_warl_o.input_disable = 1'b1;
     end
   end else if (PadType == AnalogIn0) begin : gen_analog0_warl
     // The analog pad type is basically just a feedthrough,
-    // and does hence not support any of the attributes.
+    // and hence only supports input disable.
     always_comb begin : p_attr
       attr_warl_o = '0;
+      attr_warl_o.input_disable = 1'b1;
     end
   end else begin : gen_invalid_config
     // this should throw link warnings in elaboration
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv
index e7da2760..7ff382c3 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -46,6 +46,10 @@ module prim_generic_pad_wrapper
   //VCS coverage on
   // pragma coverage on
 
+  // Input enable (active-high)
+  logic ie;
+  assign ie = ie_i & ~attr_i.input_disable;
+
   if (PadType == InputStd) begin : gen_input_only
     //VCS coverage off
     // pragma coverage off
@@ -57,7 +61,7 @@ module prim_generic_pad_wrapper
     //VCS coverage on
     // pragma coverage on
 
-    assign in_raw_o = (ie_i) ? inout_io  : 1'bz;
+    assign in_raw_o = ie ? inout_io : 1'bz;
     // input inversion
     assign in_o = attr_i.invert ^ in_raw_o;
 
@@ -71,7 +75,7 @@ module prim_generic_pad_wrapper
                PadType == BidirOd ||
                PadType == BidirStd) begin : gen_bidir
 
-    assign in_raw_o = (ie_i) ? inout_io  : 1'bz;
+    assign in_raw_o = ie ? inout_io : 1'bz;
     // input inversion
     assign in_o = attr_i.invert ^ in_raw_o;
 
@@ -95,13 +99,20 @@ module prim_generic_pad_wrapper
     //VCS coverage off
     // pragma coverage off
     logic unused_ana_sigs;
-    assign unused_ana_sigs = ^{attr_i, out_i, oe_i, ie_i};
+    assign unused_ana_sigs = ^{attr_i.invert,
+                               attr_i.virt_od_en,
+                               attr_i.drive_strength[0],
+                               attr_i.pull_en,
+                               attr_i.pull_select,
+                               out_i,
+                               oe_i,
+                               ie_i};
     //VCS coverage on
     // pragma coverage on
 
     assign inout_io = 1'bz; // explicitly make this tristate to avoid lint errors.
-    assign in_o = inout_io;
-    assign in_raw_o = inout_io;
+    assign in_raw_o = ie ? inout_io : 1'bz;
+    assign in_o = in_raw_o;
 
   end else begin : gen_invalid_config
     // this should throw link warnings in elaboration
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1p.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1p.sv
index 8d84e636..d2e835ac 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1p.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1p.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv
new file mode 100644
index 00000000..aafecf8a
--- /dev/null
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1r1w.sv
@@ -0,0 +1,84 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Synchronous two-port SRAM register model
+//   This module is for simulation and small size SRAM.
+//   Implementing ECC should be done inside wrapper not this model.
+`include "prim_assert.sv"
+module prim_generic_ram_1r1w import prim_ram_2p_pkg::*; #(
+  parameter  int Width           = 32, // bit
+  parameter  int Depth           = 128,
+  parameter  int DataBitsPerMask = 1, // Number of data bits per bit of write mask
+  parameter      MemInitFile     = "", // VMEM file to initialize the memory with
+
+  localparam int Aw              = $clog2(Depth)  // derived parameter
+) (
+  input clk_a_i,
+  input clk_b_i,
+
+  // Port A can only write
+  input                    a_req_i,
+  input        [Aw-1:0]    a_addr_i,
+  input        [Width-1:0] a_wdata_i,
+  input  logic [Width-1:0] a_wmask_i,
+
+  // Port B can only read
+  input                    b_req_i,
+  input        [Aw-1:0]    b_addr_i,
+  output logic [Width-1:0] b_rdata_o,
+
+  input ram_2p_cfg_t       cfg_i
+);
+
+// For certain synthesis experiments we compile the design with generic models to get an unmapped
+// netlist (GTECH). In these synthesis experiments, we typically black-box the memory models since
+// these are going to be simulated using plain RTL models in netlist simulations. This can be done
+// by analyzing and elaborating the design, and then removing the memory submodules before writing
+// out the verilog netlist. However, memory arrays can take a long time to elaborate, and in case
+// of two port rams they can even trigger elab errors due to multiple processes writing to the
+// same memory variable concurrently. To this end, we exclude the entire logic in this module in
+// these runs with the following macro.
+`ifndef SYNTHESIS_MEMORY_BLACK_BOXING
+
+  logic unused_cfg;
+  assign unused_cfg = ^cfg_i;
+
+  // Width of internal write mask. Note *_wmask_i input into the module is always assumed
+  // to be the full bit mask.
+  localparam int MaskWidth = Width / DataBitsPerMask;
+
+  logic [Width-1:0]     mem [Depth];
+  logic [MaskWidth-1:0] a_wmask;
+  for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
+    assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
+
+    // Ensure that all mask bits within a group have the same value for a write
+    `ASSERT(MaskCheckPortA_A, a_req_i |->
+        a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
+        clk_a_i, '0)
+  end
+
+  // Xilinx FPGA specific Two-port RAM coding style
+  // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
+  // thrown due to 'mem' being driven by two always processes below
+  always @(posedge clk_a_i) begin
+    if (a_req_i) begin
+      for (int i=0; i < MaskWidth; i = i + 1) begin
+        if (a_wmask[i]) begin
+          mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
+            a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
+        end
+      end
+    end
+  end
+
+  always @(posedge clk_b_i) begin
+    if (b_req_i) begin
+      b_rdata_o <= mem[b_addr_i];
+    end
+  end
+
+  `include "prim_util_memload.svh"
+`endif
+endmodule
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_2p.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_2p.sv
index 6e1ebdb5..f44e828b 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_2p.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_2p.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_rom.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_rom.sv
index 98d02a96..acf5f379 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_rom.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_rom.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv
index b94d39cd..a0b8e19c 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_usb_diff_rx.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_xnor2.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_xnor2.sv
index 1020f837..90eb684d 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_xnor2.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_xnor2.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_xor2.sv b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_xor2.sv
index 8282e8b4..4f303c77 100644
--- a/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_xor2.sv
+++ b/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_xor2.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/BUILD b/vendor/lowrisc_ip/ip/prim_xilinx/BUILD
index c87fb863..f42854cd 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/BUILD
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/BUILD
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_buf.vlt b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_buf.vlt
index 544a7b79..b8340b20 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_buf.vlt
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_buf.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_buf.waiver b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_buf.waiver
index af90009c..1e11afb4 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_buf.waiver
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_buf.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_gating.vlt b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_gating.vlt
index 544a7b79..b8340b20 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_gating.vlt
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_gating.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_gating.waiver b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_gating.waiver
index af90009c..1e11afb4 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_gating.waiver
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_gating.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_mux2.vlt b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_mux2.vlt
index 544a7b79..b8340b20 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_mux2.vlt
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_mux2.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_mux2.waiver b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_mux2.waiver
index af90009c..1e11afb4 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_mux2.waiver
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_clock_mux2.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.vlt b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.vlt
index 544a7b79..b8340b20 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.vlt
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.waiver b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.waiver
index 95afe139..198eeeac 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.waiver
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/lint/prim_xilinx_pad_wrapper.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_and2.core b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_and2.core
index b4ad3c02..9c86c83f 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_and2.core
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_and2.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,14 +15,12 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
     file_type: waiver
 
   files_veriblelint_waiver:
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_buf.core b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_buf.core
index d1e24797..bc4e7a2e 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_buf.core
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_buf.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_clock_buf.core b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_clock_buf.core
index 7bd93e25..f1bfbe8f 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_clock_buf.core
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_clock_buf.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_clock_gating.core b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_clock_gating.core
index 1e1064fb..587c7e5a 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_clock_gating.core
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_clock_gating.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_clock_mux2.core b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_clock_mux2.core
index 0ea81cc9..5d94cd0c 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_clock_mux2.core
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_clock_mux2.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_flop.core b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_flop.core
index 0e4ed2b6..b94d12c7 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_flop.core
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_flop.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,15 +15,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_flop_en.core b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_flop_en.core
index fef8cd60..e40394b8 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_flop_en.core
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_flop_en.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,15 +15,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_pad_attr.core b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_pad_attr.core
index 076c1cd0..6c103133 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_pad_attr.core
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_pad_attr.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -18,17 +18,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      #- lint/prim_xilinx_pad_attr.vlt
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-      #- lint/prim_xilinx_pad_attr.waiver
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_pad_wrapper.core b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_pad_wrapper.core
index eb0cc5ec..765845a0 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_pad_wrapper.core
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_pad_wrapper.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_xor2.core b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_xor2.core
index ff3fc7d9..e7f699cf 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_xor2.core
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/prim_xilinx_xor2.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,15 +15,11 @@ filesets:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-    files:
-    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_and2.sv b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_and2.sv
index 978aeccc..69d86836 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_and2.sv
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_and2.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_buf.sv b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_buf.sv
index 2e3915a5..7bdeea9c 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_buf.sv
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_buf.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv
index 8d6f4a31..51945f44 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv
index 501db88d..7eaac02a 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv
index 3e43f572..ee7390d9 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_flop.sv b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_flop.sv
index 7ce6adfa..45deeade 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_flop.sv
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_flop.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv
index 50d97575..c4de058a 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_flop_en.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv
index 2b4db6a5..7267465e 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -19,16 +19,19 @@ module prim_xilinx_pad_attr
   // Input-only:
   //
   // - inversion
+  // - input disable
   //
   // Bidirectional:
   //
   // - inversion
   // - virtual open drain
+  // - input disable
   //
   if (PadType == InputStd) begin : gen_input_only_warl
     always_comb begin : p_attr
       attr_warl_o = '0;
       attr_warl_o.invert = 1'b1;
+      attr_warl_o.input_disable = 1'b1;
     end
   end else if (PadType == BidirStd ||
                PadType == BidirTol ||
@@ -37,12 +40,14 @@ module prim_xilinx_pad_attr
       attr_warl_o = '0;
       attr_warl_o.invert = 1'b1;
       attr_warl_o.virt_od_en = 1'b1;
+      attr_warl_o.input_disable = 1'b1;
     end
   end else if (PadType == AnalogIn0) begin : gen_analog0_warl
     // The analog pad type is basically just a feedthrough,
-    // and does hence not support any of the attributes.
+    // and hence only supports input disable.
     always_comb begin : p_attr
       attr_warl_o = '0;
+      attr_warl_o.input_disable = 1'b1;
     end
   end else begin : gen_invalid_config
     // this should throw link warnings in elaboration
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv
index 571e394c..afb9c179 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
@@ -44,6 +44,9 @@ module prim_xilinx_pad_wrapper
                          scanmode_i,
                          pok_i};
 
+  // Input enable (active-high)
+  logic ie;
+  assign ie = ie_i & ~attr_i.input_disable;
 
   if (PadType == InputStd) begin : gen_input_only
     logic unused_sigs;
@@ -51,25 +54,26 @@ module prim_xilinx_pad_wrapper
                            oe_i,
                            attr_i.virt_od_en};
 
-    // input inversion
+    // Input buffer with input disable
+    // 7 Series devices feature the `IBUF_IBUFDISABLE` primitive that can disable the input path
+    // through the input buffer.  However, that primitive is not supported for the IOSTANDARDs we
+    // use (LVCMOS18 and LVCMOS33), so the logic below instead emulates its behavior (the disabled
+    // input gets internally driven to 1) without really disabling the input driver.
     logic in;
-    assign in_raw_o = (ie_i) ? in  : 1'bz;
-    assign in_o = attr_i.invert ^ in_raw_o;
-
     IBUF u_ibuf (
       .I ( inout_io ),
       .O ( in       )
     );
+    assign in_raw_o = ie ? in : 1'b1;
+
+    // Input inversion
+    assign in_o = attr_i.invert ^ in_raw_o;
+
   end else if (PadType == BidirTol ||
                PadType == DualBidirTol ||
                PadType == BidirOd ||
                PadType == BidirStd) begin : gen_bidir
 
-    // input inversion
-    logic in;
-    assign in_raw_o = (ie_i) ? in  : 1'bz;
-    assign in_o = attr_i.invert ^ in_raw_o;
-
     // virtual open drain emulation
     logic oe_n, out;
     assign out      = out_i ^ attr_i.invert;
@@ -77,12 +81,24 @@ module prim_xilinx_pad_wrapper
     // oe_n = 1: disable driver
     assign oe_n     = ~oe_i | (out & attr_i.virt_od_en);
 
+    // Input buffer with input disable
+    // TODO(#23094): This should be implemented with an instance of `IOBUF_DCIEN` (for pads in
+    // high-performance banks) or `IOBUF_INTERMDISABLE` (for pads in high-range banks).  This module
+    // currently doesn't know which bank the pad is in, so the logic below instead emulates this
+    // behavior (disabled inputs get internally driven to 1 for 7 Series devices) without really
+    // disabling the input driver.
+    logic in;
     IOBUF u_iobuf (
       .T  ( oe_n     ),
       .I  ( out      ),
       .O  ( in       ),
       .IO ( inout_io )
     );
+    assign in_raw_o = ie ? in : 1'b1;
+
+    // Input inversion
+    assign in_o = attr_i.invert ^ in_raw_o;
+
   end else if (PadType == AnalogIn0 || PadType == AnalogIn1) begin : gen_analog
 
     logic unused_sigs;
@@ -90,13 +106,16 @@ module prim_xilinx_pad_wrapper
                            oe_i,
                            attr_i.invert,
                            attr_i.virt_od_en};
-    // this is currently modeled as a logic feed through.
+
+    // Input buffer with input disable
+    // Input disable emulated in logic due to the limitations documented under `gen_input_only`.
+    logic in;
     IBUF u_ibuf (
       .I ( inout_io ),
-      .O ( in_raw_o )
+      .O ( in       )
     );
-
-    assign in_raw_o = inout_io;
+    assign in_raw_o = ie ? in : 1'b1;
+    assign in_o = in_raw_o;
 
   end else begin : gen_invalid_config
     // this should throw link warnings in elaboration
diff --git a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv
index b882f65f..0eb9c142 100644
--- a/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv
+++ b/vendor/lowrisc_ip/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/lint/common.core b/vendor/lowrisc_ip/lint/common.core
index 4bcd8f3c..20338eaf 100644
--- a/vendor/lowrisc_ip/lint/common.core
+++ b/vendor/lowrisc_ip/lint/common.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:lint:common:0.1"
diff --git a/vendor/lowrisc_ip/lint/comportable.core b/vendor/lowrisc_ip/lint/comportable.core
index f74083e8..851b6c17 100644
--- a/vendor/lowrisc_ip/lint/comportable.core
+++ b/vendor/lowrisc_ip/lint/comportable.core
@@ -1,5 +1,5 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 name: "lowrisc:lint:comportable:0.1"
@@ -20,5 +20,3 @@ targets:
     filesets:
       - tool_verilator  ? (files_verilator_waiver)
       - tool_ascentlint ? (files_ascentlint_waiver)
-
-
diff --git a/vendor/lowrisc_ip/lint/tools/ascentlint/ascentlint-config.tcl b/vendor/lowrisc_ip/lint/tools/ascentlint/ascentlint-config.tcl
index a4113b0a..d82ed9ab 100644
--- a/vendor/lowrisc_ip/lint/tools/ascentlint/ascentlint-config.tcl
+++ b/vendor/lowrisc_ip/lint/tools/ascentlint/ascentlint-config.tcl
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
@@ -15,5 +15,4 @@ set ri_max_single_range_bits 32768
 
 # Increase the maximum loop to 3200 (KmacStateW X 2)
 # this is a temporary fix for non-ASCII character in AscentLint log
-set ri_max_loop_unroll 3200 
-
+set ri_max_loop_unroll 3200
diff --git a/vendor/lowrisc_ip/lint/tools/ascentlint/common.waiver b/vendor/lowrisc_ip/lint/tools/ascentlint/common.waiver
index f254de2b..6c963949 100644
--- a/vendor/lowrisc_ip/lint/tools/ascentlint/common.waiver
+++ b/vendor/lowrisc_ip/lint/tools/ascentlint/common.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -9,5 +9,3 @@
 waive -rules {HIER_NET_NOT_READ HIER_BRANCH_NOT_READ} -regexp {unused_.*}
 waive -rules {HIER_NET_NOT_READ HIER_BRANCH_NOT_READ} -regexp {gen_.*\.unused_.*}
 waive -rules {ONE_BRANCH} -regexp {unique case statement has only one branch}
-
-
diff --git a/vendor/lowrisc_ip/lint/tools/ascentlint/comportable.waiver b/vendor/lowrisc_ip/lint/tools/ascentlint/comportable.waiver
index dcf62a97..e8515dab 100644
--- a/vendor/lowrisc_ip/lint/tools/ascentlint/comportable.waiver
+++ b/vendor/lowrisc_ip/lint/tools/ascentlint/comportable.waiver
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/lint/tools/dvsim/ascentlint.hjson b/vendor/lowrisc_ip/lint/tools/dvsim/ascentlint.hjson
index 7b76f3e2..088a7522 100644
--- a/vendor/lowrisc_ip/lint/tools/dvsim/ascentlint.hjson
+++ b/vendor/lowrisc_ip/lint/tools/dvsim/ascentlint.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/lint/tools/dvsim/common_lint_cfg.hjson b/vendor/lowrisc_ip/lint/tools/dvsim/common_lint_cfg.hjson
index 05571b5b..9ec23bdf 100644
--- a/vendor/lowrisc_ip/lint/tools/dvsim/common_lint_cfg.hjson
+++ b/vendor/lowrisc_ip/lint/tools/dvsim/common_lint_cfg.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
@@ -29,11 +29,12 @@
                "{fusesoc_core}"]
 
   // Determines which message severities to print into report summaries.
-  report_severities: ["warning", "error"]
+  report_severities: ["info", "warning", "error"]
   // Determines which message severities lead to a pass/fail.
   fail_severities: ["warning", "error"]
   // Define message bucket categories and severities.
   message_buckets: [
+    {category: "flow", severity: "info",     label: ""},
     {category: "flow", severity: "warning",  label: ""},
     {category: "flow", severity: "error",    label: ""},
     {category: "lint", severity: "info",     label: ""},
diff --git a/vendor/lowrisc_ip/lint/tools/dvsim/lint.mk b/vendor/lowrisc_ip/lint/tools/dvsim/lint.mk
index afca82ee..d7ce4708 100644
--- a/vendor/lowrisc_ip/lint/tools/dvsim/lint.mk
+++ b/vendor/lowrisc_ip/lint/tools/dvsim/lint.mk
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
diff --git a/vendor/lowrisc_ip/lint/tools/dvsim/veriblelint.hjson b/vendor/lowrisc_ip/lint/tools/dvsim/veriblelint.hjson
index a3b8f2f8..601164fa 100644
--- a/vendor/lowrisc_ip/lint/tools/dvsim/veriblelint.hjson
+++ b/vendor/lowrisc_ip/lint/tools/dvsim/veriblelint.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/lint/tools/dvsim/verilator.hjson b/vendor/lowrisc_ip/lint/tools/dvsim/verilator.hjson
index 62bf0b38..46419053 100644
--- a/vendor/lowrisc_ip/lint/tools/dvsim/verilator.hjson
+++ b/vendor/lowrisc_ip/lint/tools/dvsim/verilator.hjson
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
diff --git a/vendor/lowrisc_ip/lint/tools/veriblelint/lowrisc-styleguide.rules.verible_lint b/vendor/lowrisc_ip/lint/tools/veriblelint/lowrisc-styleguide.rules.verible_lint
index 6f03c3f2..c7678d28 100644
--- a/vendor/lowrisc_ip/lint/tools/veriblelint/lowrisc-styleguide.rules.verible_lint
+++ b/vendor/lowrisc_ip/lint/tools/veriblelint/lowrisc-styleguide.rules.verible_lint
@@ -1,4 +1,4 @@
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 #
diff --git a/vendor/lowrisc_ip/lint/tools/verilator/common.vlt b/vendor/lowrisc_ip/lint/tools/verilator/common.vlt
index 625b46a8..5416c164 100644
--- a/vendor/lowrisc_ip/lint/tools/verilator/common.vlt
+++ b/vendor/lowrisc_ip/lint/tools/verilator/common.vlt
@@ -1,4 +1,4 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
diff --git a/vendor/lowrisc_ip/lint/tools/verilator/comportable.vlt b/vendor/lowrisc_ip/lint/tools/verilator/comportable.vlt
index 5da936b4..9b914ca5 100644
--- a/vendor/lowrisc_ip/lint/tools/verilator/comportable.vlt
+++ b/vendor/lowrisc_ip/lint/tools/verilator/comportable.vlt
@@ -1,6 +1,5 @@
-// Copyright lowRISC contributors.
+// Copyright lowRISC contributors (OpenTitan project).
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
 // comportable IP waiver rules for verilator
-