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Update lowrisc_ibex to lowRISC/ibex@594ea976
Update code from upstream repository https://github.com/lowRISC/ibex.git to revision 594ea976c9dad793f87edf91ec1c4c1df447e6dc * [dv] Plan test for DM accesses in debug mode (Andreas Kurth) * fix: Illegal instruction display message (Hao) * Verification should be done with ibex_cosim branch (Marno van der Maas) * [ci] switch CI runner from Ubuntu 20.04 to 22.04 (Gary Guo) * [ci] update verible version to match OT (Gary Guo) * [ci] remove Azure Pipelines magic commands (Gary Guo) * [cosim] Update comment on `set_mip` in Cosim interface (Greg Chadwick) * [rtl] Remove low utility assertions (Greg Chadwick) * [rtl] Flush pipe on all CSR modifications (Greg Chadwick) * [rtl] Read csr_addr direct from instruction (Greg Chadwick) * [ibex_core] Fix assertion when SecureIbex is false (Rupert Swarbrick) * [ibex_register_file_fpga] Drop two confusing comments (Rupert Swarbrick) * Fix typo in comment in ibex_id_stage.sv (Katharina) * [ibex_tracer] Use static variables in always/final blocks (Robert Schilling) * [rtl] Drive oh_raddr_*_err if RdataMuxCheck=0 (Rupert Swarbrick) * Update core_ibex_pmp_fcov_if.sv (Priyanshu Mishra) * [rtl,pmp] Allow all accesses to Debug Module in debug mode (Andreas Kurth) * [controller] Add assertion on pipeline flush when entering debug mode (Andreas Kurth) * ibex_pcounts: resolve uninitialize warning (Marno van der Maas) * [rtl] Fix non-DSP reset in ibex_counter (Pascal Nasahl) * Revert "[rtl] Fix counter reset value on FPGA" (Pascal Nasahl) * [rtl] Fix counter reset value on FPGA (Pascal Nasahl) * [ci] remove Azure Pipelines (Gary Guo) * [rtl] Fix zero value in FPGA RF (Pascal Nasahl) * Block diagram: make feature text readable (Marno van der Maas) * Block diagram: fixes and improved looks (Marno van der Maas) * [dv] Cleanup some code in the compile_tb.py module (Harry Callahan) * [dv] Tweak ISS linker arg construction for Xcelium (Harry Callahan) * [pmp] Use top-level straps for PMP reset values (Robert Schilling) * Update more documentation links (Elliot Baptist) * Update verification_stages.rst OT links (Elliot Baptist) * [rtl] Fix wrong address in latch RF (Pascal Nasahl) * [rtl] fix a typo. (lingscale) * [doc] fix a typo. (lingscale) * Fix icache regression failure on VCS (Gary Guo) * [rtl] Remove ECC related data_rdata_i -> instr_X_o feedthroughs (Greg Chadwick) * Add SECURITY.md (Greg Chadwick) * [dv] Increase iterations and instructions in riscv_rf_intg_test (Greg Chadwick) * [dv] Alter riscv_rf_intg_test to cover more scenarios (Greg Chadwick) * [rtl] Fix logic for generating ECC related alerts (Greg Chadwick) * [dv] Add spurious responses to memory agent (Greg Chadwick) * [dv] Add riscv_ram_intg_test This test injects a fault into different MuBi encoded signals within the prim_ram_1p_scr and prim_ram_1p_adv and checks whether a fatal alert is triggered. (Pascal Nasahl) * [cosim] Clang lint fix (Greg Chadwick) * [ci] Bump co-sim version (Greg Chadwick) * [dv] Output warning message on problematic MIP changes (Greg Chadwick) * [cosim] Correctly deal with checking top of range memory accesses (Greg Chadwick) * [dv] Update testbench to use new 'pre_val' MIP (Greg Chadwick) * [dv] Fix model mismatches in cases where an access crosses PMP regions (Greg Chadwick) * [dv] Fix exception_stall_instr_cross illegal bins (Greg Chadwick) * [dv] Add riscv_rf_ctrl_intg_test (Greg Chadwick) * [ci] update private CI (Gary Guo) * [dv] Add cover points for memory interface behaviour (Greg Chadwick) * [dv] Fix race condition in ibex_mem_intf_agent (Greg Chadwick) * [doc] Fix C++ style guide link in README (James Wainwright) * [dv] Remove phase argument from collect_trans (Pascal Nasahl) * [dv] Add mubi and prim_count pkg to DV environment (Pascal Nasahl) * Update lowrisc_ip to lowRISC/opentitan@d268f271f4 (Pascal Nasahl) * [rtl] Add error port to iCache (Pascal Nasahl) * [rtl] Update RAM ports inside ibex_top (Pascal Nasahl) * [rtl] Guard against false memory responses for secure configurations (Greg Chadwick) * Expand the coverage plan after a review (Marno van der Maas) * [rtl] Expose ICacheScrNumPrinceRoundsHalf parameter (Pirmin Vogel) * Add missing copyright headers (James Wainwright) * [simple_system] Bump C++ version in core files (Rupert Swarbrick) * Keep to patch numbering convention (Marno van der Maas) * [ci] Add missing sudo in CI (Gary Guo) * [dv] Output VCS simulation log to file (Greg Chadwick) * [dv] Add flag needed to allow force under VCS (Greg Chadwick) * [dv] Fix use of plusargs (Greg Chadwick) * [fcov] Fix illegal bins related to stall types (Greg Chadwick) * [dv] Handle missing paths when producing regression log (Greg Chadwick) * [dv] Only run SecureIbex relevant tests for SecureIbex configs (Greg Chadwick) * [dv] Fix regression for non PMP configs (Greg Chadwick) * [dv] Fix path for vcs.tcl for wave dumping (Greg Chadwick) * [dv, cov] Log coverage merge stdout for VCS (Greg Chadwick) * [cosim] Fix SIGSEGV in ~SpikeCosim (Greg Chadwick) * [dv] Skip SVG generation in DV flow if svg module is missing (Greg Chadwick) * [dv] Flow modifications for CentOS 7 for testbench compile (Greg Chadwick) * Require Pydantic 2 or above (Marno van der Maas) * [rtl] Update use of prim_count following port changes (Greg Chadwick) * Update lowrisc_ip to lowRISC/opentitan@e0c4026501 (Greg Chadwick) * [tracer] Fix reporting of load/store data (Adrian Lees) * [bus] Return error if decode fails (Adrian Lees) * Update old `cpuctrl` CSR name in `cs_registers.rst` (Luís Marques) * Update benchmarks README to better explain how to try different configs (Greg Chadwick) * Enable the icache in coremark (Greg Chadwick) * Add icache_enable function to simple_system_common.h (Greg Chadwick) * Fix stale merge commit issue in private CI (Gary Guo) * [doc] Require sphinx version >= 7.0 (Greg Chadwick) * [rtl] Harden lockstep enable against FI (Pascal Nasahl) * Update verilator version (Pascal Nasahl) * [icache] Disable S&P diffusion layer in memory scrambling (Michael Schaffner) * Update lowrisc_ip to lowRISC/opentitan@4cf2479b8e (Michael Schaffner) * [dv] Fix paths in `merge_cov.py` (Sᴜᴘᴇʀ Lᴇᴇ) * Add NOTICE file (Michael Munday) * Tweak questa timescale argument (Harry Callahan) * Fixup the questa build/sim command templates in rtl_simulation.yaml (Harry Callahan) Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
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vendor/lowrisc_ibex.lock.hjson

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upstream:
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{
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url: https://github.com/lowRISC/ibex.git
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rev: c9f4a329636e59acb10647333badbb31bc7512b8
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rev: 594ea976c9dad793f87edf91ec1c4c1df447e6dc
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}
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}

vendor/lowrisc_ibex/.svlint.toml

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# Rules for svlint, a SystemVerilog linter commonly used in editors.
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# The configuration matches the lowRISC SystemVerilog style guide at
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# https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md.
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# See https://github.com/dalance/svlint/blob/master/RULES.md for a list of rules.
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# See https://github.com/dalance/svlint/blob/master/MANUAL.md for a list of rules.
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[option]
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exclude_paths = ["build.*", "sw/.*", ".sv.tpl$", "vendor/.*"]

vendor/lowrisc_ibex/NOTICE

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The Ibex Project
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Copyright 2024 lowRISC contributors.
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This product includes hardware and/or software developed as part of the
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Ibex(R) (https://github.com/lowRISC/ibex) and OpenTitan(R) projects.
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Ibex was originally developed by the PULP team at ETH Zurich and University of
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Bologna under the name zero-riscy. Ibex verification, performance enhancement
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and security hardening have been supported by the OpenTitan project
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(https://www.opentitan.org).

vendor/lowrisc_ibex/README.md

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coding style guide](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md).
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When contributing C or C++ source code, please try to adhere to [the OpenTitan C++ coding style
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guide](https://docs.opentitan.org/doc/rm/c_cpp_coding_style/).
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guide](https://opentitan.org/book/doc/contributing/style_guides/c_cpp_coding_style.html).
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All C and C++ code should be formatted with clang-format before committing.
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Either run `clang-format -i filename.cc` or `git clang-format` on added files.
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vendor/lowrisc_ibex/SECURITY.md

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# Reporting Security Issues
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The lowRISC team and Ibex community (including the OpenTitan partnership) take security issues seriously.
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We appreciate all efforts to find security vulnerabilities in Ibex and ask that responsible disclosure is practiced should you discover a potential vulnerability.
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As Ibex and in particular its secure configuration was developed as part of [OpenTitan](https://www.github.com/lowrisc/opentitan) contact [security@opentitan.org](mailto:security@opentitan.org) to report any security issues and do not open a public issue.
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[security@opentitan.org](mailto:security@opentitan.org) will advise on the coordinated vulnerability disclosure (CVD) procedure.

vendor/lowrisc_ibex/azure-pipelines.yml

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vendor/lowrisc_ibex/ci/azp-private.yml

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vendor/lowrisc_ibex/ci/ibex-rtl-ci-steps.yml

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vendor/lowrisc_ibex/ci/install-build-deps.sh

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fi
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case "$ID-$VERSION_ID" in
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ubuntu-16.04|ubuntu-18.04|ubuntu-20.04)
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ubuntu-20.04|ubuntu-22.04)
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# Curl must be available to get the repo key below.
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$SUDO_CMD apt-get update
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$SUDO_CMD apt-get install -y curl
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$SUDO_CMD mkdir -p /tools/riscv-isa-sim
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$SUDO_CMD chmod 777 /tools/riscv-isa-sim
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$SUDO_CMD tar -C /tools/riscv-isa-sim -xvzf ibex-cosim-"$IBEX_COSIM_VERSION".tar.gz --strip-components=1
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echo "##vso[task.prependpath]/tools/riscv-isa-sim/bin"
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echo "/tools/riscv-isa-sim/bin" >> $GITHUB_PATH
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wget https://storage.googleapis.com/verilator-builds/verilator-"$VERILATOR_VERSION".tar.gz
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$SUDO_CMD mkdir -p /tools/verilator
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$SUDO_CMD chmod 777 /tools/verilator
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$SUDO_CMD tar -C /tools/verilator -xvzf verilator-"$VERILATOR_VERSION".tar.gz
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echo "##vso[task.prependpath]/tools/verilator/$VERILATOR_VERSION/bin"
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echo "/tools/verilator/$VERILATOR_VERSION/bin" >> $GITHUB_PATH
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# Python dependencies
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#
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# Install Verible
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mkdir -p build/verible
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cd build/verible
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curl -Ls -o verible.tar.gz "https://github.com/google/verible/releases/download/$VERIBLE_VERSION/verible-$VERIBLE_VERSION-Ubuntu-$VERSION_ID-$VERSION_CODENAME-x86_64.tar.gz"
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$SUDO_CMD mkdir -p /tools/verible && $SUDO_CMD chmod 777 /tools/verible
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tar -C /tools/verible -xf verible.tar.gz --strip-components=1
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echo "##vso[task.prependpath]/tools/verible/bin"
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VERIBLE_URL="https://github.com/chipsalliance/verible/releases/download/$VERIBLE_VERSION/verible-$VERIBLE_VERSION-linux-static-x86_64.tar.gz"
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$SUDO_CMD mkdir -p /tools/verible
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curl -sSfL "$VERIBLE_URL" | $SUDO_CMD tar -C /tools/verible -xvzf - --strip-components=1
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# Fixup bin permission which is broken in tarball.
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$SUDO_CMD chmod 755 /tools/verible/bin
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echo "/tools/verible/bin" >> $GITHUB_PATH
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;;
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mkdir -p build/toolchain
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curl -Ls -o build/toolchain/rv32-toolchain.tar.xz "$TOOLCHAIN_URL"
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$SUDO_CMD mkdir -p /tools/riscv && $SUDO_CMD chmod 777 /tools/riscv
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tar -C /tools/riscv -xf build/toolchain/rv32-toolchain.tar.xz --strip-components=1
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echo "##vso[task.prependpath]/tools/riscv/bin"
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$SUDO_CMD tar -C /tools/riscv -xf build/toolchain/rv32-toolchain.tar.xz --strip-components=1
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echo "/tools/riscv/bin" >> $GITHUB_PATH

vendor/lowrisc_ibex/ci/run-cosim-test.sh

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# SPDX-License-Identifier: Apache-2.0
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#
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# Run an elf against simple system co-simulation and check the UART output for
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# reported pass/fail reporting as appropriate for use in Azure pipelines
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# reported pass/fail reporting as appropriate for use in GitHub Actions
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SKIP_PASS_CHECK=0
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echo "Running $TEST_NAME with co-simulation"
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build/lowrisc_ibex_ibex_simple_system_cosim_0/sim-verilator/Vibex_simple_system --meminit=ram,$TEST_ELF
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if [ $? != 0 ]; then
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echo "##vso[task.logissue type=error]Running % failed co-simulation testing"
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echo "::error::Running % failed co-simulation testing"
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exit 1
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fi
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grep 'FAILURE' ibex_simple_system.log
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if [ $? != 1 ]; then
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echo "##vso[task.logissue type=error]Failure seen in $TEST_NAME log"
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echo "::error::Failure seen in $TEST_NAME log"
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echo "Log contents:"
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if [ $SKIP_PASS_CHECK != 1 ]; then
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grep 'PASS' ibex_simple_system.log
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if [ $? != 0 ]; then
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echo "##vso[task.logissue type=error]No pass seen in $TEST_NAME log"
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echo "::error::No pass seen in $TEST_NAME log"
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echo "Log contents:"
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cat ibex_simple_system.log

vendor/lowrisc_ibex/ci/vars.env

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# Pipeline variables, used by the public and private CI pipelines
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# Quote values to ensure they are parsed as string (version numbers might
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# end up as float otherwise).
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VERILATOR_VERSION=v4.104
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IBEX_COSIM_VERSION=15fbd568
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VERILATOR_VERSION=v4.210
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IBEX_COSIM_VERSION=39612f9
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RISCV_TOOLCHAIN_TAR_VERSION=20220210-1
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RISCV_TOOLCHAIN_TAR_VARIANT=lowrisc-toolchain-gcc-rv32imcb
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RISCV_COMPLIANCE_GIT_VERSION=844c6660ef3f0d9b96957991109dfd80cc4938e2
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VERIBLE_VERSION=v0.0-2135-gb534c1fe
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VERIBLE_VERSION=v0.0-3622-g07b310a3
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# lowRISC-internal version numbers of Ibex-specific Spike builds.
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SPIKE_IBEX_VERSION=20220817-git-eccdcb15c3e51b4f7906c7b42fb824f24a4338a2

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