Support Hex String in mode bits of both OpenFPGA architecture file and bitstream setting file

[tangxifan]

Is your feature request related to a problem? Please describe.
Currently, the mode bits of any pb_type can be assigned from

• OpenFPGA architecture description file. For example,

 <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
 </pb_type>

• OpenFPGA bitstream setting file. For example,

<default_mode_bits name="clb.fle[n1_lut6].ble6.lut6" mode_bits="0"/>

The growing complexity of programmable logic blocks, especially DSP and BRAM, results in the large length of mode bits.
For example, the mode selection bits of a DSP can easily reach more than 32 bits.
In such case, the current binary format of mode bits causes issues:

• No easy to hand craft.
• Prune to make mistakes
• Hard to debug

When imagine something like:

<default_mode_bits name="dsp[core].DSP32" mode_bits="00001100001000001100010000000000"/>

Describe the solution you'd like

To simplify the writing, HEX format should be introduced. For example,

<default_mode_bits name="dsp[core].DSP32" mode_bits="32h'0A10B1FE"/>

This will help user to hand-craft long mode bits which is easy to debug.

Considering to add a new syntax to allow users to select between little-endian and big-endian

32H'0A10B1FE -> big endian in HEX format
32h'0A10B1FE -> little endian in HEX format

[tangxifan]

@ganeshgore @tpagarani Feel free to comment here. This is my plan. See if you have further needs. We can address them.