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Was added script xilinx-pll-calc.php
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‎README.adoc

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=== Initial git settings of new EDA-related repository
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The `git-setting.sh` script create empty repo in speciffyed location and set up required setting for EDA-related projects (at the first one: the proper `.gitattributes` and `.gitignore` files)
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The `git-setting.sh` script create empty repo in specifyed location and set up required setting for EDA-related projects (at the first one: the proper `.gitattributes` and `.gitignore` files)
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Detailed description:
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include::git-setting.adoc[leveloffset=+2]
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=== Find proper parameters for getting desired Frequency value by PLL/DCM block of Xilinx FPGA
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The `xilinx-pll-calc.php` script print table of proper parameters for desired output frequency (based on known input frequency)
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Detailed description:
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include::xilinx-pll-calc.adoc[leveloffset=+2]
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== License
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‎image/xilinx-pll-calc.png

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‎xilinx-pll-calc.adoc

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= Find proper parameters for getting desired Frequency by PLL/DCM block of Xilinx FPGA
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The `xilinx-pll-calc.php` script print table of proper parameters for desired output frequency (based on known input frequency)
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== Usage
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. Customize following variables `$F_input` (Hz), `$F_desired` (Hz) and `$precission` (%) in `xilinx-pll-calc.php`
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. Choice proper FPGA family, e.g.: `$FPGA = $SPARTAN6;`
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. Run it:
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```
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php xilinx-pll-calc.php
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```
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and looking for bold green string with exactly frequency value:
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image::image/xilinx-pll-calc.png[]
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== Limitation
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This script supports following family:
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* Xilinx Spartan-6
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* Xilinx Virtex-7
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* [Add your favourite FPGA. See next chapter]
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=== Adding new FPGA family
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Xilinx, Altera, Lattice?... Everything can be supported!
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The quick and dirty way to adding new family is filling associated array like that:
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```
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$VIRTEX7 = array(
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"FREQ_INP_MIN" => 19e6,
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"FREQ_INP_MAX" => 800e6,
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"FREQ_VCO_MIN" => 800e6,
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"FREQ_VCO_MAX" => 1600e6,
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"FREQ_OUT_MIN" => 6.25e6,
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"FREQ_OUT_MAX" => 800e6,
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"M_MIN" => 2,
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"M_MAX" => 64,
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"D_MIN" => 1,
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"D_MAX" => 128,
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"O_MIN" => 1,
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"O_MAX" => 56);
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```
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Use this equation for explanation key name, like: M, D, O, FREQ_INP, FREQ_VCO, FREQ_OUT.
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```
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#######################
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######################## #
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# # Useful Folmulae #
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# M # for PLL Equation #
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# Fvco = Fin * - # #
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# D #######################
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# #
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# Fvco M #
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# Fout = ---- or Fout = Fin * ----- #
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# O D*O #
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# #
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###########################################
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```
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== Explanation of working
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see the source code link:xilinx-pll-calc.php[]
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== ToDo
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* Mode of chaining two PLL in serial connection (for solving unresolved with single PLL Freq ratio)
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== Known issues
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not yet known

‎xilinx-pll-calc.php

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<?php
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/**
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* A PHP calculator for desired frequency by PLL/DCM onto Xilinx FPGA
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* @package
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* @author Dmitry Murzinov (kakstattakim@gmail.com)
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* @link : https://github.com/iDoka/eda-scripts
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* @version 1.0
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*/
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#######################
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######################## #
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# # Useful Folmulae #
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# M # for PLL Equation #
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# Fvco = Fin * - # #
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# D #######################
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# #
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# Fvco M #
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# Fout = ---- or Fout = Fin * ----- #
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# O D*O #
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# #
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###########################################
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# Example of usage:
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# $ php xilinx-pll-calc.php
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#
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$F_input = 50e6; // Hz
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$F_desired = 48e6; // Hz
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$precission = 0.5; // %
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//$tolerance=1; // %
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// check if CLI-mode
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if (PHP_SAPI != "cli") {
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exit;
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}
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define('__ROOT__', dirname(__FILE__));
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//require_once(__ROOT__.'/PLL-func.php');
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/*
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// parsing arg as filename
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if ($argc > 1) {
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$filename = $argv[1];
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$contents = file_get_contents($filename);
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$contents = utf8_encode($contents);
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$pinout = json_decode($contents,TRUE);
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}
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else {
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echo "Usage tool in CLI:\n\t$ php xilinx-pll-calc.php\n";
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exit;
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}
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*/
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###########################################
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### Store of settings different PLL
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$SPARTAN6 = array( // -3 grade -2 grade -1L grade
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"FREQ_INP_MIN" => 19e6,
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"FREQ_INP_MAX" => 450e6, // 540 450 300
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"FREQ_VCO_MIN" => 400e6,
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"FREQ_VCO_MAX" => 1000e6, // 1080 1000 1000
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"FREQ_OUT_MIN" => 3.125e6,
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"FREQ_OUT_MAX" => 950e6, // 1080 950 500
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"M_MIN" => 1,
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"M_MAX" => 64,
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"D_MIN" => 1,
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"D_MAX" => 128,
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"O_MIN" => 1,
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"O_MAX" => 52);
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$VIRTEX7 = array( // -3 grade -2 grade -1 grade
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"FREQ_INP_MIN" => 19e6,
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"FREQ_INP_MAX" => 800e6, // 1066 933 800
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"FREQ_VCO_MIN" => 800e6,
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"FREQ_VCO_MAX" => 1600e6, // 2133 1866 1600
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"FREQ_OUT_MIN" => 6.25e6,
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"FREQ_OUT_MAX" => 800e6, // 1066 933 800
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"M_MIN" => 2,
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"M_MAX" => 64,
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"D_MIN" => 1,
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"D_MAX" => 128,
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"O_MIN" => 1,
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"O_MAX" => 56);
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###########################################
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/*
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Stages:
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1. Check input range
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2. Check output range
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3. Pick up 3 cycles for proper Fvco and Fout with desired tolerance
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4. If unsuccessful -> goto chain of 2 serial PLL connection
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*/
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// Pick up desired FPGA family:
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$FPGA = $SPARTAN6;
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########## 1. Check input range ##########
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if (($FPGA["FREQ_INP_MIN"] > $F_input) | ($FPGA["FREQ_INP_MAX"] < $F_input)) {
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echo "CAUTION: Input frequency out of range!".PHP_EOL;
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exit;
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}
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########## 2. Check output range ##########
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if (($FPGA["FREQ_OUT_MIN"] > $F_desired) or ($FPGA["FREQ_OUT_MAX"] < $F_desired)) {
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echo "CAUTION: Output frequency out of range!".PHP_EOL;
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exit;
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}
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$tolerance = $precission / 100; // parts
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echo PHP_EOL."Settings:".PHP_EOL."\tFinput: $F_input Hz".PHP_EOL."\tFoutput: $F_desired Hz (desired)".PHP_EOL.PHP_EOL;
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//echo "\e[7m M\tD\tO \tFout (Error)\e[0m".PHP_EOL;
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echo "\e[7m M D O Fout (Error)\e[0m".PHP_EOL;
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echo "===== ===== ========= =========== =======".PHP_EOL;
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########## 3. Pick up 3 cycles for proper Fvco and Fout with desired tolerance ##########
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for ($M=$FPGA["M_MIN"]; $M<=$FPGA["M_MAX"]; $M++) {
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for ($D=$FPGA["D_MIN"]; $D<=$FPGA["D_MAX"]; $D++) {
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$F_VCO = $F_input * $M/$D;
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if (($FPGA["FREQ_VCO_MIN"] <= $F_VCO) and ($FPGA["FREQ_VCO_MAX"] >= $F_VCO)) {
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//echo "M=$M \tD=$D \tVCO=$F_VCO".PHP_EOL;
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for ($O=$FPGA["O_MIN"]; $O<=$FPGA["O_MAX"]; $O++) {
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$F_output = $F_input * $M/$D/$O;
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if ((($F_desired*(1-$tolerance)) <= $F_output) and ($F_output <= ($F_desired*(1+$tolerance)))) {
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$deviation = ceil(abs($F_output/$F_desired-1)*100*100)/100;
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if ($F_desired == $F_output) {
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echo "\e[1m\e[32m $M\t$D\t$O \t$F_output bingo\e[0m".PHP_EOL;
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} else {
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$F_output = round($F_output);
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echo " $M\t$D\t$O \t$F_output ($deviation%)".PHP_EOL;
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}
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}
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}
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}
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}
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}
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########## 4. chain of 2 serial PLL connection ##########
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# To do ...
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###########################################################################################################
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?>

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