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Commit ab2bd44

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author
Tim Essig
committed
Finished generic DMX Module
1 parent a574946 commit ab2bd44

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3 files changed

+102
-64
lines changed

3 files changed

+102
-64
lines changed

artnet.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,6 @@ void universeReceivedTMP(uint8_t universe) {
2020
}
2121

2222
void doTimerStuff1Hz(void) {
23-
PORTA.DIRTGL = 0x03;
24-
2523
for(uint8_t i=0; i < 4; i++) {
2624
universeFPS[i] = universeFPSCounter[i];
2725
universeFPSCounter[i] = 0;

dmx.c

Lines changed: 100 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -5,111 +5,151 @@
55
#include <util/delay.h>
66

77

8-
9-
108
uint8_t dmxBuffer[DMX_NUM_UNIVERSES][DMX_UNIVERSE_SIZE];
119

1210
uint8_t* getUniverseBuffer(uint8_t universe) {
1311
return dmxBuffer[universe];
1412
}
1513

1614

17-
1815
enum DMX_STATE {
1916
DMX_IDLE,
2017
DMX_BREAK,
2118
DMX_START,
2219
DMX_RUN
2320
};
2421

22+
typedef struct DMX_PORT {
23+
PORT_t* PORT;
24+
uint8_t PIN;
25+
register8_t* PIN_CTRL;
26+
USART_t* USART;
27+
uint8_t UNIVERSE;
28+
uint8_t OUTPUT_PORT;
29+
enum DMX_STATE TX_STATE;
30+
uint16_t TX_POSITION;
2531

26-
enum DMX_STATE dmx0state = DMX_IDLE;
27-
enum DMX_STATE dmx1state = DMX_IDLE;
28-
enum DMX_STATE dmx2state = DMX_IDLE;
29-
enum DMX_STATE dmx3state = DMX_IDLE;
30-
uint16_t dmx0ch = 0;
31-
uint16_t dmx1ch = 0;
32-
uint16_t dmx2ch = 0;
33-
uint16_t dmx3ch = 0;
32+
} DMX_t;
33+
34+
35+
volatile DMX_t dmxPorts[DMX_NUM_UNIVERSES];
3436

3537

3638
#define DMX_BAUD_BSCALE 0 // vorher 0b1001 -> -1
3739
#define DMX_BAUD_RESET_BSEL 15 // 125k BAUD @32Mhz, used for RESET
3840
#define DMX_BAUD_NORMAL_BSEL 7 // 250k BAUD @32Mhz
3941

40-
#define UART0 USARTD0
42+
void setupDMXPort(DMX_t* PORT) {
43+
PORT->PORT->DIRSET = 1 << PORT->PIN; // Pin 3 -> UART 0 TX
44+
*PORT->PIN_CTRL = PORT_INVEN_bm;
4145

42-
void setupDMXPort(USART_t* uart) {
43-
uart->BAUDCTRLB = DMX_BAUD_BSCALE << 4;
44-
uart->BAUDCTRLA = DMX_BAUD_RESET_BSEL;
46+
PORT->USART->BAUDCTRLB = DMX_BAUD_BSCALE << 4;
47+
PORT->USART->BAUDCTRLA = DMX_BAUD_RESET_BSEL;
4548

46-
uart->CTRLA = USART_TXCINTLVL_gm; // TX Highest INT Level
47-
uart->CTRLC = USART_SBMODE_bm | USART_CHSIZE_8BIT_gc; //2 StopBits, 8 DataBits
49+
PORT->USART->CTRLA = USART_TXCINTLVL_gm; // TX Highest INT Level
50+
PORT->USART->CTRLC = USART_SBMODE_bm | USART_CHSIZE_8BIT_gc; //2 StopBits, 8 DataBits
4851

49-
uart->CTRLB = USART_TXEN_bm; //Enable TX
52+
PORT->USART->CTRLB = USART_TXEN_bm; //Enable TX
5053
}
5154

5255
void setupDMX(void) {
53-
//DMX 1
54-
PORTC.DIRSET = PIN3_bm; // Pin 3 -> UART 0 TX
55-
PORTC.PIN3CTRL = PORT_INVEN_bm;
56-
setupDMXPort(&USARTC0);
57-
58-
//DMX 2
59-
PORTC.DIRSET = PIN7_bm; // Pin 3 -> UART 0 TX
60-
PORTC.PIN7CTRL = PORT_INVEN_bm;
61-
setupDMXPort(&USARTC1);
62-
63-
64-
//DMX 3
65-
PORTD.DIRSET = PIN3_bm; // Pin 3 -> UART 0 TX
66-
PORTD.PIN3CTRL = PORT_INVEN_bm;
67-
setupDMXPort(&USARTD0);
68-
69-
//DMX 4
70-
PORTE.DIRSET = PIN3_bm; // Pin 3 -> UART 0 TX
71-
PORTE.PIN3CTRL = PORT_INVEN_bm;
72-
setupDMXPort(&USARTE0);
56+
dmxPorts[0].PORT = &PORTC;
57+
dmxPorts[0].PIN = 3;
58+
dmxPorts[0].PIN_CTRL = &PORTC.PIN3CTRL;
59+
dmxPorts[0].USART = &USARTC0;
60+
dmxPorts[0].UNIVERSE = 0;
61+
dmxPorts[0].OUTPUT_PORT = 1;
62+
dmxPorts[0].TX_STATE = DMX_IDLE;
63+
64+
dmxPorts[1].PORT = &PORTC;
65+
dmxPorts[1].PIN = 7;
66+
dmxPorts[1].PIN_CTRL = &PORTC.PIN7CTRL;
67+
dmxPorts[1].USART = &USARTC1;
68+
dmxPorts[1].UNIVERSE = 1;
69+
dmxPorts[1].OUTPUT_PORT = 2;
70+
dmxPorts[1].TX_STATE = DMX_IDLE;
71+
72+
dmxPorts[2].PORT = &PORTD;
73+
dmxPorts[2].PIN = 3;
74+
dmxPorts[2].PIN_CTRL = &PORTD.PIN3CTRL;
75+
dmxPorts[2].USART = &USARTD0;
76+
dmxPorts[2].UNIVERSE = 2;
77+
dmxPorts[2].OUTPUT_PORT = 3;
78+
dmxPorts[2].TX_STATE = DMX_IDLE;
79+
80+
dmxPorts[3].PORT = &PORTE;
81+
dmxPorts[3].PIN = 3;
82+
dmxPorts[3].PIN_CTRL = &PORTE.PIN3CTRL;
83+
dmxPorts[3].USART = &USARTE0;
84+
dmxPorts[3].UNIVERSE = 3;
85+
dmxPorts[3].OUTPUT_PORT = 4;
86+
dmxPorts[3].TX_STATE = DMX_IDLE;
87+
88+
89+
for(uint8_t i=0; i < DMX_NUM_UNIVERSES; i++) {
90+
setupDMXPort(&dmxPorts[i]);
91+
}
7392
}
7493

7594

76-
void startDMX_TX(void) {
77-
if(dmx0state == DMX_IDLE) {
78-
//Set Baud
79-
UART0.BAUDCTRLA = DMX_BAUD_RESET_BSEL;
80-
UART0.BAUDCTRLB = DMX_BAUD_BSCALE << 4;
95+
void startDMX_TX(void) {
96+
for(uint8_t i=0; i < DMX_NUM_UNIVERSES; i++) {
97+
if(dmxPorts[i].TX_STATE == DMX_IDLE) {
98+
//Set Baud
99+
dmxPorts[i].USART->BAUDCTRLA = DMX_BAUD_RESET_BSEL;
100+
dmxPorts[i].USART->BAUDCTRLB = DMX_BAUD_BSCALE << 4;
81101

82-
//Send Break Byte
83-
UART0.DATA = 0x00;
102+
//Send Break Byte
103+
dmxPorts[i].USART->DATA = 0x00;
84104

85-
dmx0state = DMX_START;
105+
dmxPorts[i].TX_STATE = DMX_START;
106+
}
86107
}
87108
}
88109

89-
ISR(USARTD0_TXC_vect) //Transimission complete
90-
{
91-
92-
switch(dmx0state) {
110+
/**
111+
* Handle DMX Tx Interrupt
112+
*/
113+
void txISR(DMX_t* PORT) {
114+
switch(PORT->TX_STATE) {
93115
case DMX_START:
94116
//Change Baudrate
95-
UART0.BAUDCTRLA = DMX_BAUD_NORMAL_BSEL;
96-
UART0.BAUDCTRLB = DMX_BAUD_BSCALE << 4;
117+
PORT->USART->BAUDCTRLA = DMX_BAUD_NORMAL_BSEL;
118+
PORT->USART->BAUDCTRLB = DMX_BAUD_BSCALE << 4;
97119

98120
//SEND START Byte
99-
UART0.DATA = 0x00;
100-
101-
102-
dmx0ch = 0;
103-
dmx0state = DMX_RUN;
121+
PORT->USART->DATA = 0x00;
104122

123+
PORT->TX_POSITION = 0;
124+
PORT->TX_STATE = DMX_RUN;
105125
break;
106126
case DMX_RUN:
107-
UART0.DATA = dmxBuffer[0][dmx0ch++];
127+
PORT->USART->DATA = dmxBuffer[PORT->UNIVERSE][PORT->TX_POSITION++];
108128

109-
if(dmx0ch >= 512) {
110-
dmx0state = DMX_IDLE;
129+
if(PORT->TX_POSITION >= 512) {
130+
PORT->TX_STATE = DMX_IDLE;
111131
}
112132
break;
113133

114134
}
115135
}
136+
137+
ISR(USARTC0_TXC_vect) //Transimission complete
138+
{
139+
txISR(&dmxPorts[0]);
140+
}
141+
142+
ISR(USARTC1_TXC_vect) //Transimission complete
143+
{
144+
txISR(&dmxPorts[1]);
145+
}
146+
147+
ISR(USARTD0_TXC_vect) //Transimission complete
148+
{
149+
txISR(&dmxPorts[2]);
150+
}
151+
152+
ISR(USARTE0_TXC_vect) //Transimission complete
153+
{
154+
txISR(&dmxPorts[3]);
155+
}

udp.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,11 +9,11 @@
99
#define ART_DMX 0x5000
1010

1111

12-
static uint8_t eth_type_is_arp_and_my_ip(uint16_t len) {
12+
/*static uint8_t eth_type_is_arp_and_my_ip(uint16_t len) {
1313
return len >= 41 && gPB[ETH_TYPE_H_P] == ETHTYPE_ARP_H_V &&
1414
gPB[ETH_TYPE_L_P] == ETHTYPE_ARP_L_V &&
1515
memcmp(gPB + ETH_ARP_DST_IP_P, EtherCard::myip, IP_LEN) == 0;
16-
}
16+
}*/
1717

1818
void packageLoop(uint16_t len) {
1919
if (len == 0)

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