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Combining S3+C5, or possibly P4+C5 #598
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Hi, @savenlid , Please take a look at ESP-Hosted-MCU https://github.com/espressif/esp-hosted-mcu/ . This is a version of ESP-Hosted that should cater to your requirements. For the S3 + C5 combination, see https://github.com/espressif/esp-hosted-mcu/blob/main/docs/troubleshooting.md#1-esp-host-to-evaluate-already-has-native-wi-fi , which contains instructions on how to disable the Native Wi-Fi on the S3 so it will use ESP-Hosted to communicate with the C5 co-processor. For P4 as a host, you can check https://github.com/espressif/esp-hosted-mcu/blob/main/docs/esp32_p4_function_ev_board.md , which contains instructions for the P4 + C6 combination, but can be changed to the C5. A question: which transport do you plan to use? SPI or SDIO? |
Thanks for helping me. I started reading the links you gave. Regarding SDO versus SPI i am agnostic. I am also trying to get my hands on P4-eval kit and some P4 processors to try this out. |
Yes, please use the GPIOs listed on the web page. The menuconfig values are for a C5 test board and should be updated. Thank you for bringing it to my attention. |
This is correct. ESP32-C5 eco1 can work with SPI. |
Yes. The default config is to use SPI2. No need to change "SPI controller to use".
No. The SPI clock is driven by the SPI master. "Set the SPI clock frequency" refers to setting the SPI clock frequency on the SPI Master. Start with a low CLK frequency (10 MHz or lower), especially if you are connecting the master and co-processor using wires. High frequency CLKs are only stable if you use a PCB for the system. Make sure that both the SPI master and slave are using the same SPI Mode (default is Mode 3). |
After flashing the C5 as a co-processor it keeps repeating the last lines of my text below. spressif\frameworks\esp-idf-master-3\tools\idf.py'"... load:0x4084e9a0,len:0x3680 entry 0x4084c7aa I (23) boot: ESP-IDF v5.5-dev-698-g030c9957db 2nd stage bootloader I (1430) SPI_DRIVER: Hosted SPI queue size: Tx:20 Rx:20 |
Yes, you are correct. The default host configuration for ESP-Hosted is for ESP32-P4 and ESP32-H2. Add |
Yes, this is fine. It is periodically printed by the slave |
The P4 and H2, by default, do not have Wi-Fi with them. that is the reason ESP-Hosted is defaulted for them. ESP32-S3 by default has Wi-Fi. Following link includes a table and legend below, shows which all chipsets are supported: To evaluate ESP32-S3 as ESP-Hosted Slave, you might need to disable default Wi-Fi using https://github.com/espressif/esp-hosted-mcu/blob/main/docs/troubleshooting.md#1-esp-host-to-evaluate-already-has-native-wi-fi |
I managed to get it working in iperf. setting the target gives a less than reassuring output: However, equal to the iperf example it seems to work ok. I (389) os_wrapper_esp: GPIO [17] configuring as Interrupt The ISR I can suspect to be only 1 single ISR for all GPIO, so maybe its what it says. now a question to you 2 gentlemens. My plan is to convert our current system S3 -> S3+C5 (for the sake of 5Ghz wifi capability) Will I succeed or am I a dead man walking ? Will I get the DM9051 in on the SPI3 over the gpio-mux, or will it be possible to run both the C5 and DM9051 on SPI2-port using 2 chip-selects ? Thank you. |
You are referring to this ESP-Hosted SPI setting in You can check
I checked wifi-remote and you are right. esp32c5 is not currently a slave option (probably a temporary removal). As a temporary measure, you can use an earlier version of wifi-remote that has the C5 as an option, like v0.8.5 https://components.espressif.com/components/espressif/esp_wifi_remote/versions/0.8.5?language=en You can use it by running:
Just a check: you are seeing this while using the S3 as the ESP-Hosted host? If yes, please check that you have disabled wifi related settings as mentioned in the link https://github.com/espressif/esp-hosted-mcu/blob/main/docs/troubleshooting.md#1-esp-host-to-evaluate-already-has-native-wi-fi Can you provide the console output from your ESP-Hosted master (S3?) and slave (C5?) from boot-up onwards? |
Remark: as I wrote, its working, but with failure to register an GPIO4 as IRQ. Yes I did disable all wifi in the host (S3 ). Remark: you don't find this text confusing ? I think I slowly start to understand the wordings Question #1 pi@RPI16:~/esp250305/esp-idf/examples/protocols/http_server/simple $ idf.py moni load:0x403cb700,len:0x2f84 I (24) boot: ESP-IDF v5.5-dev-3372-g38628f98b9-dirty 2nd stage bootloader I (345) spi_wrapper: Transport: SPI, Mode:3 Freq:40MHz TxQ:20 RxQ:20 I (369) transport: Add ESP-Hosted channel IF[2]: S[0] Tx[0x4200c58c] Rx[0x420176 a4] I (377) sleep_gpio: Configure to isolate all GPIO pins in sleep state I (2009) transport: Base transport is set-up I (2019) transport: Slave chip Id[12] I (17039) esp_netif_handlers: example_netif_sta ip: 192.168.1.215, mask: 255.255.255.0, gw: 192.168.1.1 Question #2: Will I succeed or am I a dead man walking ? Will I get the DM9051 in on the SPI3 over the gpio-mux, or will it be possible to run both the C5 and DM9051 on SPI2-port using 2 chip-selects ? Thank you |
Regarding this: I (389) os_wrapper_esp: GPIO [17] configuring as Interrupt This is no cause for concern. The spi driver wants to register two GPIOs ( We will look at removing this 'error' in a future update in our wrapper code. |
If C5 eco 2 works with SDIO, how ill the connections be made between S3 and C5 ? |
Hello @savenlid , We have C5+P4 SDIO board, whose schematic we can share to you. Around week or two wait should be better. |
thanks, I wait a couple of weeks, we wont produce until we can get wroom modules with eco2 |
sure thanks. |
Hi again, I was successfully using the S5 as wifi co-processor in the examples/protocols/http_server/simple. But when I wanted to add my DM9051 spi ethernet only SPI 0,1,2 is available, not #3. |
To be honest, The naming has been confusing for us as well, across the chips. Anyway, The instance is what matters at the last. Correlation with TRM and code would give your proper instance and their IO MUX pins. For example, for S3, I can see SPI2 IO_MUX pins here: https://github.com/espressif/esp-idf/blob/master/components/soc/esp32s3/include/soc/spi_pins.h TRM: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf In general, IO_MUX vs GPIO matrix performance difference is only significant for 'Classic ESP32' (due to design that time) What I mean, it doesn't much matter which GPIO you use. even if you use non IO_MUX pin, it would have very small or no performance hit. Further, if you browse through https://docs.espressif.com/projects/esp-idf/en/v5.4.1/esp32s3/api-reference/peripherals/spi_slave.html, you would get required details easily. you can change the chipset of your interest here: |
Important thing despite to know, even if SPI slave states say 60MHz or so in slave mode, We could get it reliable till 40MHz, depending upon the chipset. Obviously higher frequencies (>20MHz) would only make any meaning only if you have PCB. Please refrain from using higher frequencies using jumper cables for SPI, as it would just not work due to signal issues. If you free up some peripheral, it would be usable . for example, you use sdio for hosted. still everything else (apart from that peripheral and GPIOs) from chip is usable (depends how you handle it) for something else. |
thanks, I understand now that picking the acctual pins is not so picky. I also would have preferred 0,1,2,3 throughout all docs. But for the core question, it seems the wifi-hosted is taking port 2 ? |
Hi, @savenlid , Regarding #598 (comment) That Menuconfig for SPI is controlled by https://github.com/espressif/esp-idf/blob/master/examples/common_components/protocol_examples_common/Kconfig.projbuild#L253C1-L259C91 :
Taking a look at https://github.com/espressif/esp-idf/blob/master/components/hal/include/hal/spi_types.h#L18C1-L28C21 : /**
* @brief General purpose SPI Host Controller ID.
*/
typedef enum {
SPI1_HOST = 0, ///< SPI1
SPI2_HOST = 1, ///< SPI2
#if SOC_SPI_PERIPH_NUM > 2
SPI3_HOST = 2, ///< SPI3
#endif
SPI_HOST_MAX, ///< invalid host value
} spi_host_device_t; To use SPI3, select ESP-Hosted is using |
I try to modify some examples to get hosted-wifi and spi-ethernet simultaneously. The example project example/wifi/iperf already have both components (esp_wifi_remote/esp_hosted) already added. idf.py add-dependency "espressif/esp_wifi_remote" Any hints to me why this happens ? only beginning tail if link is shown below. multiple definition of `wifi_init' Another question, why do some examples have a parallel components directory separated from the normal components as described in the docs. Why this parallel component-dir with example_xxxx ? In this doc: The above is a bit confusing to me, is there a legacy reason ? pi@RPI16:~/esps3host/esp-idf/examples/ethernet/basic $ idf.py build ......... x.a -u __cxx_fatal_exception -u uart_vfs_include_dev_init -u usb_serial_jtag_vfs_include_dev_init -u usb_serial_jtag_connection_monitor_include -u esp_vfs_include_console_register -u vfs_include_syscalls_impl -u esp_vfs_include_nullfs_register -u include_esp_phy_override -lphy -lbtbb esp-idf/esp_phy/libesp_phy.a -lphy -lbtbb esp-idf/esp_phy/libesp_phy.a -lphy -lbtbb && : in function `wifi_init':/home/pi/esps3host/esp-idf/examples/ethernet/basic/managed_components/espressif__esp_hosted/host/drivers/rpc/slaveif/rpc_slave_if.c:170: multiple definition of `wifi_init'; esp-idf/espressif__console_cmd_wifi/libespressif__console_cmd_wifi.a(console_wifi.c.obj):/home/pi/esps3host/esp-idf/examples/ethernet/basic/managed_components/espressif__console_cmd_wifi/console_wifi.c:95: first defined here |
Hi, @savenlid #598 (comment) is rather large to digest. Regarding
Could you provide the example project (includes
|
Sorry FYI, I have both spi-eth-dm905 and spi-hosted-c5 working simultaneously now. To the problem #1. #2, why do some examples bring in their own component-lib ( not compatible with the offical/docs) |
Thanks for the summary.
I will check the zip. We think we know what is happening and will verity the fix with your zip file. Will let you know.
ESP-Hosted doesn't handle ethernet configuration, so best to post this question to ESP-IDF. I see you have already posted one question on eth SPI espressif/esp-idf#15919 . You can post this question there also (as a new issue). |
@savenlid Commit espressif/esp-hosted-mcu@6e118a3 should fix this issue:
|
@savenlid , Closing the issue for now. Please feel free to re-open if the fix doesn't work. |
Checklist
Feature description
ESP32-S3 + ESP32-C5, a more complete descripton for this user case
Use cases
We started with the S3 but today we need 5Ghz wifi ( market requierments )
The quickest solution is to hook up the C5 and let it do the wifi ( disable S3 radio )
Could you make some mentioning of this specific combo considering its 2 pcs esp chips involved.
We need the USB of the S3 and the 5Ghz wifi of the C4
Another option would be P4+C5
Or another competitor chip for example STM32H743 + C5
But the low cost of the esp keep all of us trying to use the esp32 chips to solve everything.
Alternatives
P4+C5
STM32+C5
Additional context
No response
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