tests: Ignore deprecation warnings due to RFC 66.

Author: zyp

tests/test_serial.py

@@ -7,6 +7,7 @@
 from amaranth.lib.fifo import SyncFIFO
 from amaranth.lib.wiring import *
 from amaranth.sim import *
+from amaranth._utils import _ignore_deprecated
 
 from amaranth_stdio.serial import *
 
@@ -126,7 +127,8 @@ async def testbench(ctx):
                     self.assertTrue(ctx.get(getattr(dut.err, error)))
 
         sim = Simulator(dut)
-        sim.add_clock(1e-6)
+        with _ignore_deprecated():
+            sim.add_clock(1e-6)
         sim.add_testbench(testbench)
         with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
@@ -200,7 +202,8 @@ async def testbench(ctx):
             self.assertTrue(ctx.get(dut.err.overflow))
 
         sim = Simulator(dut)
-        sim.add_clock(1e-6)
+        with _ignore_deprecated():
+            sim.add_clock(1e-6)
         sim.add_testbench(testbench)
         with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
@@ -228,7 +231,8 @@ async def testbench(ctx):
             self.assertFalse(ctx.get(fifo.r_rdy))
 
         sim = Simulator(m)
-        sim.add_clock(1e-6)
+        with _ignore_deprecated():
+            sim.add_clock(1e-6)
         sim.add_testbench(testbench)
         with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
@@ -329,7 +333,8 @@ async def testbench(ctx):
                 self.assertEqual(ctx.get(tx_o), bit)
 
         sim = Simulator(dut)
-        sim.add_clock(1e-6)
+        with _ignore_deprecated():
+            sim.add_clock(1e-6)
         sim.add_testbench(testbench)
         with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
@@ -411,7 +416,8 @@ async def testbench(ctx):
                 self.assertEqual(ctx.get(dut.o), bit)
 
         sim = Simulator(m)
-        sim.add_clock(1e-6)
+        with _ignore_deprecated():
+            sim.add_clock(1e-6)
         sim.add_testbench(testbench)
         with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
@@ -539,7 +545,8 @@ async def testbench(ctx):
             self.assertEqual(ctx.get(dut.rx.data), 0xAA)
 
         sim = Simulator(m)
-        sim.add_clock(1e-6)
+        with _ignore_deprecated():
+            sim.add_clock(1e-6)
         sim.add_testbench(testbench)
         with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()
@@ -564,7 +571,8 @@ async def testbench(ctx):
             self.assertEqual(ctx.get(dut.rx.data), 0xAA)
 
         sim = Simulator(m)
-        sim.add_clock(1e-6)
+        with _ignore_deprecated():
+            sim.add_clock(1e-6)
         sim.add_testbench(testbench)
         with sim.write_vcd(vcd_file="test.vcd"):
             sim.run()