Skip to content

Commit f21b31e

Browse files
committed
csr.bus: fix incorrect flow of element members of register signatures.
1 parent 1925de0 commit f21b31e

File tree

4 files changed

+14
-14
lines changed

4 files changed

+14
-14
lines changed

amaranth_soc/csr/bus.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -592,12 +592,12 @@ def _check_memory_map(self, memory_map):
592592
raise ValueError("CSR multiplexer memory map cannot have windows")
593593
for reg, reg_name, (reg_start, reg_end) in memory_map.resources():
594594
if not ("element" in reg.signature.members and
595-
reg.signature.members["element"].flow == Out and
595+
reg.signature.members["element"].flow == In and
596596
reg.signature.members["element"].is_signature and
597597
isinstance(reg.signature.members["element"].signature, Element.Signature)):
598598
raise AttributeError(f"Signature of CSR register {reg_name} must have a "
599599
f"csr.Element.Signature member named 'element' and oriented "
600-
f"as wiring.Out")
600+
f"as wiring.In")
601601

602602
def elaborate(self, platform):
603603
m = Module()

amaranth_soc/csr/reg.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -437,7 +437,7 @@ class Register(wiring.Component):
437437
438438
Members
439439
-------
440-
element : :py:`Out(csr.Element.Signature(shape, access))`
440+
element : :py:`In(csr.Element.Signature(shape, access))`
441441
Interface between this :class:`Register` and a CSR bus primitive.
442442
443443
Raises
@@ -522,7 +522,7 @@ def filter_fields(src):
522522
raise ValueError(f"Field {'__'.join(field_path)} is writable, but element access "
523523
f"mode is {access}")
524524

525-
super().__init__({"element": Out(Element.Signature(width, access))})
525+
super().__init__({"element": In(Element.Signature(width, access))})
526526

527527
@property
528528
def field(self):

tests/test_csr_bus.py

+9-9
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212

1313
class _MockRegister(wiring.Component):
1414
def __init__(self, width, access):
15-
super().__init__({"element": Out(csr.Element.Signature(width, access))})
15+
super().__init__({"element": In(csr.Element.Signature(width, access))})
1616

1717

1818
class ElementSignatureTestCase(unittest.TestCase):
@@ -204,32 +204,32 @@ class _Reg(wiring.Component):
204204
pass
205205
# wrong name
206206
map_0 = MemoryMap(addr_width=1, data_width=8)
207-
map_0.add_resource(_Reg({"foo": Out(csr.Element.Signature(8, "rw"))}), name=("a",), size=1)
207+
map_0.add_resource(_Reg({"foo": In(csr.Element.Signature(8, "rw"))}), name=("a",), size=1)
208208
with self.assertRaisesRegex(AttributeError,
209209
r"Signature of CSR register \('a',\) must have a csr\.Element\.Signature member "
210-
r"named 'element' and oriented as wiring\.Out"):
210+
r"named 'element' and oriented as wiring\.In"):
211211
csr.Multiplexer(map_0)
212212
# wrong direction
213213
map_1 = MemoryMap(addr_width=1, data_width=8)
214-
map_1.add_resource(_Reg({"element": In(csr.Element.Signature(8, "rw"))}), name=("a",),
214+
map_1.add_resource(_Reg({"element": Out(csr.Element.Signature(8, "rw"))}), name=("a",),
215215
size=1)
216216
with self.assertRaisesRegex(AttributeError,
217217
r"Signature of CSR register \('a',\) must have a csr\.Element\.Signature member "
218-
r"named 'element' and oriented as wiring\.Out"):
218+
r"named 'element' and oriented as wiring\.In"):
219219
csr.Multiplexer(map_1)
220220
# wrong member type
221221
map_2 = MemoryMap(addr_width=1, data_width=8)
222-
map_2.add_resource(_Reg({"element": Out(unsigned(8))}), name=("a",), size=1)
222+
map_2.add_resource(_Reg({"element": In(unsigned(8))}), name=("a",), size=1)
223223
with self.assertRaisesRegex(AttributeError,
224224
r"Signature of CSR register \('a',\) must have a csr\.Element\.Signature member "
225-
r"named 'element' and oriented as wiring\.Out"):
225+
r"named 'element' and oriented as wiring\.In"):
226226
csr.Multiplexer(map_2)
227227
# wrong member signature
228228
map_3 = MemoryMap(addr_width=1, data_width=8)
229-
map_3.add_resource(_Reg({"element": Out(wiring.Signature({}))}), name=("a",), size=1)
229+
map_3.add_resource(_Reg({"element": In(wiring.Signature({}))}), name=("a",), size=1)
230230
with self.assertRaisesRegex(AttributeError,
231231
r"Signature of CSR register \('a',\) must have a csr\.Element\.Signature member "
232-
r"named 'element' and oriented as wiring\.Out"):
232+
r"named 'element' and oriented as wiring\.In"):
233233
csr.Multiplexer(map_3)
234234

235235
def test_wrong_memory_map_windows(self):

tests/test_csr_wishbone.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
class _MockRegister(wiring.Component):
1515
def __init__(self, width, name):
1616
super().__init__({
17-
"element": Out(csr.Element.Signature(width, "rw")),
17+
"element": In(csr.Element.Signature(width, "rw")),
1818
"r_count": Out(unsigned(8)),
1919
"w_count": Out(unsigned(8)),
2020
"data": Out(width)

0 commit comments

Comments
 (0)