|
| 1 | +from pyb import CAN |
| 2 | +import time |
| 3 | +import errno |
| 4 | + |
| 5 | +# Test the various receive IRQs, including overflow |
| 6 | + |
| 7 | +rx_overflow = False |
| 8 | + |
| 9 | +REASONS = ["received", "full", "overflow"] |
| 10 | + |
| 11 | +# CAN IDs |
| 12 | +ID_SPAM = 0x345 # messages spammed into the receive FIFO |
| 13 | +ID_ACK_OFLOW = 0x055 # message the receiver sends after it's seen an overflow |
| 14 | +ID_AFTER = 0x100 # message the sender sends after the ACK |
| 15 | + |
| 16 | + |
| 17 | +def cb0(bus, reason): |
| 18 | + global rx_overflow |
| 19 | + if reason != 0 and not rx_overflow: |
| 20 | + # exact timing of 'received' callbacks depends on controller type, |
| 21 | + # so only log the other two |
| 22 | + print("rx0 reason", REASONS[reason]) |
| 23 | + if reason == 2: |
| 24 | + rx_overflow = True |
| 25 | + |
| 26 | + |
| 27 | +# Accept all standard IDs on FIFO 0 |
| 28 | +def _enable_accept_all(): |
| 29 | + if hasattr(CAN, "MASK"): # FD-CAN controller |
| 30 | + can.setfilter(0, CAN.RANGE, 0, (0x0, 0x7FF), extframe=False) |
| 31 | + else: |
| 32 | + can.setfilter(0, CAN.MASK16, 0, (0, 0, 0, 0), extframe=False) |
| 33 | + |
| 34 | + |
| 35 | +# Receiver |
| 36 | +def instance0(): |
| 37 | + _enable_accept_all() |
| 38 | + can.rxcallback(0, cb0) |
| 39 | + |
| 40 | + multitest.next() |
| 41 | + multitest.wait("sender ready") |
| 42 | + multitest.broadcast("receiver ready") |
| 43 | + |
| 44 | + while not rx_overflow: |
| 45 | + pass # Resume ASAP after FIFO0 overflows |
| 46 | + |
| 47 | + can.send(b"overflow", ID_ACK_OFLOW) |
| 48 | + |
| 49 | + # drain the receive FIFO, making sure we read at least on ID_SPAM message |
| 50 | + rxed_spam = False |
| 51 | + while can.any(0): |
| 52 | + msg = can.recv(0, timeout=0) |
| 53 | + assert msg[0] == ID_SPAM |
| 54 | + rxed_spam = True |
| 55 | + print("rxed_spam", rxed_spam) |
| 56 | + |
| 57 | + # This should be the one message with ID_AFTER, there may be one or two spam messages as well |
| 58 | + for _ in range(10): |
| 59 | + msg = can.recv(0, timeout=500) |
| 60 | + if msg[0] == ID_AFTER: |
| 61 | + print(msg) |
| 62 | + break |
| 63 | + |
| 64 | + # RX FIFO should be empty now |
| 65 | + print("any", can.any(0)) |
| 66 | + |
| 67 | + |
| 68 | +# Sender |
| 69 | +def instance1(): |
| 70 | + _enable_accept_all() |
| 71 | + multitest.next() |
| 72 | + multitest.broadcast("sender ready") |
| 73 | + multitest.wait("receiver ready") |
| 74 | + |
| 75 | + # Spam out messages until the receiver tells us its RX FIFO is full. |
| 76 | + # |
| 77 | + # The RX FIFO on the receiver can vary from 3 deep (BXCAN) to 25 deep (STM32H7), |
| 78 | + # so we keep sending to it until we see a CAN message on ID_ACK_OFLOW indicating |
| 79 | + # the receiver's FIFO has overflowed |
| 80 | + for i in range(255): |
| 81 | + can.send(bytes([i] * 8), ID_SPAM, timeout=25) |
| 82 | + if can.any(0): |
| 83 | + print(can.recv(0)) # should be ID_ACK_OFLOW |
| 84 | + break |
| 85 | + # on boards like STM32H7 the TX FIFO is really deep, so don't fill it too quickly... |
| 86 | + time.sleep_ms(1) |
| 87 | + |
| 88 | + # give the receiver some time to make space in the FIFO |
| 89 | + time.sleep_ms(200) |
| 90 | + |
| 91 | + # send the final message, the receiver should get this one |
| 92 | + can.send(b"aaaaa", ID_AFTER) |
| 93 | + |
| 94 | + # Sender's RX FIFO should also be empty at this point |
| 95 | + print("any", can.any(0)) |
| 96 | + |
| 97 | + |
| 98 | +can = CAN(1, CAN.NORMAL, baudrate=500_000, sample_point=75) |
0 commit comments