Skip to content

Incorrect pinmux values for SDIO1 on Hi3518E V200 #135

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
relghuar opened this issue May 10, 2025 · 0 comments
Open

Incorrect pinmux values for SDIO1 on Hi3518E V200 #135

relghuar opened this issue May 10, 2025 · 0 comments

Comments

@relghuar
Copy link

Hello,
I'm working on a small camera with hi3518ev200 chip and a wifi module connected to SDIO1. Original stock firmware is a LiteOS clone. I've managed to flash openipc on it, and after investigating both stock firmware and ipctool readouts it seems there are discrepancies in your SDIO1 mappings in EV20Xregs array.
According to "ipctool reginfo" almost all SDIO1_ pins correspond to pinmux register value "0x3", except SDIO1_CARD_POWER_EN which is 0x4. This seems wrong, my stock firmware sets all those values to 0x4. I've replicated that and after some more shenanigans with onboard MCU (which is connected to UART1 and controls PWR and RST pins for wifi) I've finally managed to make wifi card at least present itself on MMC bus (as SDIO_ID 0296:5347 which seems to be in kernel already as Wilc1000 but is NOT actually that card or very much compatible at all :-/).
Anyway, this is pinmux configuration which makes SDIO1_* pins work correctly (at least those used on my board, I'm not sure about SDIO1_CARD_DETECT, SDIO1_CWPR and SDIO1_CARD_POWER_EN but have no reason to doubt the stock firmware setting them right):

muxctrl_reg4 0x200f0010 0x4 GPIO2_0 RMII_CLK VO_CLK SDIO1_CCLK_OUT
muxctrl_reg5 0x200f0014 0x4 GPIO2_1 RMII_TX_EN VO_VS SDIO1_CARD_DETECT
muxctrl_reg6 0x200f0018 0x4 GPIO2_2 RMII_TXD0 VO_DATA5 SDIO1_CWPR
muxctrl_reg7 0x200f001c 0x4 GPIO2_3 RMII_TXD1 VO_DE SDIO1_CDATA1
muxctrl_reg8 0x200f0020 0x4 GPIO2_4 RMII_RX_DV VO_DATA7 SDIO1_CDATA0
muxctrl_reg9 0x200f0024 0x4 GPIO2_5 RMII_RXD0 VO_DATA2 SDIO1_CDATA3
muxctrl_reg10 0x200f0028 0x4 GPIO2_6 RMII_RXD1 VO_DATA3 SDIO1_CCMD
muxctrl_reg11 0x200f002c 0x4 GPIO2_7 EPHY_RST BOOT_SEL VO_HS [SDIO1_CARD_POWER_EN]
muxctrl_reg13 0x200f0034 0x4 GPIO3_0 EPHY_CLK VO_DATA1 SDIO1_CDATA2

Some of these pins I've tested manually in GPIO mode and that seemed to work fine with pinmux reg 0x0, and the default power-on values are 0x1 which would point to RMII/EPHY also being correct, but I have no idea what exactly should be mapped to 0x2/0x3 values.
Is it possible perhaps to insert "UNKNOWN" as 0x3 in there so the SDIO1 pins are in correct position? It's cost me quite some time and frustration wondering why nothing works with original 0x3 values...
If it helps, this is basic "ipctool" output for my board:

root@openipc-hi3518ev200:~# ipctool
mdio busy
mdio busy
---
chip:
  vendor: HiSilicon
  model: 3518EV200
board:
  vendor: OpenIPC
  version: 2.5.04.30
ethernet:
  u-mdio-phyaddr: 0
  phy-id: 0x00000000
  d-mdio-phyaddr: 0
rom:
- type: nor
  block: 64K
  partitions:
    - name: boot
      size: 0x40000
      sha1: 3be1edb5
    - name: env
      size: 0x10000
      sha1: 623a40f5
      contains:
        - name: uboot-env
          offset: 0x0
    - name: kernel
      size: 0x200000
      sha1: c442306d
    - name: rootfs
      size: 0x530000
      sha1: c6fde31d
    - name: rootfs_data
      size: 0x80000
      sha1: 402772f1
  size: 8M
  addr-mode: 3-byte
ram:
  total: 32M
firmware:
  u-boot: "2010.06 (Nov 14 2022 - 19:23:46)"
  kernel: "4.9.37 (Fri May 9 17:50:50 CEST 2025)"
  toolchain: buildroot-gcc-13.3.0
  main-app: majestic

Thanks a lot!
BR,
relghuar

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant